pciide_common.c revision 1.7
1 /* $NetBSD: pciide_common.c,v 1.7 2004/01/03 01:50:53 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.7 2004/01/03 01:50:53 thorpej Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/malloc.h> 83 84 #include <uvm/uvm_extern.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pcidevs.h> 89 #include <dev/pci/pciidereg.h> 90 #include <dev/pci/pciidevar.h> 91 92 #include <dev/ic/wdcreg.h> 93 94 #ifdef WDCDEBUG 95 int wdcdebug_pciide_mask = 0; 96 #endif 97 98 static const char dmaerrfmt[] = 99 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 100 101 /* Default product description for devices not known from this controller */ 102 const struct pciide_product_desc default_product_desc = { 103 0, 104 0, 105 "Generic PCI IDE controller", 106 default_chip_map, 107 }; 108 109 const struct pciide_product_desc * 110 pciide_lookup_product(id, pp) 111 pcireg_t id; 112 const struct pciide_product_desc *pp; 113 { 114 for (; pp->chip_map != NULL; pp++) 115 if (PCI_PRODUCT(id) == pp->ide_product) 116 break; 117 118 if (pp->chip_map == NULL) 119 return NULL; 120 return pp; 121 } 122 123 void 124 pciide_common_attach(sc, pa, pp) 125 struct pciide_softc *sc; 126 struct pci_attach_args *pa; 127 const struct pciide_product_desc *pp; 128 { 129 pci_chipset_tag_t pc = pa->pa_pc; 130 pcitag_t tag = pa->pa_tag; 131 pcireg_t csr; 132 char devinfo[256]; 133 const char *displaydev; 134 135 aprint_naive(": disk controller\n"); 136 aprint_normal("\n"); 137 138 sc->sc_pci_id = pa->pa_id; 139 if (pp == NULL) { 140 /* should only happen for generic pciide devices */ 141 sc->sc_pp = &default_product_desc; 142 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 143 displaydev = devinfo; 144 } else { 145 sc->sc_pp = pp; 146 displaydev = sc->sc_pp->ide_name; 147 } 148 149 /* if displaydev == NULL, printf is done in chip-specific map */ 150 if (displaydev) 151 aprint_normal("%s: %s (rev. 0x%02x)\n", 152 sc->sc_wdcdev.sc_dev.dv_xname, displaydev, 153 PCI_REVISION(pa->pa_class)); 154 155 sc->sc_pc = pa->pa_pc; 156 sc->sc_tag = pa->pa_tag; 157 158 /* Set up DMA defaults; these might be adjusted by chip_map. */ 159 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 160 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 161 162 #ifdef WDCDEBUG 163 if (wdcdebug_pciide_mask & DEBUG_PROBE) 164 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 165 #endif 166 sc->sc_pp->chip_map(sc, pa); 167 168 if (sc->sc_dma_ok) { 169 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 170 csr |= PCI_COMMAND_MASTER_ENABLE; 171 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 172 } 173 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 174 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 175 } 176 177 /* tell whether the chip is enabled or not */ 178 int 179 pciide_chipen(sc, pa) 180 struct pciide_softc *sc; 181 struct pci_attach_args *pa; 182 { 183 pcireg_t csr; 184 185 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 186 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 187 PCI_COMMAND_STATUS_REG); 188 aprint_normal("%s: device disabled (at %s)\n", 189 sc->sc_wdcdev.sc_dev.dv_xname, 190 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 191 "device" : "bridge"); 192 return 0; 193 } 194 return 1; 195 } 196 197 void 198 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 199 struct pci_attach_args *pa; 200 struct pciide_channel *cp; 201 int compatchan; 202 bus_size_t *cmdsizep, *ctlsizep; 203 { 204 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 205 struct wdc_channel *wdc_cp = &cp->wdc_channel; 206 int i; 207 208 cp->compat = 1; 209 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 210 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 211 212 wdc_cp->cmd_iot = pa->pa_iot; 213 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 214 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_baseioh) != 0) { 215 aprint_error("%s: couldn't map %s channel cmd regs\n", 216 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 217 goto bad; 218 } 219 220 wdc_cp->ctl_iot = pa->pa_iot; 221 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 222 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 223 aprint_error("%s: couldn't map %s channel ctl regs\n", 224 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 225 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 226 PCIIDE_COMPAT_CMD_SIZE); 227 goto bad; 228 } 229 230 for (i = 0; i < WDC_NREG; i++) { 231 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, i, 232 i == 0 ? 4 : 1, &wdc_cp->cmd_iohs[i]) != 0) { 233 aprint_error("%s: couldn't subregion %s channel " 234 "cmd regs\n", 235 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 236 goto bad; 237 } 238 } 239 wdc_cp->data32iot = wdc_cp->cmd_iot; 240 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 241 pciide_map_compat_intr(pa, cp, compatchan); 242 return; 243 244 bad: 245 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 246 return; 247 } 248 249 void 250 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 251 struct pci_attach_args * pa; 252 struct pciide_channel *cp; 253 bus_size_t *cmdsizep, *ctlsizep; 254 int (*pci_intr) __P((void *)); 255 { 256 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 257 struct wdc_channel *wdc_cp = &cp->wdc_channel; 258 const char *intrstr; 259 pci_intr_handle_t intrhandle; 260 int i; 261 262 cp->compat = 0; 263 264 if (sc->sc_pci_ih == NULL) { 265 if (pci_intr_map(pa, &intrhandle) != 0) { 266 aprint_error("%s: couldn't map native-PCI interrupt\n", 267 sc->sc_wdcdev.sc_dev.dv_xname); 268 goto bad; 269 } 270 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 271 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 272 intrhandle, IPL_BIO, pci_intr, sc); 273 if (sc->sc_pci_ih != NULL) { 274 aprint_normal("%s: using %s for native-PCI interrupt\n", 275 sc->sc_wdcdev.sc_dev.dv_xname, 276 intrstr ? intrstr : "unknown interrupt"); 277 } else { 278 aprint_error( 279 "%s: couldn't establish native-PCI interrupt", 280 sc->sc_wdcdev.sc_dev.dv_xname); 281 if (intrstr != NULL) 282 aprint_normal(" at %s", intrstr); 283 aprint_normal("\n"); 284 goto bad; 285 } 286 } 287 cp->ih = sc->sc_pci_ih; 288 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 289 PCI_MAPREG_TYPE_IO, 0, 290 &wdc_cp->cmd_iot, &wdc_cp->cmd_baseioh, NULL, cmdsizep) != 0) { 291 aprint_error("%s: couldn't map %s channel cmd regs\n", 292 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 293 goto bad; 294 } 295 296 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 297 PCI_MAPREG_TYPE_IO, 0, 298 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 299 aprint_error("%s: couldn't map %s channel ctl regs\n", 300 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 301 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 302 *cmdsizep); 303 goto bad; 304 } 305 /* 306 * In native mode, 4 bytes of I/O space are mapped for the control 307 * register, the control register is at offset 2. Pass the generic 308 * code a handle for only one byte at the right offset. 309 */ 310 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 311 &wdc_cp->ctl_ioh) != 0) { 312 aprint_error("%s: unable to subregion %s channel ctl regs\n", 313 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 314 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 315 *cmdsizep); 316 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 317 goto bad; 318 } 319 320 for (i = 0; i < WDC_NREG; i++) { 321 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, i, 322 i == 0 ? 4 : 1, &wdc_cp->cmd_iohs[i]) != 0) { 323 aprint_error("%s: couldn't subregion %s channel " 324 "cmd regs\n", 325 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 326 goto bad; 327 } 328 } 329 wdc_cp->data32iot = wdc_cp->cmd_iot; 330 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 331 return; 332 333 bad: 334 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 335 return; 336 } 337 338 void 339 pciide_mapreg_dma(sc, pa) 340 struct pciide_softc *sc; 341 struct pci_attach_args *pa; 342 { 343 pcireg_t maptype; 344 bus_addr_t addr; 345 struct pciide_channel *pc; 346 int reg, chan; 347 bus_size_t size; 348 349 /* 350 * Map DMA registers 351 * 352 * Note that sc_dma_ok is the right variable to test to see if 353 * DMA can be done. If the interface doesn't support DMA, 354 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 355 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 356 * non-zero if the interface supports DMA and the registers 357 * could be mapped. 358 * 359 * XXX Note that despite the fact that the Bus Master IDE specs 360 * XXX say that "The bus master IDE function uses 16 bytes of IO 361 * XXX space," some controllers (at least the United 362 * XXX Microelectronics UM8886BF) place it in memory space. 363 */ 364 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 365 PCIIDE_REG_BUS_MASTER_DMA); 366 367 switch (maptype) { 368 case PCI_MAPREG_TYPE_IO: 369 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 370 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 371 &addr, NULL, NULL) == 0); 372 if (sc->sc_dma_ok == 0) { 373 aprint_normal( 374 ", but unused (couldn't query registers)"); 375 break; 376 } 377 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 378 && addr >= 0x10000) { 379 sc->sc_dma_ok = 0; 380 aprint_normal( 381 ", but unused (registers at unsafe address " 382 "%#lx)", (unsigned long)addr); 383 break; 384 } 385 /* FALLTHROUGH */ 386 387 case PCI_MAPREG_MEM_TYPE_32BIT: 388 sc->sc_dma_ok = (pci_mapreg_map(pa, 389 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 390 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 391 sc->sc_dmat = pa->pa_dmat; 392 if (sc->sc_dma_ok == 0) { 393 aprint_normal(", but unused (couldn't map registers)"); 394 } else { 395 sc->sc_wdcdev.dma_arg = sc; 396 sc->sc_wdcdev.dma_init = pciide_dma_init; 397 sc->sc_wdcdev.dma_start = pciide_dma_start; 398 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 399 } 400 401 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 402 PCIIDE_OPTIONS_NODMA) { 403 aprint_normal( 404 ", but unused (forced off by config file)"); 405 sc->sc_dma_ok = 0; 406 } 407 break; 408 409 default: 410 sc->sc_dma_ok = 0; 411 aprint_normal( 412 ", but unsupported register maptype (0x%x)", maptype); 413 } 414 415 /* 416 * Set up the default handles for the DMA registers. 417 * Just reserve 32 bits for each handle, unless space 418 * doesn't permit it. 419 */ 420 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 421 pc = &sc->pciide_channels[chan]; 422 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 423 size = 4; 424 if (size > (IDEDMA_SCH_OFFSET - reg)) 425 size = IDEDMA_SCH_OFFSET - reg; 426 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 427 IDEDMA_SCH_OFFSET * chan + reg, size, 428 &pc->dma_iohs[reg]) != 0) { 429 sc->sc_dma_ok = 0; 430 aprint_normal(", but can't subregion offset %d " 431 "size %lu", reg, (u_long)size); 432 return; 433 } 434 } 435 } 436 } 437 438 int 439 pciide_compat_intr(arg) 440 void *arg; 441 { 442 struct pciide_channel *cp = arg; 443 444 #ifdef DIAGNOSTIC 445 /* should only be called for a compat channel */ 446 if (cp->compat == 0) 447 panic("pciide compat intr called for non-compat chan %p", cp); 448 #endif 449 return (wdcintr(&cp->wdc_channel)); 450 } 451 452 int 453 pciide_pci_intr(arg) 454 void *arg; 455 { 456 struct pciide_softc *sc = arg; 457 struct pciide_channel *cp; 458 struct wdc_channel *wdc_cp; 459 int i, rv, crv; 460 461 rv = 0; 462 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 463 cp = &sc->pciide_channels[i]; 464 wdc_cp = &cp->wdc_channel; 465 466 /* If a compat channel skip. */ 467 if (cp->compat) 468 continue; 469 /* if this channel not waiting for intr, skip */ 470 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 471 continue; 472 473 crv = wdcintr(wdc_cp); 474 if (crv == 0) 475 ; /* leave rv alone */ 476 else if (crv == 1) 477 rv = 1; /* claim the intr */ 478 else if (rv == 0) /* crv should be -1 in this case */ 479 rv = crv; /* if we've done no better, take it */ 480 } 481 return (rv); 482 } 483 484 void 485 pciide_channel_dma_setup(cp) 486 struct pciide_channel *cp; 487 { 488 int drive; 489 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 490 struct ata_drive_datas *drvp; 491 492 for (drive = 0; drive < 2; drive++) { 493 drvp = &cp->wdc_channel.ch_drive[drive]; 494 /* If no drive, skip */ 495 if ((drvp->drive_flags & DRIVE) == 0) 496 continue; 497 /* setup DMA if needed */ 498 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 499 (drvp->drive_flags & DRIVE_UDMA) == 0) || 500 sc->sc_dma_ok == 0) { 501 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 502 continue; 503 } 504 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 505 != 0) { 506 /* Abort DMA setup */ 507 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 508 continue; 509 } 510 } 511 } 512 513 int 514 pciide_dma_table_setup(sc, channel, drive) 515 struct pciide_softc *sc; 516 int channel, drive; 517 { 518 bus_dma_segment_t seg; 519 int error, rseg; 520 const bus_size_t dma_table_size = 521 sizeof(struct idedma_table) * NIDEDMA_TABLES; 522 struct pciide_dma_maps *dma_maps = 523 &sc->pciide_channels[channel].dma_maps[drive]; 524 525 /* If table was already allocated, just return */ 526 if (dma_maps->dma_table) 527 return 0; 528 529 /* Allocate memory for the DMA tables and map it */ 530 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 531 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 532 BUS_DMA_NOWAIT)) != 0) { 533 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 534 "allocate", drive, error); 535 return error; 536 } 537 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 538 dma_table_size, 539 (caddr_t *)&dma_maps->dma_table, 540 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 541 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 542 "map", drive, error); 543 return error; 544 } 545 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 546 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 547 (unsigned long)seg.ds_addr), DEBUG_PROBE); 548 /* Create and load table DMA map for this disk */ 549 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 550 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 551 &dma_maps->dmamap_table)) != 0) { 552 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 553 "create", drive, error); 554 return error; 555 } 556 if ((error = bus_dmamap_load(sc->sc_dmat, 557 dma_maps->dmamap_table, 558 dma_maps->dma_table, 559 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 560 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 561 "load", drive, error); 562 return error; 563 } 564 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 565 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 566 DEBUG_PROBE); 567 /* Create a xfer DMA map for this drive */ 568 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 569 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 570 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 571 &dma_maps->dmamap_xfer)) != 0) { 572 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 573 "create xfer", drive, error); 574 return error; 575 } 576 return 0; 577 } 578 579 int 580 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 581 void *v; 582 int channel, drive; 583 void *databuf; 584 size_t datalen; 585 int flags; 586 { 587 struct pciide_softc *sc = v; 588 int error, seg; 589 struct pciide_channel *cp = &sc->pciide_channels[channel]; 590 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 591 592 error = bus_dmamap_load(sc->sc_dmat, 593 dma_maps->dmamap_xfer, 594 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 595 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 596 if (error) { 597 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 598 "load xfer", drive, error); 599 return error; 600 } 601 602 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 603 dma_maps->dmamap_xfer->dm_mapsize, 604 (flags & WDC_DMA_READ) ? 605 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 606 607 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 608 #ifdef DIAGNOSTIC 609 /* A segment must not cross a 64k boundary */ 610 { 611 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 612 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 613 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 614 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 615 printf("pciide_dma: segment %d physical addr 0x%lx" 616 " len 0x%lx not properly aligned\n", 617 seg, phys, len); 618 panic("pciide_dma: buf align"); 619 } 620 } 621 #endif 622 dma_maps->dma_table[seg].base_addr = 623 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 624 dma_maps->dma_table[seg].byte_count = 625 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 626 IDEDMA_BYTE_COUNT_MASK); 627 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 628 seg, le32toh(dma_maps->dma_table[seg].byte_count), 629 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 630 631 } 632 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 633 htole32(IDEDMA_BYTE_COUNT_EOT); 634 635 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 636 dma_maps->dmamap_table->dm_mapsize, 637 BUS_DMASYNC_PREWRITE); 638 639 /* Maps are ready. Start DMA function */ 640 #ifdef DIAGNOSTIC 641 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 642 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 643 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 644 panic("pciide_dma_init: table align"); 645 } 646 #endif 647 648 /* Clear status bits */ 649 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 650 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 651 /* Write table addr */ 652 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 653 dma_maps->dmamap_table->dm_segs[0].ds_addr); 654 /* set read/write */ 655 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 656 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 657 /* remember flags */ 658 dma_maps->dma_flags = flags; 659 return 0; 660 } 661 662 void 663 pciide_dma_start(v, channel, drive) 664 void *v; 665 int channel, drive; 666 { 667 struct pciide_softc *sc = v; 668 struct pciide_channel *cp = &sc->pciide_channels[channel]; 669 670 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 671 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 672 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 673 | IDEDMA_CMD_START); 674 } 675 676 int 677 pciide_dma_finish(v, channel, drive, force) 678 void *v; 679 int channel, drive; 680 int force; 681 { 682 struct pciide_softc *sc = v; 683 u_int8_t status; 684 int error = 0; 685 struct pciide_channel *cp = &sc->pciide_channels[channel]; 686 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 687 688 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 689 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 690 DEBUG_XFERS); 691 692 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 693 return WDC_DMAST_NOIRQ; 694 695 /* stop DMA channel */ 696 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 697 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 698 & ~IDEDMA_CMD_START); 699 700 /* Unload the map of the data buffer */ 701 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 702 dma_maps->dmamap_xfer->dm_mapsize, 703 (dma_maps->dma_flags & WDC_DMA_READ) ? 704 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 705 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 706 707 if ((status & IDEDMA_CTL_ERR) != 0) { 708 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 709 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 710 error |= WDC_DMAST_ERR; 711 } 712 713 if ((status & IDEDMA_CTL_INTR) == 0) { 714 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 715 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 716 drive, status); 717 error |= WDC_DMAST_NOIRQ; 718 } 719 720 if ((status & IDEDMA_CTL_ACT) != 0) { 721 /* data underrun, may be a valid condition for ATAPI */ 722 error |= WDC_DMAST_UNDER; 723 } 724 return error; 725 } 726 727 void 728 pciide_irqack(chp) 729 struct wdc_channel *chp; 730 { 731 struct pciide_channel *cp = (struct pciide_channel*)chp; 732 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 733 734 /* clear status bits in IDE DMA registers */ 735 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 736 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 737 } 738 739 /* some common code used by several chip_map */ 740 int 741 pciide_chansetup(sc, channel, interface) 742 struct pciide_softc *sc; 743 int channel; 744 pcireg_t interface; 745 { 746 struct pciide_channel *cp = &sc->pciide_channels[channel]; 747 sc->wdc_chanarray[channel] = &cp->wdc_channel; 748 cp->name = PCIIDE_CHANNEL_NAME(channel); 749 cp->wdc_channel.channel = channel; 750 cp->wdc_channel.wdc = &sc->sc_wdcdev; 751 cp->wdc_channel.ch_queue = 752 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 753 if (cp->wdc_channel.ch_queue == NULL) { 754 aprint_error("%s %s channel: " 755 "can't allocate memory for command queue", 756 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 757 return 0; 758 } 759 aprint_normal("%s: %s channel %s to %s mode\n", 760 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 761 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 762 "configured" : "wired", 763 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 764 "native-PCI" : "compatibility"); 765 return 1; 766 } 767 768 /* some common code used by several chip channel_map */ 769 void 770 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 771 struct pci_attach_args *pa; 772 struct pciide_channel *cp; 773 pcireg_t interface; 774 bus_size_t *cmdsizep, *ctlsizep; 775 int (*pci_intr) __P((void *)); 776 { 777 struct wdc_channel *wdc_cp = &cp->wdc_channel; 778 779 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 780 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr); 781 else 782 pciide_mapregs_compat(pa, cp, wdc_cp->channel, cmdsizep, 783 ctlsizep); 784 wdcattach(wdc_cp); 785 } 786 787 /* 788 * generic code to map the compat intr. 789 */ 790 void 791 pciide_map_compat_intr(pa, cp, compatchan) 792 struct pci_attach_args *pa; 793 struct pciide_channel *cp; 794 int compatchan; 795 { 796 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 797 798 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 799 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 800 pa, compatchan, pciide_compat_intr, cp); 801 if (cp->ih == NULL) { 802 #endif 803 aprint_error("%s: no compatibility interrupt for use by %s " 804 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 805 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 806 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 807 } 808 #endif 809 } 810 811 void 812 default_chip_map(sc, pa) 813 struct pciide_softc *sc; 814 struct pci_attach_args *pa; 815 { 816 struct pciide_channel *cp; 817 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 818 pcireg_t csr; 819 int channel, drive; 820 struct ata_drive_datas *drvp; 821 u_int8_t idedma_ctl; 822 bus_size_t cmdsize, ctlsize; 823 char *failreason; 824 825 if (pciide_chipen(sc, pa) == 0) 826 return; 827 828 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 829 aprint_normal("%s: bus-master DMA support present", 830 sc->sc_wdcdev.sc_dev.dv_xname); 831 if (sc->sc_pp == &default_product_desc && 832 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 833 PCIIDE_OPTIONS_DMA) == 0) { 834 aprint_normal(", but unused (no driver support)"); 835 sc->sc_dma_ok = 0; 836 } else { 837 pciide_mapreg_dma(sc, pa); 838 if (sc->sc_dma_ok != 0) 839 aprint_normal(", used without full driver " 840 "support"); 841 } 842 } else { 843 aprint_normal("%s: hardware does not support DMA", 844 sc->sc_wdcdev.sc_dev.dv_xname); 845 sc->sc_dma_ok = 0; 846 } 847 aprint_normal("\n"); 848 if (sc->sc_dma_ok) { 849 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 850 sc->sc_wdcdev.irqack = pciide_irqack; 851 } 852 sc->sc_wdcdev.PIO_cap = 0; 853 sc->sc_wdcdev.DMA_cap = 0; 854 855 sc->sc_wdcdev.channels = sc->wdc_chanarray; 856 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 857 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 858 859 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 860 cp = &sc->pciide_channels[channel]; 861 if (pciide_chansetup(sc, channel, interface) == 0) 862 continue; 863 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 864 pciide_pci_intr); 865 if (cp->wdc_channel.ch_flags & WDCF_DISABLED) 866 continue; 867 /* 868 * Check to see if something appears to be there. 869 */ 870 failreason = NULL; 871 /* 872 * In native mode, always enable the controller. It's 873 * not possible to have an ISA board using the same address 874 * anyway. 875 */ 876 if (interface & PCIIDE_INTERFACE_PCI(channel)) 877 goto next; 878 if (!wdcprobe(&cp->wdc_channel)) { 879 failreason = "not responding; disabled or no drives?"; 880 goto next; 881 } 882 /* 883 * Now, make sure it's actually attributable to this PCI IDE 884 * channel by trying to access the channel again while the 885 * PCI IDE controller's I/O space is disabled. (If the 886 * channel no longer appears to be there, it belongs to 887 * this controller.) YUCK! 888 */ 889 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 890 PCI_COMMAND_STATUS_REG); 891 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 892 csr & ~PCI_COMMAND_IO_ENABLE); 893 if (wdcprobe(&cp->wdc_channel)) 894 failreason = "other hardware responding at addresses"; 895 pci_conf_write(sc->sc_pc, sc->sc_tag, 896 PCI_COMMAND_STATUS_REG, csr); 897 next: 898 if (failreason) { 899 aprint_error("%s: %s channel ignored (%s)\n", 900 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 901 failreason); 902 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 903 bus_space_unmap(cp->wdc_channel.cmd_iot, 904 cp->wdc_channel.cmd_baseioh, cmdsize); 905 bus_space_unmap(cp->wdc_channel.ctl_iot, 906 cp->wdc_channel.ctl_ioh, ctlsize); 907 908 } 909 } 910 911 if (sc->sc_dma_ok == 0) 912 return; 913 914 /* Allocate DMA maps */ 915 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 916 idedma_ctl = 0; 917 cp = &sc->pciide_channels[channel]; 918 for (drive = 0; drive < 2; drive++) { 919 drvp = &cp->wdc_channel.ch_drive[drive]; 920 /* If no drive, skip */ 921 if ((drvp->drive_flags & DRIVE) == 0) 922 continue; 923 if ((drvp->drive_flags & DRIVE_DMA) == 0) 924 continue; 925 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 926 /* Abort DMA setup */ 927 aprint_error( 928 "%s:%d:%d: can't allocate DMA maps, " 929 "using PIO transfers\n", 930 sc->sc_wdcdev.sc_dev.dv_xname, 931 channel, drive); 932 drvp->drive_flags &= ~DRIVE_DMA; 933 } 934 aprint_normal("%s:%d:%d: using DMA data transfers\n", 935 sc->sc_wdcdev.sc_dev.dv_xname, 936 channel, drive); 937 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 938 } 939 if (idedma_ctl != 0) { 940 /* Add software bits in status register */ 941 bus_space_write_1(sc->sc_dma_iot, 942 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 943 } 944 } 945 } 946 947 void 948 sata_setup_channel(chp) 949 struct wdc_channel *chp; 950 { 951 struct ata_drive_datas *drvp; 952 int drive; 953 u_int32_t idedma_ctl; 954 struct pciide_channel *cp = (struct pciide_channel*)chp; 955 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 956 957 /* setup DMA if needed */ 958 pciide_channel_dma_setup(cp); 959 960 idedma_ctl = 0; 961 962 for (drive = 0; drive < 2; drive++) { 963 drvp = &chp->ch_drive[drive]; 964 /* If no drive, skip */ 965 if ((drvp->drive_flags & DRIVE) == 0) 966 continue; 967 if (drvp->drive_flags & DRIVE_UDMA) { 968 /* use Ultra/DMA */ 969 drvp->drive_flags &= ~DRIVE_DMA; 970 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 971 } else if (drvp->drive_flags & DRIVE_DMA) { 972 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 973 } 974 } 975 976 /* 977 * Nothing to do to setup modes; it is meaningless in S-ATA 978 * (but many S-ATA drives still want to get the SET_FEATURE 979 * command). 980 */ 981 if (idedma_ctl != 0) { 982 /* Add software bits in status register */ 983 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 984 idedma_ctl); 985 } 986 } 987
Indexes created Thu Oct 02 07:10:07 GMT 2025