pciide_common.c revision 1.8.2.2
1 /* $NetBSD: pciide_common.c,v 1.8.2.2 2004/06/05 05:00:14 jmc Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.8.2.2 2004/06/05 05:00:14 jmc Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/malloc.h> 83 84 #include <uvm/uvm_extern.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pcidevs.h> 89 #include <dev/pci/pciidereg.h> 90 #include <dev/pci/pciidevar.h> 91 92 #include <dev/ic/wdcreg.h> 93 94 #ifdef WDCDEBUG 95 int wdcdebug_pciide_mask = 0; 96 #endif 97 98 static const char dmaerrfmt[] = 99 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 100 101 /* Default product description for devices not known from this controller */ 102 const struct pciide_product_desc default_product_desc = { 103 0, 104 0, 105 "Generic PCI IDE controller", 106 default_chip_map, 107 }; 108 109 const struct pciide_product_desc * 110 pciide_lookup_product(id, pp) 111 pcireg_t id; 112 const struct pciide_product_desc *pp; 113 { 114 for (; pp->chip_map != NULL; pp++) 115 if (PCI_PRODUCT(id) == pp->ide_product) 116 break; 117 118 if (pp->chip_map == NULL) 119 return NULL; 120 return pp; 121 } 122 123 void 124 pciide_common_attach(sc, pa, pp) 125 struct pciide_softc *sc; 126 struct pci_attach_args *pa; 127 const struct pciide_product_desc *pp; 128 { 129 pci_chipset_tag_t pc = pa->pa_pc; 130 pcitag_t tag = pa->pa_tag; 131 pcireg_t csr; 132 char devinfo[256]; 133 const char *displaydev; 134 135 aprint_naive(": disk controller\n"); 136 aprint_normal("\n"); 137 138 sc->sc_pci_id = pa->pa_id; 139 if (pp == NULL) { 140 /* should only happen for generic pciide devices */ 141 sc->sc_pp = &default_product_desc; 142 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 143 displaydev = devinfo; 144 } else { 145 sc->sc_pp = pp; 146 displaydev = sc->sc_pp->ide_name; 147 } 148 149 /* if displaydev == NULL, printf is done in chip-specific map */ 150 if (displaydev) 151 aprint_normal("%s: %s (rev. 0x%02x)\n", 152 sc->sc_wdcdev.sc_dev.dv_xname, displaydev, 153 PCI_REVISION(pa->pa_class)); 154 155 sc->sc_pc = pa->pa_pc; 156 sc->sc_tag = pa->pa_tag; 157 158 /* Set up DMA defaults; these might be adjusted by chip_map. */ 159 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 160 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 161 162 #ifdef WDCDEBUG 163 if (wdcdebug_pciide_mask & DEBUG_PROBE) 164 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 165 #endif 166 sc->sc_pp->chip_map(sc, pa); 167 168 if (sc->sc_dma_ok) { 169 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 170 csr |= PCI_COMMAND_MASTER_ENABLE; 171 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 172 } 173 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 174 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 175 } 176 177 /* tell whether the chip is enabled or not */ 178 int 179 pciide_chipen(sc, pa) 180 struct pciide_softc *sc; 181 struct pci_attach_args *pa; 182 { 183 pcireg_t csr; 184 185 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 186 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 187 PCI_COMMAND_STATUS_REG); 188 aprint_normal("%s: device disabled (at %s)\n", 189 sc->sc_wdcdev.sc_dev.dv_xname, 190 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 191 "device" : "bridge"); 192 return 0; 193 } 194 return 1; 195 } 196 197 void 198 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 199 struct pci_attach_args *pa; 200 struct pciide_channel *cp; 201 int compatchan; 202 bus_size_t *cmdsizep, *ctlsizep; 203 { 204 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 205 struct wdc_channel *wdc_cp = &cp->wdc_channel; 206 int i; 207 208 cp->compat = 1; 209 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 210 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 211 212 wdc_cp->cmd_iot = pa->pa_iot; 213 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 214 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_baseioh) != 0) { 215 aprint_error("%s: couldn't map %s channel cmd regs\n", 216 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 217 goto bad; 218 } 219 220 wdc_cp->ctl_iot = pa->pa_iot; 221 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 222 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 223 aprint_error("%s: couldn't map %s channel ctl regs\n", 224 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 225 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 226 PCIIDE_COMPAT_CMD_SIZE); 227 goto bad; 228 } 229 230 for (i = 0; i < WDC_NREG; i++) { 231 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, i, 232 i == 0 ? 4 : 1, &wdc_cp->cmd_iohs[i]) != 0) { 233 aprint_error("%s: couldn't subregion %s channel " 234 "cmd regs\n", 235 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 236 goto bad; 237 } 238 } 239 wdc_cp->data32iot = wdc_cp->cmd_iot; 240 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 241 pciide_map_compat_intr(pa, cp, compatchan); 242 return; 243 244 bad: 245 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 246 return; 247 } 248 249 void 250 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 251 struct pci_attach_args * pa; 252 struct pciide_channel *cp; 253 bus_size_t *cmdsizep, *ctlsizep; 254 int (*pci_intr) __P((void *)); 255 { 256 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 257 struct wdc_channel *wdc_cp = &cp->wdc_channel; 258 const char *intrstr; 259 pci_intr_handle_t intrhandle; 260 int i; 261 262 cp->compat = 0; 263 264 if (sc->sc_pci_ih == NULL) { 265 if (pci_intr_map(pa, &intrhandle) != 0) { 266 aprint_error("%s: couldn't map native-PCI interrupt\n", 267 sc->sc_wdcdev.sc_dev.dv_xname); 268 goto bad; 269 } 270 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 271 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 272 intrhandle, IPL_BIO, pci_intr, sc); 273 if (sc->sc_pci_ih != NULL) { 274 aprint_normal("%s: using %s for native-PCI interrupt\n", 275 sc->sc_wdcdev.sc_dev.dv_xname, 276 intrstr ? intrstr : "unknown interrupt"); 277 } else { 278 aprint_error( 279 "%s: couldn't establish native-PCI interrupt", 280 sc->sc_wdcdev.sc_dev.dv_xname); 281 if (intrstr != NULL) 282 aprint_normal(" at %s", intrstr); 283 aprint_normal("\n"); 284 goto bad; 285 } 286 } 287 cp->ih = sc->sc_pci_ih; 288 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), 289 PCI_MAPREG_TYPE_IO, 0, 290 &wdc_cp->cmd_iot, &wdc_cp->cmd_baseioh, NULL, cmdsizep) != 0) { 291 aprint_error("%s: couldn't map %s channel cmd regs\n", 292 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 293 goto bad; 294 } 295 296 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), 297 PCI_MAPREG_TYPE_IO, 0, 298 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 299 aprint_error("%s: couldn't map %s channel ctl regs\n", 300 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 301 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 302 *cmdsizep); 303 goto bad; 304 } 305 /* 306 * In native mode, 4 bytes of I/O space are mapped for the control 307 * register, the control register is at offset 2. Pass the generic 308 * code a handle for only one byte at the right offset. 309 */ 310 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 311 &wdc_cp->ctl_ioh) != 0) { 312 aprint_error("%s: unable to subregion %s channel ctl regs\n", 313 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 314 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 315 *cmdsizep); 316 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 317 goto bad; 318 } 319 320 for (i = 0; i < WDC_NREG; i++) { 321 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, i, 322 i == 0 ? 4 : 1, &wdc_cp->cmd_iohs[i]) != 0) { 323 aprint_error("%s: couldn't subregion %s channel " 324 "cmd regs\n", 325 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 326 goto bad; 327 } 328 } 329 wdc_cp->data32iot = wdc_cp->cmd_iot; 330 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 331 return; 332 333 bad: 334 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 335 return; 336 } 337 338 void 339 pciide_mapreg_dma(sc, pa) 340 struct pciide_softc *sc; 341 struct pci_attach_args *pa; 342 { 343 pcireg_t maptype; 344 bus_addr_t addr; 345 struct pciide_channel *pc; 346 int reg, chan; 347 bus_size_t size; 348 349 /* 350 * Map DMA registers 351 * 352 * Note that sc_dma_ok is the right variable to test to see if 353 * DMA can be done. If the interface doesn't support DMA, 354 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 355 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 356 * non-zero if the interface supports DMA and the registers 357 * could be mapped. 358 * 359 * XXX Note that despite the fact that the Bus Master IDE specs 360 * XXX say that "The bus master IDE function uses 16 bytes of IO 361 * XXX space," some controllers (at least the United 362 * XXX Microelectronics UM8886BF) place it in memory space. 363 */ 364 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 365 PCIIDE_REG_BUS_MASTER_DMA); 366 367 switch (maptype) { 368 case PCI_MAPREG_TYPE_IO: 369 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 370 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 371 &addr, NULL, NULL) == 0); 372 if (sc->sc_dma_ok == 0) { 373 aprint_normal( 374 ", but unused (couldn't query registers)"); 375 break; 376 } 377 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 378 && addr >= 0x10000) { 379 sc->sc_dma_ok = 0; 380 aprint_normal( 381 ", but unused (registers at unsafe address " 382 "%#lx)", (unsigned long)addr); 383 break; 384 } 385 /* FALLTHROUGH */ 386 387 case PCI_MAPREG_MEM_TYPE_32BIT: 388 sc->sc_dma_ok = (pci_mapreg_map(pa, 389 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 390 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 391 sc->sc_dmat = pa->pa_dmat; 392 if (sc->sc_dma_ok == 0) { 393 aprint_normal(", but unused (couldn't map registers)"); 394 } else { 395 sc->sc_wdcdev.dma_arg = sc; 396 sc->sc_wdcdev.dma_init = pciide_dma_init; 397 sc->sc_wdcdev.dma_start = pciide_dma_start; 398 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 399 } 400 401 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 402 PCIIDE_OPTIONS_NODMA) { 403 aprint_normal( 404 ", but unused (forced off by config file)"); 405 sc->sc_dma_ok = 0; 406 } 407 break; 408 409 default: 410 sc->sc_dma_ok = 0; 411 aprint_normal( 412 ", but unsupported register maptype (0x%x)", maptype); 413 } 414 415 if (sc->sc_dma_ok == 0) 416 return; 417 418 /* 419 * Set up the default handles for the DMA registers. 420 * Just reserve 32 bits for each handle, unless space 421 * doesn't permit it. 422 */ 423 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 424 pc = &sc->pciide_channels[chan]; 425 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 426 size = 4; 427 if (size > (IDEDMA_SCH_OFFSET - reg)) 428 size = IDEDMA_SCH_OFFSET - reg; 429 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 430 IDEDMA_SCH_OFFSET * chan + reg, size, 431 &pc->dma_iohs[reg]) != 0) { 432 sc->sc_dma_ok = 0; 433 aprint_normal(", but can't subregion offset %d " 434 "size %lu", reg, (u_long)size); 435 return; 436 } 437 } 438 } 439 } 440 441 int 442 pciide_compat_intr(arg) 443 void *arg; 444 { 445 struct pciide_channel *cp = arg; 446 447 #ifdef DIAGNOSTIC 448 /* should only be called for a compat channel */ 449 if (cp->compat == 0) 450 panic("pciide compat intr called for non-compat chan %p", cp); 451 #endif 452 return (wdcintr(&cp->wdc_channel)); 453 } 454 455 int 456 pciide_pci_intr(arg) 457 void *arg; 458 { 459 struct pciide_softc *sc = arg; 460 struct pciide_channel *cp; 461 struct wdc_channel *wdc_cp; 462 int i, rv, crv; 463 464 rv = 0; 465 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 466 cp = &sc->pciide_channels[i]; 467 wdc_cp = &cp->wdc_channel; 468 469 /* If a compat channel skip. */ 470 if (cp->compat) 471 continue; 472 /* if this channel not waiting for intr, skip */ 473 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 474 continue; 475 476 crv = wdcintr(wdc_cp); 477 if (crv == 0) 478 ; /* leave rv alone */ 479 else if (crv == 1) 480 rv = 1; /* claim the intr */ 481 else if (rv == 0) /* crv should be -1 in this case */ 482 rv = crv; /* if we've done no better, take it */ 483 } 484 return (rv); 485 } 486 487 void 488 pciide_channel_dma_setup(cp) 489 struct pciide_channel *cp; 490 { 491 int drive; 492 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 493 struct ata_drive_datas *drvp; 494 495 for (drive = 0; drive < 2; drive++) { 496 drvp = &cp->wdc_channel.ch_drive[drive]; 497 /* If no drive, skip */ 498 if ((drvp->drive_flags & DRIVE) == 0) 499 continue; 500 /* setup DMA if needed */ 501 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 502 (drvp->drive_flags & DRIVE_UDMA) == 0) || 503 sc->sc_dma_ok == 0) { 504 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 505 continue; 506 } 507 if (pciide_dma_table_setup(sc, cp->wdc_channel.ch_channel, 508 drive) != 0) { 509 /* Abort DMA setup */ 510 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 511 continue; 512 } 513 } 514 } 515 516 int 517 pciide_dma_table_setup(sc, channel, drive) 518 struct pciide_softc *sc; 519 int channel, drive; 520 { 521 bus_dma_segment_t seg; 522 int error, rseg; 523 const bus_size_t dma_table_size = 524 sizeof(struct idedma_table) * NIDEDMA_TABLES; 525 struct pciide_dma_maps *dma_maps = 526 &sc->pciide_channels[channel].dma_maps[drive]; 527 528 /* If table was already allocated, just return */ 529 if (dma_maps->dma_table) 530 return 0; 531 532 /* Allocate memory for the DMA tables and map it */ 533 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 534 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 535 BUS_DMA_NOWAIT)) != 0) { 536 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 537 "allocate", drive, error); 538 return error; 539 } 540 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 541 dma_table_size, 542 (caddr_t *)&dma_maps->dma_table, 543 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 544 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 545 "map", drive, error); 546 return error; 547 } 548 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 549 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 550 (unsigned long)seg.ds_addr), DEBUG_PROBE); 551 /* Create and load table DMA map for this disk */ 552 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 553 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 554 &dma_maps->dmamap_table)) != 0) { 555 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 556 "create", drive, error); 557 return error; 558 } 559 if ((error = bus_dmamap_load(sc->sc_dmat, 560 dma_maps->dmamap_table, 561 dma_maps->dma_table, 562 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 563 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 564 "load", drive, error); 565 return error; 566 } 567 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 568 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 569 DEBUG_PROBE); 570 /* Create a xfer DMA map for this drive */ 571 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 572 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 573 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 574 &dma_maps->dmamap_xfer)) != 0) { 575 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 576 "create xfer", drive, error); 577 return error; 578 } 579 return 0; 580 } 581 582 int 583 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 584 void *v; 585 int channel, drive; 586 void *databuf; 587 size_t datalen; 588 int flags; 589 { 590 struct pciide_softc *sc = v; 591 int error, seg; 592 struct pciide_channel *cp = &sc->pciide_channels[channel]; 593 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 594 595 error = bus_dmamap_load(sc->sc_dmat, 596 dma_maps->dmamap_xfer, 597 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 598 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 599 if (error) { 600 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 601 "load xfer", drive, error); 602 return error; 603 } 604 605 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 606 dma_maps->dmamap_xfer->dm_mapsize, 607 (flags & WDC_DMA_READ) ? 608 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 609 610 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 611 #ifdef DIAGNOSTIC 612 /* A segment must not cross a 64k boundary */ 613 { 614 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 615 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 616 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 617 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 618 printf("pciide_dma: segment %d physical addr 0x%lx" 619 " len 0x%lx not properly aligned\n", 620 seg, phys, len); 621 panic("pciide_dma: buf align"); 622 } 623 } 624 #endif 625 dma_maps->dma_table[seg].base_addr = 626 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 627 dma_maps->dma_table[seg].byte_count = 628 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 629 IDEDMA_BYTE_COUNT_MASK); 630 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 631 seg, le32toh(dma_maps->dma_table[seg].byte_count), 632 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 633 634 } 635 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 636 htole32(IDEDMA_BYTE_COUNT_EOT); 637 638 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 639 dma_maps->dmamap_table->dm_mapsize, 640 BUS_DMASYNC_PREWRITE); 641 642 /* Maps are ready. Start DMA function */ 643 #ifdef DIAGNOSTIC 644 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 645 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 646 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 647 panic("pciide_dma_init: table align"); 648 } 649 #endif 650 651 /* Clear status bits */ 652 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 653 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 654 /* Write table addr */ 655 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 656 dma_maps->dmamap_table->dm_segs[0].ds_addr); 657 /* set read/write */ 658 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 659 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 660 /* remember flags */ 661 dma_maps->dma_flags = flags; 662 return 0; 663 } 664 665 void 666 pciide_dma_start(v, channel, drive) 667 void *v; 668 int channel, drive; 669 { 670 struct pciide_softc *sc = v; 671 struct pciide_channel *cp = &sc->pciide_channels[channel]; 672 673 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 674 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 675 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 676 | IDEDMA_CMD_START); 677 } 678 679 int 680 pciide_dma_finish(v, channel, drive, force) 681 void *v; 682 int channel, drive; 683 int force; 684 { 685 struct pciide_softc *sc = v; 686 u_int8_t status; 687 int error = 0; 688 struct pciide_channel *cp = &sc->pciide_channels[channel]; 689 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 690 691 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 692 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 693 DEBUG_XFERS); 694 695 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 696 return WDC_DMAST_NOIRQ; 697 698 /* stop DMA channel */ 699 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 700 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 701 & ~IDEDMA_CMD_START); 702 703 /* Unload the map of the data buffer */ 704 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 705 dma_maps->dmamap_xfer->dm_mapsize, 706 (dma_maps->dma_flags & WDC_DMA_READ) ? 707 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 708 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 709 710 if ((status & IDEDMA_CTL_ERR) != 0) { 711 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 712 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 713 error |= WDC_DMAST_ERR; 714 } 715 716 if ((status & IDEDMA_CTL_INTR) == 0) { 717 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 718 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 719 drive, status); 720 error |= WDC_DMAST_NOIRQ; 721 } 722 723 if ((status & IDEDMA_CTL_ACT) != 0) { 724 /* data underrun, may be a valid condition for ATAPI */ 725 error |= WDC_DMAST_UNDER; 726 } 727 return error; 728 } 729 730 void 731 pciide_irqack(chp) 732 struct wdc_channel *chp; 733 { 734 struct pciide_channel *cp = (struct pciide_channel*)chp; 735 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 736 737 /* clear status bits in IDE DMA registers */ 738 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 739 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 740 } 741 742 /* some common code used by several chip_map */ 743 int 744 pciide_chansetup(sc, channel, interface) 745 struct pciide_softc *sc; 746 int channel; 747 pcireg_t interface; 748 { 749 struct pciide_channel *cp = &sc->pciide_channels[channel]; 750 sc->wdc_chanarray[channel] = &cp->wdc_channel; 751 cp->name = PCIIDE_CHANNEL_NAME(channel); 752 cp->wdc_channel.ch_channel = channel; 753 cp->wdc_channel.ch_wdc = &sc->sc_wdcdev; 754 cp->wdc_channel.ch_queue = 755 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 756 if (cp->wdc_channel.ch_queue == NULL) { 757 aprint_error("%s %s channel: " 758 "can't allocate memory for command queue", 759 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 760 return 0; 761 } 762 aprint_normal("%s: %s channel %s to %s mode\n", 763 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 764 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 765 "configured" : "wired", 766 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 767 "native-PCI" : "compatibility"); 768 return 1; 769 } 770 771 /* some common code used by several chip channel_map */ 772 void 773 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 774 struct pci_attach_args *pa; 775 struct pciide_channel *cp; 776 pcireg_t interface; 777 bus_size_t *cmdsizep, *ctlsizep; 778 int (*pci_intr) __P((void *)); 779 { 780 struct wdc_channel *wdc_cp = &cp->wdc_channel; 781 782 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) 783 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr); 784 else 785 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 786 ctlsizep); 787 wdcattach(wdc_cp); 788 } 789 790 /* 791 * generic code to map the compat intr. 792 */ 793 void 794 pciide_map_compat_intr(pa, cp, compatchan) 795 struct pci_attach_args *pa; 796 struct pciide_channel *cp; 797 int compatchan; 798 { 799 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 800 801 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 802 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 803 pa, compatchan, pciide_compat_intr, cp); 804 if (cp->ih == NULL) { 805 #endif 806 aprint_error("%s: no compatibility interrupt for use by %s " 807 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 808 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 809 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 810 } 811 #endif 812 } 813 814 void 815 default_chip_map(sc, pa) 816 struct pciide_softc *sc; 817 struct pci_attach_args *pa; 818 { 819 struct pciide_channel *cp; 820 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 821 pcireg_t csr; 822 int channel, drive; 823 struct ata_drive_datas *drvp; 824 u_int8_t idedma_ctl; 825 bus_size_t cmdsize, ctlsize; 826 char *failreason; 827 828 if (pciide_chipen(sc, pa) == 0) 829 return; 830 831 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 832 aprint_normal("%s: bus-master DMA support present", 833 sc->sc_wdcdev.sc_dev.dv_xname); 834 if (sc->sc_pp == &default_product_desc && 835 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 836 PCIIDE_OPTIONS_DMA) == 0) { 837 aprint_normal(", but unused (no driver support)"); 838 sc->sc_dma_ok = 0; 839 } else { 840 pciide_mapreg_dma(sc, pa); 841 if (sc->sc_dma_ok != 0) 842 aprint_normal(", used without full driver " 843 "support"); 844 } 845 } else { 846 aprint_normal("%s: hardware does not support DMA", 847 sc->sc_wdcdev.sc_dev.dv_xname); 848 sc->sc_dma_ok = 0; 849 } 850 aprint_normal("\n"); 851 if (sc->sc_dma_ok) { 852 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 853 sc->sc_wdcdev.irqack = pciide_irqack; 854 } 855 sc->sc_wdcdev.PIO_cap = 0; 856 sc->sc_wdcdev.DMA_cap = 0; 857 858 sc->sc_wdcdev.channels = sc->wdc_chanarray; 859 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 860 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 861 862 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 863 cp = &sc->pciide_channels[channel]; 864 if (pciide_chansetup(sc, channel, interface) == 0) 865 continue; 866 if (interface & PCIIDE_INTERFACE_PCI(channel)) 867 pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 868 pciide_pci_intr); 869 else 870 pciide_mapregs_compat(pa, cp, 871 cp->wdc_channel.ch_channel, &cmdsize, &ctlsize); 872 if (cp->wdc_channel.ch_flags & WDCF_DISABLED) 873 continue; 874 /* 875 * Check to see if something appears to be there. 876 */ 877 failreason = NULL; 878 /* 879 * In native mode, always enable the controller. It's 880 * not possible to have an ISA board using the same address 881 * anyway. 882 */ 883 if (interface & PCIIDE_INTERFACE_PCI(channel)) 884 goto next; 885 if (!wdcprobe(&cp->wdc_channel)) { 886 failreason = "not responding; disabled or no drives?"; 887 goto next; 888 } 889 /* 890 * Now, make sure it's actually attributable to this PCI IDE 891 * channel by trying to access the channel again while the 892 * PCI IDE controller's I/O space is disabled. (If the 893 * channel no longer appears to be there, it belongs to 894 * this controller.) YUCK! 895 */ 896 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 897 PCI_COMMAND_STATUS_REG); 898 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 899 csr & ~PCI_COMMAND_IO_ENABLE); 900 if (wdcprobe(&cp->wdc_channel)) 901 failreason = "other hardware responding at addresses"; 902 pci_conf_write(sc->sc_pc, sc->sc_tag, 903 PCI_COMMAND_STATUS_REG, csr); 904 next: 905 if (failreason) { 906 aprint_error("%s: %s channel ignored (%s)\n", 907 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 908 failreason); 909 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 910 bus_space_unmap(cp->wdc_channel.cmd_iot, 911 cp->wdc_channel.cmd_baseioh, cmdsize); 912 bus_space_unmap(cp->wdc_channel.ctl_iot, 913 cp->wdc_channel.ctl_ioh, ctlsize); 914 915 } else { 916 wdcattach(&cp->wdc_channel); 917 } 918 } 919 920 if (sc->sc_dma_ok == 0) 921 return; 922 923 /* Allocate DMA maps */ 924 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 925 idedma_ctl = 0; 926 cp = &sc->pciide_channels[channel]; 927 for (drive = 0; drive < 2; drive++) { 928 drvp = &cp->wdc_channel.ch_drive[drive]; 929 /* If no drive, skip */ 930 if ((drvp->drive_flags & DRIVE) == 0) 931 continue; 932 if ((drvp->drive_flags & DRIVE_DMA) == 0) 933 continue; 934 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 935 /* Abort DMA setup */ 936 aprint_error( 937 "%s:%d:%d: can't allocate DMA maps, " 938 "using PIO transfers\n", 939 sc->sc_wdcdev.sc_dev.dv_xname, 940 channel, drive); 941 drvp->drive_flags &= ~DRIVE_DMA; 942 } 943 aprint_normal("%s:%d:%d: using DMA data transfers\n", 944 sc->sc_wdcdev.sc_dev.dv_xname, 945 channel, drive); 946 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 947 } 948 if (idedma_ctl != 0) { 949 /* Add software bits in status register */ 950 bus_space_write_1(sc->sc_dma_iot, 951 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 952 } 953 } 954 } 955 956 void 957 sata_setup_channel(chp) 958 struct wdc_channel *chp; 959 { 960 struct ata_drive_datas *drvp; 961 int drive; 962 u_int32_t idedma_ctl; 963 struct pciide_channel *cp = (struct pciide_channel*)chp; 964 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.ch_wdc; 965 966 /* setup DMA if needed */ 967 pciide_channel_dma_setup(cp); 968 969 idedma_ctl = 0; 970 971 for (drive = 0; drive < 2; drive++) { 972 drvp = &chp->ch_drive[drive]; 973 /* If no drive, skip */ 974 if ((drvp->drive_flags & DRIVE) == 0) 975 continue; 976 if (drvp->drive_flags & DRIVE_UDMA) { 977 /* use Ultra/DMA */ 978 drvp->drive_flags &= ~DRIVE_DMA; 979 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 980 } else if (drvp->drive_flags & DRIVE_DMA) { 981 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 982 } 983 } 984 985 /* 986 * Nothing to do to setup modes; it is meaningless in S-ATA 987 * (but many S-ATA drives still want to get the SET_FEATURE 988 * command). 989 */ 990 if (idedma_ctl != 0) { 991 /* Add software bits in status register */ 992 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 993 idedma_ctl); 994 } 995 } 996
Indexes created Thu Oct 02 07:10:07 GMT 2025