pciide_common.c revision 1.8.2.3.2.1
1 /* $NetBSD: pciide_common.c,v 1.8.2.3.2.1 2005/03/16 13:04:31 tron Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.8.2.3.2.1 2005/03/16 13:04:31 tron Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/malloc.h> 83 84 #include <uvm/uvm_extern.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pcidevs.h> 89 #include <dev/pci/pciidereg.h> 90 #include <dev/pci/pciidevar.h> 91 92 #include <dev/ic/wdcreg.h> 93 94 #ifdef WDCDEBUG 95 int wdcdebug_pciide_mask = 0; 96 #endif 97 98 static const char dmaerrfmt[] = 99 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 100 101 /* Default product description for devices not known from this controller */ 102 const struct pciide_product_desc default_product_desc = { 103 0, 104 0, 105 "Generic PCI IDE controller", 106 default_chip_map, 107 }; 108 109 const struct pciide_product_desc * 110 pciide_lookup_product(id, pp) 111 pcireg_t id; 112 const struct pciide_product_desc *pp; 113 { 114 for (; pp->chip_map != NULL; pp++) 115 if (PCI_PRODUCT(id) == pp->ide_product) 116 break; 117 118 if (pp->chip_map == NULL) 119 return NULL; 120 return pp; 121 } 122 123 void 124 pciide_common_attach(sc, pa, pp) 125 struct pciide_softc *sc; 126 struct pci_attach_args *pa; 127 const struct pciide_product_desc *pp; 128 { 129 pci_chipset_tag_t pc = pa->pa_pc; 130 pcitag_t tag = pa->pa_tag; 131 pcireg_t csr; 132 char devinfo[256]; 133 const char *displaydev; 134 135 aprint_naive(": disk controller\n"); 136 aprint_normal("\n"); 137 138 sc->sc_pci_id = pa->pa_id; 139 if (pp == NULL) { 140 /* should only happen for generic pciide devices */ 141 sc->sc_pp = &default_product_desc; 142 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 143 displaydev = devinfo; 144 } else { 145 sc->sc_pp = pp; 146 displaydev = sc->sc_pp->ide_name; 147 } 148 149 /* if displaydev == NULL, printf is done in chip-specific map */ 150 if (displaydev) 151 aprint_normal("%s: %s (rev. 0x%02x)\n", 152 sc->sc_wdcdev.sc_dev.dv_xname, displaydev, 153 PCI_REVISION(pa->pa_class)); 154 155 sc->sc_pc = pa->pa_pc; 156 sc->sc_tag = pa->pa_tag; 157 158 /* Set up DMA defaults; these might be adjusted by chip_map. */ 159 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 160 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 161 162 #ifdef WDCDEBUG 163 if (wdcdebug_pciide_mask & DEBUG_PROBE) 164 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 165 #endif 166 sc->sc_pp->chip_map(sc, pa); 167 168 if (sc->sc_dma_ok) { 169 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 170 csr |= PCI_COMMAND_MASTER_ENABLE; 171 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 172 } 173 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 174 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 175 } 176 177 /* tell whether the chip is enabled or not */ 178 int 179 pciide_chipen(sc, pa) 180 struct pciide_softc *sc; 181 struct pci_attach_args *pa; 182 { 183 pcireg_t csr; 184 185 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 186 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 187 PCI_COMMAND_STATUS_REG); 188 aprint_normal("%s: device disabled (at %s)\n", 189 sc->sc_wdcdev.sc_dev.dv_xname, 190 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 191 "device" : "bridge"); 192 return 0; 193 } 194 return 1; 195 } 196 197 void 198 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 199 struct pci_attach_args *pa; 200 struct pciide_channel *cp; 201 int compatchan; 202 bus_size_t *cmdsizep, *ctlsizep; 203 { 204 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 205 struct wdc_channel *wdc_cp = &cp->wdc_channel; 206 int i; 207 208 cp->compat = 1; 209 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 210 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 211 212 wdc_cp->cmd_iot = pa->pa_iot; 213 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 214 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_baseioh) != 0) { 215 aprint_error("%s: couldn't map %s channel cmd regs\n", 216 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 217 goto bad; 218 } 219 220 wdc_cp->ctl_iot = pa->pa_iot; 221 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 222 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 223 aprint_error("%s: couldn't map %s channel ctl regs\n", 224 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 225 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 226 PCIIDE_COMPAT_CMD_SIZE); 227 goto bad; 228 } 229 230 for (i = 0; i < WDC_NREG; i++) { 231 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, i, 232 i == 0 ? 4 : 1, &wdc_cp->cmd_iohs[i]) != 0) { 233 aprint_error("%s: couldn't subregion %s channel " 234 "cmd regs\n", 235 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 236 goto bad; 237 } 238 } 239 wdc_cp->data32iot = wdc_cp->cmd_iot; 240 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 241 return; 242 243 bad: 244 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 245 return; 246 } 247 248 void 249 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 250 struct pci_attach_args * pa; 251 struct pciide_channel *cp; 252 bus_size_t *cmdsizep, *ctlsizep; 253 int (*pci_intr) __P((void *)); 254 { 255 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 256 struct wdc_channel *wdc_cp = &cp->wdc_channel; 257 const char *intrstr; 258 pci_intr_handle_t intrhandle; 259 int i; 260 261 cp->compat = 0; 262 263 if (sc->sc_pci_ih == NULL) { 264 if (pci_intr_map(pa, &intrhandle) != 0) { 265 aprint_error("%s: couldn't map native-PCI interrupt\n", 266 sc->sc_wdcdev.sc_dev.dv_xname); 267 goto bad; 268 } 269 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 270 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 271 intrhandle, IPL_BIO, pci_intr, sc); 272 if (sc->sc_pci_ih != NULL) { 273 aprint_normal("%s: using %s for native-PCI interrupt\n", 274 sc->sc_wdcdev.sc_dev.dv_xname, 275 intrstr ? intrstr : "unknown interrupt"); 276 } else { 277 aprint_error( 278 "%s: couldn't establish native-PCI interrupt", 279 sc->sc_wdcdev.sc_dev.dv_xname); 280 if (intrstr != NULL) 281 aprint_normal(" at %s", intrstr); 282 aprint_normal("\n"); 283 goto bad; 284 } 285 } 286 cp->ih = sc->sc_pci_ih; 287 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), 288 PCI_MAPREG_TYPE_IO, 0, 289 &wdc_cp->cmd_iot, &wdc_cp->cmd_baseioh, NULL, cmdsizep) != 0) { 290 aprint_error("%s: couldn't map %s channel cmd regs\n", 291 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 292 goto bad; 293 } 294 295 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), 296 PCI_MAPREG_TYPE_IO, 0, 297 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 298 aprint_error("%s: couldn't map %s channel ctl regs\n", 299 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 300 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 301 *cmdsizep); 302 goto bad; 303 } 304 /* 305 * In native mode, 4 bytes of I/O space are mapped for the control 306 * register, the control register is at offset 2. Pass the generic 307 * code a handle for only one byte at the right offset. 308 */ 309 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 310 &wdc_cp->ctl_ioh) != 0) { 311 aprint_error("%s: unable to subregion %s channel ctl regs\n", 312 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 313 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 314 *cmdsizep); 315 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 316 goto bad; 317 } 318 319 for (i = 0; i < WDC_NREG; i++) { 320 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, i, 321 i == 0 ? 4 : 1, &wdc_cp->cmd_iohs[i]) != 0) { 322 aprint_error("%s: couldn't subregion %s channel " 323 "cmd regs\n", 324 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 325 goto bad; 326 } 327 } 328 wdc_cp->data32iot = wdc_cp->cmd_iot; 329 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 330 return; 331 332 bad: 333 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 334 return; 335 } 336 337 void 338 pciide_mapreg_dma(sc, pa) 339 struct pciide_softc *sc; 340 struct pci_attach_args *pa; 341 { 342 pcireg_t maptype; 343 bus_addr_t addr; 344 struct pciide_channel *pc; 345 int reg, chan; 346 bus_size_t size; 347 348 /* 349 * Map DMA registers 350 * 351 * Note that sc_dma_ok is the right variable to test to see if 352 * DMA can be done. If the interface doesn't support DMA, 353 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 354 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 355 * non-zero if the interface supports DMA and the registers 356 * could be mapped. 357 * 358 * XXX Note that despite the fact that the Bus Master IDE specs 359 * XXX say that "The bus master IDE function uses 16 bytes of IO 360 * XXX space," some controllers (at least the United 361 * XXX Microelectronics UM8886BF) place it in memory space. 362 */ 363 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 364 PCIIDE_REG_BUS_MASTER_DMA); 365 366 switch (maptype) { 367 case PCI_MAPREG_TYPE_IO: 368 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 369 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 370 &addr, NULL, NULL) == 0); 371 if (sc->sc_dma_ok == 0) { 372 aprint_normal( 373 ", but unused (couldn't query registers)"); 374 break; 375 } 376 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 377 && addr >= 0x10000) { 378 sc->sc_dma_ok = 0; 379 aprint_normal( 380 ", but unused (registers at unsafe address " 381 "%#lx)", (unsigned long)addr); 382 break; 383 } 384 /* FALLTHROUGH */ 385 386 case PCI_MAPREG_MEM_TYPE_32BIT: 387 sc->sc_dma_ok = (pci_mapreg_map(pa, 388 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 389 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 390 sc->sc_dmat = pa->pa_dmat; 391 if (sc->sc_dma_ok == 0) { 392 aprint_normal(", but unused (couldn't map registers)"); 393 } else { 394 sc->sc_wdcdev.dma_arg = sc; 395 sc->sc_wdcdev.dma_init = pciide_dma_init; 396 sc->sc_wdcdev.dma_start = pciide_dma_start; 397 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 398 } 399 400 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 401 PCIIDE_OPTIONS_NODMA) { 402 aprint_normal( 403 ", but unused (forced off by config file)"); 404 sc->sc_dma_ok = 0; 405 } 406 break; 407 408 default: 409 sc->sc_dma_ok = 0; 410 aprint_normal( 411 ", but unsupported register maptype (0x%x)", maptype); 412 } 413 414 if (sc->sc_dma_ok == 0) 415 return; 416 417 /* 418 * Set up the default handles for the DMA registers. 419 * Just reserve 32 bits for each handle, unless space 420 * doesn't permit it. 421 */ 422 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 423 pc = &sc->pciide_channels[chan]; 424 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 425 size = 4; 426 if (size > (IDEDMA_SCH_OFFSET - reg)) 427 size = IDEDMA_SCH_OFFSET - reg; 428 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 429 IDEDMA_SCH_OFFSET * chan + reg, size, 430 &pc->dma_iohs[reg]) != 0) { 431 sc->sc_dma_ok = 0; 432 aprint_normal(", but can't subregion offset %d " 433 "size %lu", reg, (u_long)size); 434 return; 435 } 436 } 437 } 438 } 439 440 int 441 pciide_compat_intr(arg) 442 void *arg; 443 { 444 struct pciide_channel *cp = arg; 445 446 #ifdef DIAGNOSTIC 447 /* should only be called for a compat channel */ 448 if (cp->compat == 0) 449 panic("pciide compat intr called for non-compat chan %p", cp); 450 #endif 451 return (wdcintr(&cp->wdc_channel)); 452 } 453 454 int 455 pciide_pci_intr(arg) 456 void *arg; 457 { 458 struct pciide_softc *sc = arg; 459 struct pciide_channel *cp; 460 struct wdc_channel *wdc_cp; 461 int i, rv, crv; 462 463 rv = 0; 464 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 465 cp = &sc->pciide_channels[i]; 466 wdc_cp = &cp->wdc_channel; 467 468 /* If a compat channel skip. */ 469 if (cp->compat) 470 continue; 471 /* if this channel not waiting for intr, skip */ 472 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 473 continue; 474 475 crv = wdcintr(wdc_cp); 476 if (crv == 0) 477 ; /* leave rv alone */ 478 else if (crv == 1) 479 rv = 1; /* claim the intr */ 480 else if (rv == 0) /* crv should be -1 in this case */ 481 rv = crv; /* if we've done no better, take it */ 482 } 483 return (rv); 484 } 485 486 void 487 pciide_channel_dma_setup(cp) 488 struct pciide_channel *cp; 489 { 490 int drive; 491 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 492 struct ata_drive_datas *drvp; 493 494 for (drive = 0; drive < 2; drive++) { 495 drvp = &cp->wdc_channel.ch_drive[drive]; 496 /* If no drive, skip */ 497 if ((drvp->drive_flags & DRIVE) == 0) 498 continue; 499 /* setup DMA if needed */ 500 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 501 (drvp->drive_flags & DRIVE_UDMA) == 0) || 502 sc->sc_dma_ok == 0) { 503 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 504 continue; 505 } 506 if (pciide_dma_table_setup(sc, cp->wdc_channel.ch_channel, 507 drive) != 0) { 508 /* Abort DMA setup */ 509 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 510 continue; 511 } 512 } 513 } 514 515 int 516 pciide_dma_table_setup(sc, channel, drive) 517 struct pciide_softc *sc; 518 int channel, drive; 519 { 520 bus_dma_segment_t seg; 521 int error, rseg; 522 const bus_size_t dma_table_size = 523 sizeof(struct idedma_table) * NIDEDMA_TABLES; 524 struct pciide_dma_maps *dma_maps = 525 &sc->pciide_channels[channel].dma_maps[drive]; 526 527 /* If table was already allocated, just return */ 528 if (dma_maps->dma_table) 529 return 0; 530 531 /* Allocate memory for the DMA tables and map it */ 532 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 533 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 534 BUS_DMA_NOWAIT)) != 0) { 535 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 536 "allocate", drive, error); 537 return error; 538 } 539 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 540 dma_table_size, 541 (caddr_t *)&dma_maps->dma_table, 542 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 543 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 544 "map", drive, error); 545 return error; 546 } 547 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 548 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 549 (unsigned long)seg.ds_addr), DEBUG_PROBE); 550 /* Create and load table DMA map for this disk */ 551 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 552 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 553 &dma_maps->dmamap_table)) != 0) { 554 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 555 "create", drive, error); 556 return error; 557 } 558 if ((error = bus_dmamap_load(sc->sc_dmat, 559 dma_maps->dmamap_table, 560 dma_maps->dma_table, 561 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 562 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 563 "load", drive, error); 564 return error; 565 } 566 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 567 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 568 DEBUG_PROBE); 569 /* Create a xfer DMA map for this drive */ 570 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 571 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 572 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 573 &dma_maps->dmamap_xfer)) != 0) { 574 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 575 "create xfer", drive, error); 576 return error; 577 } 578 return 0; 579 } 580 581 int 582 pciide_dma_dmamap_setup(sc, channel, drive, databuf, datalen, flags) 583 struct pciide_softc *sc; 584 int channel, drive; 585 void *databuf; 586 size_t datalen; 587 int flags; 588 { 589 int error, seg; 590 struct pciide_channel *cp = &sc->pciide_channels[channel]; 591 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 592 593 error = bus_dmamap_load(sc->sc_dmat, 594 dma_maps->dmamap_xfer, 595 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 596 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 597 if (error) { 598 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 599 "load xfer", drive, error); 600 return error; 601 } 602 603 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 604 dma_maps->dmamap_xfer->dm_mapsize, 605 (flags & WDC_DMA_READ) ? 606 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 607 608 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 609 #ifdef DIAGNOSTIC 610 /* A segment must not cross a 64k boundary */ 611 { 612 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 613 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 614 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 615 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 616 printf("pciide_dma: segment %d physical addr 0x%lx" 617 " len 0x%lx not properly aligned\n", 618 seg, phys, len); 619 panic("pciide_dma: buf align"); 620 } 621 } 622 #endif 623 dma_maps->dma_table[seg].base_addr = 624 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 625 dma_maps->dma_table[seg].byte_count = 626 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 627 IDEDMA_BYTE_COUNT_MASK); 628 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 629 seg, le32toh(dma_maps->dma_table[seg].byte_count), 630 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 631 632 } 633 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 634 htole32(IDEDMA_BYTE_COUNT_EOT); 635 636 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 637 dma_maps->dmamap_table->dm_mapsize, 638 BUS_DMASYNC_PREWRITE); 639 640 #ifdef DIAGNOSTIC 641 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 642 printf("pciide_dma_dmamap_setup: addr 0x%lx " 643 "not properly aligned\n", 644 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 645 panic("pciide_dma_init: table align"); 646 } 647 #endif 648 /* remember flags */ 649 dma_maps->dma_flags = flags; 650 651 return 0; 652 } 653 654 int 655 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 656 void *v; 657 int channel, drive; 658 void *databuf; 659 size_t datalen; 660 int flags; 661 { 662 struct pciide_softc *sc = v; 663 int error; 664 struct pciide_channel *cp = &sc->pciide_channels[channel]; 665 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 666 667 if ((error = pciide_dma_dmamap_setup(sc, channel, drive, 668 databuf, datalen, flags)) != 0) 669 return error; 670 /* Maps are ready. Start DMA function */ 671 /* Clear status bits */ 672 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 673 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 674 /* Write table addr */ 675 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 676 dma_maps->dmamap_table->dm_segs[0].ds_addr); 677 /* set read/write */ 678 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 679 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 680 return 0; 681 } 682 683 void 684 pciide_dma_start(v, channel, drive) 685 void *v; 686 int channel, drive; 687 { 688 struct pciide_softc *sc = v; 689 struct pciide_channel *cp = &sc->pciide_channels[channel]; 690 691 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 692 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 693 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 694 | IDEDMA_CMD_START); 695 } 696 697 int 698 pciide_dma_finish(v, channel, drive, force) 699 void *v; 700 int channel, drive; 701 int force; 702 { 703 struct pciide_softc *sc = v; 704 u_int8_t status; 705 int error = 0; 706 struct pciide_channel *cp = &sc->pciide_channels[channel]; 707 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 708 709 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 710 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 711 DEBUG_XFERS); 712 713 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 714 return WDC_DMAST_NOIRQ; 715 716 /* stop DMA channel */ 717 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 718 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 719 & ~IDEDMA_CMD_START); 720 721 /* Unload the map of the data buffer */ 722 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 723 dma_maps->dmamap_xfer->dm_mapsize, 724 (dma_maps->dma_flags & WDC_DMA_READ) ? 725 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 726 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 727 728 if ((status & IDEDMA_CTL_ERR) != 0) { 729 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 730 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 731 error |= WDC_DMAST_ERR; 732 } 733 734 if ((status & IDEDMA_CTL_INTR) == 0) { 735 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 736 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 737 drive, status); 738 error |= WDC_DMAST_NOIRQ; 739 } 740 741 if ((status & IDEDMA_CTL_ACT) != 0) { 742 /* data underrun, may be a valid condition for ATAPI */ 743 error |= WDC_DMAST_UNDER; 744 } 745 return error; 746 } 747 748 void 749 pciide_irqack(chp) 750 struct wdc_channel *chp; 751 { 752 struct pciide_channel *cp = (struct pciide_channel*)chp; 753 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 754 755 /* clear status bits in IDE DMA registers */ 756 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 757 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 758 } 759 760 /* some common code used by several chip_map */ 761 int 762 pciide_chansetup(sc, channel, interface) 763 struct pciide_softc *sc; 764 int channel; 765 pcireg_t interface; 766 { 767 struct pciide_channel *cp = &sc->pciide_channels[channel]; 768 sc->wdc_chanarray[channel] = &cp->wdc_channel; 769 cp->name = PCIIDE_CHANNEL_NAME(channel); 770 cp->wdc_channel.ch_channel = channel; 771 cp->wdc_channel.ch_wdc = &sc->sc_wdcdev; 772 cp->wdc_channel.ch_queue = 773 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 774 if (cp->wdc_channel.ch_queue == NULL) { 775 aprint_error("%s %s channel: " 776 "can't allocate memory for command queue", 777 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 778 return 0; 779 } 780 aprint_normal("%s: %s channel %s to %s mode\n", 781 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 782 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 783 "configured" : "wired", 784 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 785 "native-PCI" : "compatibility"); 786 return 1; 787 } 788 789 /* some common code used by several chip channel_map */ 790 void 791 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 792 struct pci_attach_args *pa; 793 struct pciide_channel *cp; 794 pcireg_t interface; 795 bus_size_t *cmdsizep, *ctlsizep; 796 int (*pci_intr) __P((void *)); 797 { 798 struct wdc_channel *wdc_cp = &cp->wdc_channel; 799 800 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) 801 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr); 802 else { 803 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 804 ctlsizep); 805 if ((cp->wdc_channel.ch_flags & WDCF_DISABLED) == 0) 806 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 807 } 808 wdcattach(wdc_cp); 809 } 810 811 /* 812 * generic code to map the compat intr. 813 */ 814 void 815 pciide_map_compat_intr(pa, cp, compatchan) 816 struct pci_attach_args *pa; 817 struct pciide_channel *cp; 818 int compatchan; 819 { 820 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 821 822 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 823 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 824 pa, compatchan, pciide_compat_intr, cp); 825 if (cp->ih == NULL) { 826 #endif 827 aprint_error("%s: no compatibility interrupt for use by %s " 828 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 829 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 830 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 831 } 832 #endif 833 } 834 835 void 836 default_chip_map(sc, pa) 837 struct pciide_softc *sc; 838 struct pci_attach_args *pa; 839 { 840 struct pciide_channel *cp; 841 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 842 pcireg_t csr; 843 int channel, drive; 844 struct ata_drive_datas *drvp; 845 u_int8_t idedma_ctl; 846 bus_size_t cmdsize, ctlsize; 847 char *failreason; 848 849 if (pciide_chipen(sc, pa) == 0) 850 return; 851 852 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 853 aprint_normal("%s: bus-master DMA support present", 854 sc->sc_wdcdev.sc_dev.dv_xname); 855 if (sc->sc_pp == &default_product_desc && 856 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 857 PCIIDE_OPTIONS_DMA) == 0) { 858 aprint_normal(", but unused (no driver support)"); 859 sc->sc_dma_ok = 0; 860 } else { 861 pciide_mapreg_dma(sc, pa); 862 if (sc->sc_dma_ok != 0) 863 aprint_normal(", used without full driver " 864 "support"); 865 } 866 } else { 867 aprint_normal("%s: hardware does not support DMA", 868 sc->sc_wdcdev.sc_dev.dv_xname); 869 sc->sc_dma_ok = 0; 870 } 871 aprint_normal("\n"); 872 if (sc->sc_dma_ok) { 873 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 874 sc->sc_wdcdev.irqack = pciide_irqack; 875 } 876 sc->sc_wdcdev.PIO_cap = 0; 877 sc->sc_wdcdev.DMA_cap = 0; 878 879 sc->sc_wdcdev.channels = sc->wdc_chanarray; 880 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 881 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 882 883 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 884 cp = &sc->pciide_channels[channel]; 885 if (pciide_chansetup(sc, channel, interface) == 0) 886 continue; 887 if (interface & PCIIDE_INTERFACE_PCI(channel)) 888 pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 889 pciide_pci_intr); 890 else 891 pciide_mapregs_compat(pa, cp, 892 cp->wdc_channel.ch_channel, &cmdsize, &ctlsize); 893 if (cp->wdc_channel.ch_flags & WDCF_DISABLED) 894 continue; 895 /* 896 * Check to see if something appears to be there. 897 */ 898 failreason = NULL; 899 /* 900 * In native mode, always enable the controller. It's 901 * not possible to have an ISA board using the same address 902 * anyway. 903 */ 904 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 905 wdcattach(&cp->wdc_channel); 906 continue; 907 } 908 if (!wdcprobe(&cp->wdc_channel)) { 909 failreason = "not responding; disabled or no drives?"; 910 goto next; 911 } 912 /* 913 * Now, make sure it's actually attributable to this PCI IDE 914 * channel by trying to access the channel again while the 915 * PCI IDE controller's I/O space is disabled. (If the 916 * channel no longer appears to be there, it belongs to 917 * this controller.) YUCK! 918 */ 919 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 920 PCI_COMMAND_STATUS_REG); 921 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 922 csr & ~PCI_COMMAND_IO_ENABLE); 923 if (wdcprobe(&cp->wdc_channel)) 924 failreason = "other hardware responding at addresses"; 925 pci_conf_write(sc->sc_pc, sc->sc_tag, 926 PCI_COMMAND_STATUS_REG, csr); 927 next: 928 if (failreason) { 929 aprint_error("%s: %s channel ignored (%s)\n", 930 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 931 failreason); 932 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 933 bus_space_unmap(cp->wdc_channel.cmd_iot, 934 cp->wdc_channel.cmd_baseioh, cmdsize); 935 bus_space_unmap(cp->wdc_channel.ctl_iot, 936 cp->wdc_channel.ctl_ioh, ctlsize); 937 } else { 938 pciide_map_compat_intr(pa, cp, 939 cp->wdc_channel.ch_channel); 940 wdcattach(&cp->wdc_channel); 941 } 942 } 943 944 if (sc->sc_dma_ok == 0) 945 return; 946 947 /* Allocate DMA maps */ 948 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 949 idedma_ctl = 0; 950 cp = &sc->pciide_channels[channel]; 951 for (drive = 0; drive < 2; drive++) { 952 drvp = &cp->wdc_channel.ch_drive[drive]; 953 /* If no drive, skip */ 954 if ((drvp->drive_flags & DRIVE) == 0) 955 continue; 956 if ((drvp->drive_flags & DRIVE_DMA) == 0) 957 continue; 958 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 959 /* Abort DMA setup */ 960 aprint_error( 961 "%s:%d:%d: can't allocate DMA maps, " 962 "using PIO transfers\n", 963 sc->sc_wdcdev.sc_dev.dv_xname, 964 channel, drive); 965 drvp->drive_flags &= ~DRIVE_DMA; 966 } 967 aprint_normal("%s:%d:%d: using DMA data transfers\n", 968 sc->sc_wdcdev.sc_dev.dv_xname, 969 channel, drive); 970 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 971 } 972 if (idedma_ctl != 0) { 973 /* Add software bits in status register */ 974 bus_space_write_1(sc->sc_dma_iot, 975 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 976 } 977 } 978 } 979 980 void 981 sata_setup_channel(chp) 982 struct wdc_channel *chp; 983 { 984 struct ata_drive_datas *drvp; 985 int drive; 986 u_int32_t idedma_ctl; 987 struct pciide_channel *cp = (struct pciide_channel*)chp; 988 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.ch_wdc; 989 990 /* setup DMA if needed */ 991 pciide_channel_dma_setup(cp); 992 993 idedma_ctl = 0; 994 995 for (drive = 0; drive < 2; drive++) { 996 drvp = &chp->ch_drive[drive]; 997 /* If no drive, skip */ 998 if ((drvp->drive_flags & DRIVE) == 0) 999 continue; 1000 if (drvp->drive_flags & DRIVE_UDMA) { 1001 /* use Ultra/DMA */ 1002 drvp->drive_flags &= ~DRIVE_DMA; 1003 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1004 } else if (drvp->drive_flags & DRIVE_DMA) { 1005 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1006 } 1007 } 1008 1009 /* 1010 * Nothing to do to setup modes; it is meaningless in S-ATA 1011 * (but many S-ATA drives still want to get the SET_FEATURE 1012 * command). 1013 */ 1014 if (idedma_ctl != 0) { 1015 /* Add software bits in status register */ 1016 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 1017 idedma_ctl); 1018 } 1019 } 1020
Indexes created Thu Oct 02 07:10:07 GMT 2025