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pciide_pdc202xx_reg.h revision 1.2 
      1 /*	$NetBSD: pciide_pdc202xx_reg.h,v 1.2 1999/11/28 20:05:18 bouyer Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1999 Manuel Bouyer.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by the University of
     17  *	California, Berkeley and its contributors.
     18  * 4. Neither the name of the University nor the names of its contributors
     19  *    may be used to endorse or promote products derived from this software
     20  *    without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  *
     34  */
     35 
     36 /*
     37  * Registers definitions for PROMISE PDC20246/PDC20262 PCI IDE controller.
     38  * Unfortunably the HW docs are not publically available. I've been able
     39  * to get a partial one for the PDC20246, and a better one for the PDC20262
     40  * from Promise.
     41  */
     42 
     43 #define PDC2xx_STATE		0x50
     44 #define PDC2xx_STATE_IDERAID		0x0001
     45 #define PDC2xx_STATE_NATIVE		0x0080
     46 /* controller initial state values(PDC20246 only) */
     47 #define PDC246_STATE_SHIPID		0x8000
     48 #define PDC246_STATE_IOCHRDY		0x0400
     49 #define PDC246_STATE_LBA(channel)	(0x0100 << (channel))
     50 #define PDC246_STATE_ISAIRQ		0x0008
     51 #define PDC246_STATE_EN(channel)	(0x0002 << (channel))
     52 /* controller initial state values(PDC20262 only) */
     53 #define PDC262_STATE_EN(chan)		(0x1000 << (chan))
     54 #define PDC262_STATE_80P(chan)		(0x0400 << (chan))
     55 
     56 /* per-drive timings */
     57 #define PDC2xx_TIM(channel, drive) (0x60 + 4 * (drive) + 8 * (channel))
     58 #define PDC2xx_TIM_SET_PA(r, x)	(((r) & 0xfffffff0) | ((x) & 0xf))
     59 #define PDC2xx_TIM_SET_PB(r, x)	(((r) & 0xffffe0ff) | (((x) & 0x1f) << 8))
     60 #define PDC2xx_TIM_SET_MB(r, x)	(((r) & 0xffff1fff) | (((x) & 0x7) << 13))
     61 #define PDC2xx_TIM_SET_MC(r, x)	(((r) & 0xfff0ffff) | (((x) & 0xf) << 16))
     62 #define PDC2xx_TIM_PRE		0x00000010
     63 #define PDC2xx_TIM_IORDY	0x00000020
     64 #define PDC2xx_TIM_ERRDY	0x00000040
     65 #define PDC2xx_TIM_SYNC		0x00000080
     66 #define PDC2xx_TIM_DMAW		0x00100000
     67 #define PDC2xx_TIM_DMAR		0x00200000
     68 #define PDC2xx_TIM_IORDYp	0x00400000
     69 #define PDC2xx_TIM_DMARQp	0x00800000
     70 
     71 /* The following are extentions of the DMA registers */
     72 
     73 /* Ultra-DMA mode 3/4 control (PDC20262 only, 1 byte) */
     74 #define PDC262_U66	0x11
     75 #define PDC262_U66_EN(chan) (0x1 << ((chan) *2))
     76 /* primary mode (1 byte) */
     77 #define PDC2xx_PM	0x1a
     78 /* secondary mode (1 byte) */
     79 #define PDC2xx_SM	0x1b
     80 /* System control register (4 bytes) */
     81 #define PDC2xx_SCR	0x1c
     82 #define PDC2xx_SCR_SET_GEN(r,x) (((r) & 0xffffff00) | ((x) & 0xff))
     83 #define PDC2xx_SCR_EMPTY(channel) (0x00000100 << (4 * channel))
     84 #define PDC2xx_SCR_FULL(channel) (0x00000200 << (4 * channel))
     85 #define PDC2xx_SCR_INT(channel) (0x00000400 << (4 * channel))
     86 #define PDC2xx_SCR_ERR(channel) (0x00000800 << (4 * channel))
     87 #define PDC2xx_SCR_SET_I2C(r,x) (((r) & 0xfff0ffff) | (((x) & 0xf) << 16))
     88 #define PDC2xx_SCR_SET_POLL(r,x) (((r) & 0xff0fffff) | (((x) & 0xf) << 20))
     89 #define PDC2xx_SCR_DMA		0x01000000
     90 #define PDC2xx_SCR_IORDY	0x02000000
     91 #define PDC2xx_SCR_G2FD		0x04000000
     92 #define PDC2xx_SCR_FLOAT	0x08000000
     93 #define PDC2xx_SCR_RSET		0x10000000
     94 #define PDC2xx_SCR_TST		0x20000000
     95 /* Values for "General Purpose Register" (PDC20262 only) */
     96 #define PDC262_SCR_GEN_LAT	0x20
     97 
     98 /* ATAPI port ((PDC20262 only) (4 bytes) */
     99 #define PDC262_ATAPI(chan) (0x20 + (4 * (chan)))
    100 #define PDC262_ATAPI_WC_MASK	0x00000fff
    101 #define PDC262_ATAPI_DMA_READ	0x00001000
    102 #define PDC262_ATAPI_DMA_WRITE	0x00002000
    103 #define PDC262_ATAPI_UDMA	0x00004000
    104 
    105 /*
    106  * The timings provided here cmoes from the PDC20262 docs. I hope they are
    107  * rigth for the PDC20246 too ...
    108  */
    109 
    110 static int8_t pdc2xx_pa[] = {0x9, 0x5, 0x3, 0x2, 0x1};
    111 static int8_t pdc2xx_pb[] = {0x13, 0xc, 0x8, 0x6, 0x4};
    112 static int8_t pdc2xx_dma_mb[] = {0x7, 0x3, 0x3};
    113 static int8_t pdc2xx_dma_mc[] = {0xf, 0x4, 0x3};
    114 static int8_t pdc2xx_udma_mb[] = {0x3, 0x2, 0x1, 0x2, 0x1};
    115 static int8_t pdc2xx_udma_mc[] = {0x3, 0x2, 0x1, 0x2, 0x1};
    116