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pciide_sl82c105_reg.h revision 1.1 
      1 /*	$NetBSD: pciide_sl82c105_reg.h,v 1.1 2002/04/03 17:02:21 thorpej Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jason R. Thorpe.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *	This product includes software developed by the NetBSD
     21  *	Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 /*
     40  * Register definitions for the Symphony Labs 82C105 PCI IDE
     41  * interface.  This 82C105 is also found embedded in the Winbond
     42  * 83C553 Southbridge.
     43  */
     44 
     45 /* PCI configuration space registers */
     46 
     47 #define	SYMPH_PORT0_P	(PCI_MAPREG_START + 0x00)	/* port 0 primary */
     48 #define	SYMPH_PORT0_S	(PCI_MAPREG_START + 0x04)	/* port 0 secondary */
     49 #define	SYMPH_PORT1_P	(PCI_MAPREG_START + 0x08)	/* port 1 primary */
     50 #define	SYMPH_PORT1_S	(PCI_MAPREG_START + 0x0c)	/* port 1 secondary */
     51 #define	SYMPH_BMIDER	(PCI_MAPREG_START + 0x10)	/* bus master regs */
     52 
     53 #define	SYMPH_IDECSR	0x40		/* IDE control/status */
     54 #define	SYMPH_P0D0CR	0x44		/* port 0 drive 0 control */
     55 #define	SYMPH_P0D1CR	0x48		/* port 0 drive 1 control */
     56 #define	SYMPH_P1D0CR	0x4c		/* port 1 drive 0 control */
     57 #define	SYMPH_P1D1CR	0c50		/* port 1 drive 1 control */
     58 
     59 #define	IDECR_IDE_IRQB	(1U << 30)	/* IDE_IRQB signal */
     60 #define	IDECR_IDE_IRQA	(1U << 28)	/* IDE_IRQA signal */
     61 #define	IDECR_RA_SHIFT	16		/* read-ahead duration */
     62 #define	IDECR_RA_MASK	(0x7ff << IDECR_RA_SHIFT)
     63 #define	IDECR_LEGIRQ	(1U << 1)	/* legacy IRQ mode */
     64 #define	IDECR_P1F16	(1U << 5)	/* port 1 fast 16 */
     65 #define	IDECR_P1EN	(1U << 4)	/* port 1 enable */
     66 #define	IDECR_P0F16	(1U << 1)	/* port 0 fast 16 */
     67 #define	IDECR_P0EN	(1U << 0)	/* port 0 enable */
     68 
     69 #define	PxDx_USR_SHIFT	16		/* user defined bits */
     70 #define	PxDx_USR_MASK	(0xff << PxDx_USR_SHIFT)
     71 #define	PxDx_CMD_ON_SHIFT 8		/* CMD ON time */
     72 #define	PxDx_CMD_ON_MASK (0x1f << PxDx_CMD_ON_SHIFT)
     73 #define	PxDx_PWEN	(1U << 7)	/* posted write enable */
     74 #define	PxDx_RDYEN	(1U << 6)	/* IOCHRDY enable */
     75 #define	PxDx_RAEN	(1U << 5)	/* read-ahead enable */
     76 #define	PxDx_CMD_OFF_MASK (0x1f)	/* CMD OFF time */
     77 
     78 /*
     79  * IDE CMD ON and CMD OFF times for a 33MHz PCI bus clock.
     80  *
     81  * These come from Table 4-4 of the 83c553 manual.
     82  */
     83 struct symph_cmdtime {
     84 	int	cmd_on;		/* cmd on time */
     85 	int	cmd_off;	/* cmd off time */
     86 };
     87 
     88 static const struct symph_cmdtime symph_pio_times[]
     89     __attribute__((__unused__)) = {
     90 /*        programmed               actual       */
     91 	{ 5, 13 },		/* 6, 14 */
     92 	{ 4, 7 },		/* 5, 8 */
     93 	{ 3, 4 },		/* 4, 5 */
     94 	{ 2, 2 },		/* 3, 3 */
     95 	{ 2, 0 },		/* 3, 1 */
     96 	{ 1, 0 },		/* 2, 1 */
     97 };
     98 
     99 static const struct symph_cmdtime symph_sw_dma_times[]
    100     __attribute__((__unused__)) = {
    101 /*        programmed               actual       */
    102 	{ 15, 15 },		/* 16, 16 */
    103 };
    104 
    105 static const struct symph_cmdtime symph_mw_dma_times[]
    106      __attribute__((__unused__)) = {
    107 /*        programmed               actual       */
    108 	{ 7, 7 },		/* 8, 8 */
    109 	{ 2, 1 },		/* 3, 2 */
    110 	{ 2, 0 },		/* 3, 1 */
    111 	{ 1, 0 },		/* 2, 1 */
    112 };
    113