pciidevar.h revision 1.10.2.2
1 1.10.2.2 skrll /* $NetBSD: pciidevar.h,v 1.10.2.2 2004/08/25 06:58:06 skrll Exp $ */ 2 1.1 cgd 3 1.1 cgd /* 4 1.1 cgd * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved. 5 1.1 cgd * 6 1.1 cgd * Redistribution and use in source and binary forms, with or without 7 1.1 cgd * modification, are permitted provided that the following conditions 8 1.1 cgd * are met: 9 1.1 cgd * 1. Redistributions of source code must retain the above copyright 10 1.1 cgd * notice, this list of conditions and the following disclaimer. 11 1.1 cgd * 2. Redistributions in binary form must reproduce the above copyright 12 1.1 cgd * notice, this list of conditions and the following disclaimer in the 13 1.1 cgd * documentation and/or other materials provided with the distribution. 14 1.1 cgd * 3. All advertising materials mentioning features or use of this software 15 1.1 cgd * must display the following acknowledgement: 16 1.1 cgd * This product includes software developed by Christopher G. Demetriou 17 1.1 cgd * for the NetBSD Project. 18 1.1 cgd * 4. The name of the author may not be used to endorse or promote products 19 1.1 cgd * derived from this software without specific prior written permission 20 1.1 cgd * 21 1.1 cgd * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 1.1 cgd * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 1.1 cgd * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 1.1 cgd * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 1.1 cgd * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 1.1 cgd * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 1.1 cgd * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 1.1 cgd * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 1.1 cgd * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 1.1 cgd * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1.1 cgd */ 32 1.1 cgd 33 1.10.2.2 skrll #ifndef _DEV_PCI_PCIIDEVAR_H_ 34 1.10.2.2 skrll #define _DEV_PCI_PCIIDEVAR_H_ 35 1.10.2.2 skrll 36 1.1 cgd /* 37 1.1 cgd * PCI IDE driver exported software structures. 38 1.1 cgd * 39 1.1 cgd * Author: Christopher G. Demetriou, March 2, 1998. 40 1.1 cgd */ 41 1.1 cgd 42 1.3 soren #include <dev/ata/atavar.h> 43 1.3 soren #include <dev/ic/wdcreg.h> 44 1.3 soren #include <dev/ic/wdcvar.h> 45 1.10.2.1 skrll #include "opt_pciide.h" 46 1.10.2.1 skrll 47 1.10.2.1 skrll /* options passed via the 'flags' config keyword */ 48 1.10.2.1 skrll #define PCIIDE_OPTIONS_DMA 0x01 49 1.10.2.1 skrll #define PCIIDE_OPTIONS_NODMA 0x02 50 1.10.2.1 skrll 51 1.10.2.2 skrll #ifndef ATADEBUG 52 1.10.2.2 skrll #define ATADEBUG 53 1.10.2.1 skrll #endif 54 1.10.2.1 skrll 55 1.10.2.1 skrll #define DEBUG_DMA 0x01 56 1.10.2.1 skrll #define DEBUG_XFERS 0x02 57 1.10.2.1 skrll #define DEBUG_FUNCS 0x08 58 1.10.2.1 skrll #define DEBUG_PROBE 0x10 59 1.10.2.2 skrll #ifdef ATADEBUG 60 1.10.2.2 skrll extern int atadebug_pciide_mask; 61 1.10.2.2 skrll #define ATADEBUG_PRINT(args, level) \ 62 1.10.2.2 skrll if (atadebug_pciide_mask & (level)) printf args 63 1.10.2.1 skrll #else 64 1.10.2.2 skrll #define ATADEBUG_PRINT(args, level) 65 1.10.2.1 skrll #endif 66 1.3 soren 67 1.1 cgd struct device; 68 1.3 soren 69 1.10.2.1 skrll /* 70 1.10.2.1 skrll * While standard PCI IDE controllers only have 2 channels, it is 71 1.10.2.1 skrll * common for PCI SATA controllers to have more. Here we define 72 1.10.2.1 skrll * the maximum number of channels that any one PCI IDE device can 73 1.10.2.1 skrll * have. 74 1.10.2.1 skrll */ 75 1.10.2.1 skrll #define PCIIDE_MAX_CHANNELS 4 76 1.10.2.1 skrll 77 1.3 soren struct pciide_softc { 78 1.3 soren struct wdc_softc sc_wdcdev; /* common wdc definitions */ 79 1.3 soren pci_chipset_tag_t sc_pc; /* PCI registers info */ 80 1.3 soren pcitag_t sc_tag; 81 1.3 soren void *sc_pci_ih; /* PCI interrupt handle */ 82 1.3 soren int sc_dma_ok; /* bus-master DMA info */ 83 1.10.2.1 skrll /* 84 1.10.2.1 skrll * sc_dma_ioh may only be used to allocate the dma_iohs 85 1.10.2.1 skrll * array in the channels (see below), or by chip-dependent 86 1.10.2.1 skrll * code that knows what it's doing, as the registers may 87 1.10.2.1 skrll * be laid out differently. All code in pciide_common.c 88 1.10.2.1 skrll * must use the channel->dma_iohs array. 89 1.10.2.1 skrll */ 90 1.3 soren bus_space_tag_t sc_dma_iot; 91 1.3 soren bus_space_handle_t sc_dma_ioh; 92 1.3 soren bus_dma_tag_t sc_dmat; 93 1.10 thorpej 94 1.10 thorpej /* 95 1.10 thorpej * Some controllers might have DMA restrictions other than 96 1.10 thorpej * the norm. 97 1.10 thorpej */ 98 1.10 thorpej bus_size_t sc_dma_maxsegsz; 99 1.10 thorpej bus_size_t sc_dma_boundary; 100 1.5 thorpej 101 1.10.2.1 skrll /* For VIA/AMD/nVidia */ 102 1.10.2.1 skrll bus_addr_t sc_apo_regbase; 103 1.8 thorpej 104 1.5 thorpej /* For Cypress */ 105 1.5 thorpej const struct cy82c693_handle *sc_cy_handle; 106 1.5 thorpej int sc_cy_compatchan; 107 1.9 bouyer 108 1.9 bouyer /* for SiS */ 109 1.9 bouyer u_int8_t sis_type; 110 1.5 thorpej 111 1.10.2.1 skrll /* For Silicon Image SATALink */ 112 1.10.2.1 skrll bus_space_tag_t sc_ba5_st; 113 1.10.2.1 skrll bus_space_handle_t sc_ba5_sh; 114 1.10.2.1 skrll int sc_ba5_en; 115 1.10.2.1 skrll 116 1.8 thorpej /* Vendor info (for interpreting Chip description) */ 117 1.10.2.1 skrll pcireg_t sc_pci_id; 118 1.3 soren /* Chip description */ 119 1.3 soren const struct pciide_product_desc *sc_pp; 120 1.3 soren /* common definitions */ 121 1.10.2.2 skrll struct ata_channel *wdc_chanarray[PCIIDE_MAX_CHANNELS]; 122 1.3 soren /* internal bookkeeping */ 123 1.3 soren struct pciide_channel { /* per-channel data */ 124 1.10.2.2 skrll struct ata_channel ata_channel; /* generic part */ 125 1.10.2.1 skrll const char *name; 126 1.6 bouyer int compat; /* is it compat? */ 127 1.6 bouyer void *ih; /* compat or pci handle */ 128 1.6 bouyer bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */ 129 1.3 soren /* DMA tables and DMA map for xfer, for each drive */ 130 1.3 soren struct pciide_dma_maps { 131 1.3 soren bus_dmamap_t dmamap_table; 132 1.3 soren struct idedma_table *dma_table; 133 1.3 soren bus_dmamap_t dmamap_xfer; 134 1.4 bouyer int dma_flags; 135 1.3 soren } dma_maps[2]; 136 1.10.2.1 skrll bus_space_handle_t dma_iohs[IDEDMA_NREGS]; 137 1.10.2.1 skrll /* 138 1.10.2.1 skrll * Some controllers require certain bits to 139 1.10.2.1 skrll * always be set for proper operation of the 140 1.10.2.1 skrll * controller. Set those bits here, if they're 141 1.10.2.1 skrll * required. 142 1.10.2.1 skrll */ 143 1.10.2.1 skrll uint8_t idedma_cmd; 144 1.10.2.1 skrll } pciide_channels[PCIIDE_MAX_CHANNELS]; 145 1.10.2.1 skrll }; 146 1.10.2.1 skrll 147 1.10.2.2 skrll /* Given an ata_channel, get the pciide_softc. */ 148 1.10.2.2 skrll #define CHAN_TO_PCIIDE(chp) ((struct pciide_softc *) (chp)->ch_atac) 149 1.10.2.2 skrll 150 1.10.2.2 skrll /* Given an ata_channel, get the pciide_channel. */ 151 1.10.2.2 skrll #define CHAN_TO_PCHAN(chp) ((struct pciide_channel *) (chp)) 152 1.10.2.2 skrll 153 1.10.2.1 skrll struct pciide_product_desc { 154 1.10.2.1 skrll u_int32_t ide_product; 155 1.10.2.1 skrll int ide_flags; 156 1.10.2.1 skrll const char *ide_name; 157 1.10.2.1 skrll /* map and setup chip, probe drives */ 158 1.10.2.1 skrll void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 159 1.3 soren }; 160 1.1 cgd 161 1.10.2.1 skrll /* Flags for ide_flags */ 162 1.10.2.1 skrll #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 163 1.10.2.1 skrll 164 1.10.2.1 skrll 165 1.10.2.1 skrll /* inlines for reading/writing 8-bit PCI registers */ 166 1.10.2.1 skrll static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 167 1.10.2.1 skrll int)); 168 1.10.2.1 skrll static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 169 1.10.2.1 skrll int, u_int8_t)); 170 1.10.2.1 skrll 171 1.10.2.1 skrll static __inline u_int8_t 172 1.10.2.1 skrll pciide_pci_read(pc, pa, reg) 173 1.10.2.1 skrll pci_chipset_tag_t pc; 174 1.10.2.1 skrll pcitag_t pa; 175 1.10.2.1 skrll int reg; 176 1.10.2.1 skrll { 177 1.10.2.1 skrll 178 1.10.2.1 skrll return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 179 1.10.2.1 skrll ((reg & 0x03) * 8) & 0xff); 180 1.10.2.1 skrll } 181 1.10.2.1 skrll 182 1.10.2.1 skrll static __inline void 183 1.10.2.1 skrll pciide_pci_write(pc, pa, reg, val) 184 1.10.2.1 skrll pci_chipset_tag_t pc; 185 1.10.2.1 skrll pcitag_t pa; 186 1.10.2.1 skrll int reg; 187 1.10.2.1 skrll u_int8_t val; 188 1.10.2.1 skrll { 189 1.10.2.1 skrll pcireg_t pcival; 190 1.10.2.1 skrll 191 1.10.2.1 skrll pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 192 1.10.2.1 skrll pcival &= ~(0xff << ((reg & 0x03) * 8)); 193 1.10.2.1 skrll pcival |= (val << ((reg & 0x03) * 8)); 194 1.10.2.1 skrll pci_conf_write(pc, pa, (reg & ~0x03), pcival); 195 1.10.2.1 skrll } 196 1.10.2.1 skrll 197 1.10.2.1 skrll void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 198 1.10.2.2 skrll void sata_setup_channel __P((struct ata_channel*)); 199 1.10.2.1 skrll 200 1.10.2.1 skrll void pciide_channel_dma_setup __P((struct pciide_channel *)); 201 1.10.2.1 skrll int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 202 1.10.2.1 skrll int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 203 1.10.2.1 skrll void pciide_dma_start __P((void*, int, int)); 204 1.10.2.1 skrll int pciide_dma_finish __P((void*, int, int, int)); 205 1.10.2.2 skrll void pciide_irqack __P((struct ata_channel *)); 206 1.10.2.1 skrll 207 1.1 cgd /* 208 1.1 cgd * Functions defined by machine-dependent code. 209 1.1 cgd */ 210 1.1 cgd 211 1.1 cgd /* Attach compat interrupt handler, returning handle or NULL if failed. */ 212 1.7 simonb #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 213 1.1 cgd void *pciide_machdep_compat_intr_establish __P((struct device *, 214 1.1 cgd struct pci_attach_args *, int, int (*)(void *), void *)); 215 1.7 simonb #endif 216 1.10.2.1 skrll 217 1.10.2.1 skrll const struct pciide_product_desc* pciide_lookup_product 218 1.10.2.1 skrll __P((u_int32_t, const struct pciide_product_desc *)); 219 1.10.2.1 skrll void pciide_common_attach 220 1.10.2.1 skrll __P((struct pciide_softc *, struct pci_attach_args *, 221 1.10.2.1 skrll const struct pciide_product_desc *)); 222 1.10.2.1 skrll 223 1.10.2.1 skrll int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 224 1.10.2.1 skrll void pciide_mapregs_compat __P(( struct pci_attach_args *, 225 1.10.2.1 skrll struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 226 1.10.2.1 skrll void pciide_mapregs_native __P((struct pci_attach_args *, 227 1.10.2.1 skrll struct pciide_channel *, bus_size_t *, bus_size_t *, 228 1.10.2.1 skrll int (*pci_intr) __P((void *)))); 229 1.10.2.1 skrll void pciide_mapreg_dma __P((struct pciide_softc *, 230 1.10.2.1 skrll struct pci_attach_args *)); 231 1.10.2.1 skrll int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 232 1.10.2.1 skrll void pciide_mapchan __P((struct pci_attach_args *, 233 1.10.2.1 skrll struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 234 1.10.2.1 skrll int (*pci_intr) __P((void *)))); 235 1.10.2.1 skrll void pciide_map_compat_intr __P(( struct pci_attach_args *, 236 1.10.2.1 skrll struct pciide_channel *, int)); 237 1.10.2.1 skrll int pciide_compat_intr __P((void *)); 238 1.10.2.1 skrll int pciide_pci_intr __P((void *)); 239 1.10.2.2 skrll 240 1.10.2.2 skrll #endif /* _DEV_PCI_PCIIDEVAR_H_ */ 241
Indexes created Tue Oct 14 06:10:07 GMT 2025