pciidevar.h revision 1.14
1 /* $NetBSD: pciidevar.h,v 1.14 2003/11/27 23:02:40 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI IDE driver exported software structures. 35 * 36 * Author: Christopher G. Demetriou, March 2, 1998. 37 */ 38 39 #include <dev/ata/atavar.h> 40 #include <dev/ic/wdcreg.h> 41 #include <dev/ic/wdcvar.h> 42 #include "opt_pciide.h" 43 44 #ifndef WDCDEBUG 45 #define WDCDEBUG 46 #endif 47 48 #define DEBUG_DMA 0x01 49 #define DEBUG_XFERS 0x02 50 #define DEBUG_FUNCS 0x08 51 #define DEBUG_PROBE 0x10 52 #ifdef WDCDEBUG 53 extern int wdcdebug_pciide_mask; 54 #define WDCDEBUG_PRINT(args, level) \ 55 if (wdcdebug_pciide_mask & (level)) printf args 56 #else 57 #define WDCDEBUG_PRINT(args, level) 58 #endif 59 60 struct device; 61 62 struct pciide_softc { 63 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 64 pci_chipset_tag_t sc_pc; /* PCI registers info */ 65 pcitag_t sc_tag; 66 void *sc_pci_ih; /* PCI interrupt handle */ 67 int sc_dma_ok; /* bus-master DMA info */ 68 /* 69 * sc_dma_ioh may only be used to allocate the dma_iohs 70 * array in the channels (see below), or by chip-dependent 71 * code that knows what it's doing, as the registers may 72 * be laid out differently. All code in pciide_common.c 73 * must use the channel->dma_iohs array. 74 */ 75 bus_space_tag_t sc_dma_iot; 76 bus_space_handle_t sc_dma_ioh; 77 bus_dma_tag_t sc_dmat; 78 79 /* 80 * Some controllers might have DMA restrictions other than 81 * the norm. 82 */ 83 bus_size_t sc_dma_maxsegsz; 84 bus_size_t sc_dma_boundary; 85 86 /* For VIA/AMD/nVidia */ 87 bus_addr_t sc_apo_regbase; 88 89 /* For Cypress */ 90 const struct cy82c693_handle *sc_cy_handle; 91 int sc_cy_compatchan; 92 93 /* for SiS */ 94 u_int8_t sis_type; 95 96 /* Vendor info (for interpreting Chip description) */ 97 pcireg_t sc_pci_id; 98 /* Chip description */ 99 const struct pciide_product_desc *sc_pp; 100 /* common definitions */ 101 struct channel_softc *wdc_chanarray[PCIIDE_NUM_CHANNELS]; 102 /* internal bookkeeping */ 103 struct pciide_channel { /* per-channel data */ 104 struct channel_softc wdc_channel; /* generic part */ 105 char *name; 106 int compat; /* is it compat? */ 107 void *ih; /* compat or pci handle */ 108 bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */ 109 /* DMA tables and DMA map for xfer, for each drive */ 110 struct pciide_dma_maps { 111 bus_dmamap_t dmamap_table; 112 struct idedma_table *dma_table; 113 bus_dmamap_t dmamap_xfer; 114 int dma_flags; 115 } dma_maps[2]; 116 bus_space_handle_t dma_iohs[IDEDMA_NREGS]; 117 } pciide_channels[PCIIDE_NUM_CHANNELS]; 118 }; 119 120 struct pciide_product_desc { 121 u_int32_t ide_product; 122 int ide_flags; 123 const char *ide_name; 124 /* map and setup chip, probe drives */ 125 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 126 }; 127 128 /* Flags for ide_flags */ 129 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 130 131 132 /* inlines for reading/writing 8-bit PCI registers */ 133 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 134 int)); 135 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 136 int, u_int8_t)); 137 138 static __inline u_int8_t 139 pciide_pci_read(pc, pa, reg) 140 pci_chipset_tag_t pc; 141 pcitag_t pa; 142 int reg; 143 { 144 145 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 146 ((reg & 0x03) * 8) & 0xff); 147 } 148 149 static __inline void 150 pciide_pci_write(pc, pa, reg, val) 151 pci_chipset_tag_t pc; 152 pcitag_t pa; 153 int reg; 154 u_int8_t val; 155 { 156 pcireg_t pcival; 157 158 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 159 pcival &= ~(0xff << ((reg & 0x03) * 8)); 160 pcival |= (val << ((reg & 0x03) * 8)); 161 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 162 } 163 164 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void sata_setup_channel __P((struct channel_softc*)); 166 167 void pciide_channel_dma_setup __P((struct pciide_channel *)); 168 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 169 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 170 void pciide_dma_start __P((void*, int, int)); 171 int pciide_dma_finish __P((void*, int, int, int)); 172 void pciide_irqack __P((struct channel_softc *)); 173 174 /* 175 * Functions defined by machine-dependent code. 176 */ 177 178 /* Attach compat interrupt handler, returning handle or NULL if failed. */ 179 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 180 void *pciide_machdep_compat_intr_establish __P((struct device *, 181 struct pci_attach_args *, int, int (*)(void *), void *)); 182 #endif 183 184 const struct pciide_product_desc* pciide_lookup_product 185 __P((u_int32_t, const struct pciide_product_desc *)); 186 void pciide_common_attach 187 __P((struct pciide_softc *, struct pci_attach_args *, 188 const struct pciide_product_desc *)); 189 190 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 191 void pciide_mapregs_compat __P(( struct pci_attach_args *, 192 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 193 void pciide_mapregs_native __P((struct pci_attach_args *, 194 struct pciide_channel *, bus_size_t *, bus_size_t *, 195 int (*pci_intr) __P((void *)))); 196 void pciide_mapreg_dma __P((struct pciide_softc *, 197 struct pci_attach_args *)); 198 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 199 void pciide_mapchan __P((struct pci_attach_args *, 200 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 201 int (*pci_intr) __P((void *)))); 202 void pciide_map_compat_intr __P(( struct pci_attach_args *, 203 struct pciide_channel *, int)); 204 int pciide_compat_intr __P((void *)); 205 int pciide_pci_intr __P((void *)); 206
Indexes created Thu Sep 25 16:09:42 GMT 2025