pciidevar.h revision 1.15
1 /* $NetBSD: pciidevar.h,v 1.15 2003/12/17 21:08:29 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI IDE driver exported software structures. 35 * 36 * Author: Christopher G. Demetriou, March 2, 1998. 37 */ 38 39 #include <dev/ata/atavar.h> 40 #include <dev/ic/wdcreg.h> 41 #include <dev/ic/wdcvar.h> 42 #include "opt_pciide.h" 43 44 #ifndef WDCDEBUG 45 #define WDCDEBUG 46 #endif 47 48 #define DEBUG_DMA 0x01 49 #define DEBUG_XFERS 0x02 50 #define DEBUG_FUNCS 0x08 51 #define DEBUG_PROBE 0x10 52 #ifdef WDCDEBUG 53 extern int wdcdebug_pciide_mask; 54 #define WDCDEBUG_PRINT(args, level) \ 55 if (wdcdebug_pciide_mask & (level)) printf args 56 #else 57 #define WDCDEBUG_PRINT(args, level) 58 #endif 59 60 struct device; 61 62 struct pciide_softc { 63 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 64 pci_chipset_tag_t sc_pc; /* PCI registers info */ 65 pcitag_t sc_tag; 66 void *sc_pci_ih; /* PCI interrupt handle */ 67 int sc_dma_ok; /* bus-master DMA info */ 68 /* 69 * sc_dma_ioh may only be used to allocate the dma_iohs 70 * array in the channels (see below), or by chip-dependent 71 * code that knows what it's doing, as the registers may 72 * be laid out differently. All code in pciide_common.c 73 * must use the channel->dma_iohs array. 74 */ 75 bus_space_tag_t sc_dma_iot; 76 bus_space_handle_t sc_dma_ioh; 77 bus_dma_tag_t sc_dmat; 78 79 /* 80 * Some controllers might have DMA restrictions other than 81 * the norm. 82 */ 83 bus_size_t sc_dma_maxsegsz; 84 bus_size_t sc_dma_boundary; 85 86 /* For VIA/AMD/nVidia */ 87 bus_addr_t sc_apo_regbase; 88 89 /* For Cypress */ 90 const struct cy82c693_handle *sc_cy_handle; 91 int sc_cy_compatchan; 92 93 /* for SiS */ 94 u_int8_t sis_type; 95 96 /* For Silicon Image SATALink */ 97 bus_space_tag_t sc_ba5_st; 98 bus_space_handle_t sc_ba5_sh; 99 int sc_ba5_en; 100 101 /* Vendor info (for interpreting Chip description) */ 102 pcireg_t sc_pci_id; 103 /* Chip description */ 104 const struct pciide_product_desc *sc_pp; 105 /* common definitions */ 106 struct channel_softc *wdc_chanarray[PCIIDE_NUM_CHANNELS]; 107 /* internal bookkeeping */ 108 struct pciide_channel { /* per-channel data */ 109 struct channel_softc wdc_channel; /* generic part */ 110 char *name; 111 int compat; /* is it compat? */ 112 void *ih; /* compat or pci handle */ 113 bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */ 114 /* DMA tables and DMA map for xfer, for each drive */ 115 struct pciide_dma_maps { 116 bus_dmamap_t dmamap_table; 117 struct idedma_table *dma_table; 118 bus_dmamap_t dmamap_xfer; 119 int dma_flags; 120 } dma_maps[2]; 121 bus_space_handle_t dma_iohs[IDEDMA_NREGS]; 122 } pciide_channels[PCIIDE_NUM_CHANNELS]; 123 }; 124 125 struct pciide_product_desc { 126 u_int32_t ide_product; 127 int ide_flags; 128 const char *ide_name; 129 /* map and setup chip, probe drives */ 130 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 131 }; 132 133 /* Flags for ide_flags */ 134 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 135 136 137 /* inlines for reading/writing 8-bit PCI registers */ 138 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 139 int)); 140 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 141 int, u_int8_t)); 142 143 static __inline u_int8_t 144 pciide_pci_read(pc, pa, reg) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 { 149 150 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 151 ((reg & 0x03) * 8) & 0xff); 152 } 153 154 static __inline void 155 pciide_pci_write(pc, pa, reg, val) 156 pci_chipset_tag_t pc; 157 pcitag_t pa; 158 int reg; 159 u_int8_t val; 160 { 161 pcireg_t pcival; 162 163 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 164 pcival &= ~(0xff << ((reg & 0x03) * 8)); 165 pcival |= (val << ((reg & 0x03) * 8)); 166 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 167 } 168 169 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 170 void sata_setup_channel __P((struct channel_softc*)); 171 172 void pciide_channel_dma_setup __P((struct pciide_channel *)); 173 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 174 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 175 void pciide_dma_start __P((void*, int, int)); 176 int pciide_dma_finish __P((void*, int, int, int)); 177 void pciide_irqack __P((struct channel_softc *)); 178 179 /* 180 * Functions defined by machine-dependent code. 181 */ 182 183 /* Attach compat interrupt handler, returning handle or NULL if failed. */ 184 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 185 void *pciide_machdep_compat_intr_establish __P((struct device *, 186 struct pci_attach_args *, int, int (*)(void *), void *)); 187 #endif 188 189 const struct pciide_product_desc* pciide_lookup_product 190 __P((u_int32_t, const struct pciide_product_desc *)); 191 void pciide_common_attach 192 __P((struct pciide_softc *, struct pci_attach_args *, 193 const struct pciide_product_desc *)); 194 195 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 196 void pciide_mapregs_compat __P(( struct pci_attach_args *, 197 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 198 void pciide_mapregs_native __P((struct pci_attach_args *, 199 struct pciide_channel *, bus_size_t *, bus_size_t *, 200 int (*pci_intr) __P((void *)))); 201 void pciide_mapreg_dma __P((struct pciide_softc *, 202 struct pci_attach_args *)); 203 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 204 void pciide_mapchan __P((struct pci_attach_args *, 205 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 206 int (*pci_intr) __P((void *)))); 207 void pciide_map_compat_intr __P(( struct pci_attach_args *, 208 struct pciide_channel *, int)); 209 int pciide_compat_intr __P((void *)); 210 int pciide_pci_intr __P((void *)); 211
Indexes created Wed Sep 24 05:09:52 GMT 2025