pciidevar.h revision 1.18
1 /* $NetBSD: pciidevar.h,v 1.18 2003/12/19 19:09:20 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI IDE driver exported software structures. 35 * 36 * Author: Christopher G. Demetriou, March 2, 1998. 37 */ 38 39 #include <dev/ata/atavar.h> 40 #include <dev/ic/wdcreg.h> 41 #include <dev/ic/wdcvar.h> 42 #include "opt_pciide.h" 43 44 /* options passed via the 'flags' config keyword */ 45 #define PCIIDE_OPTIONS_DMA 0x01 46 #define PCIIDE_OPTIONS_NODMA 0x02 47 48 #ifndef WDCDEBUG 49 #define WDCDEBUG 50 #endif 51 52 #define DEBUG_DMA 0x01 53 #define DEBUG_XFERS 0x02 54 #define DEBUG_FUNCS 0x08 55 #define DEBUG_PROBE 0x10 56 #ifdef WDCDEBUG 57 extern int wdcdebug_pciide_mask; 58 #define WDCDEBUG_PRINT(args, level) \ 59 if (wdcdebug_pciide_mask & (level)) printf args 60 #else 61 #define WDCDEBUG_PRINT(args, level) 62 #endif 63 64 struct device; 65 66 struct pciide_softc { 67 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 68 pci_chipset_tag_t sc_pc; /* PCI registers info */ 69 pcitag_t sc_tag; 70 void *sc_pci_ih; /* PCI interrupt handle */ 71 int sc_dma_ok; /* bus-master DMA info */ 72 /* 73 * sc_dma_ioh may only be used to allocate the dma_iohs 74 * array in the channels (see below), or by chip-dependent 75 * code that knows what it's doing, as the registers may 76 * be laid out differently. All code in pciide_common.c 77 * must use the channel->dma_iohs array. 78 */ 79 bus_space_tag_t sc_dma_iot; 80 bus_space_handle_t sc_dma_ioh; 81 bus_dma_tag_t sc_dmat; 82 83 /* 84 * Some controllers might have DMA restrictions other than 85 * the norm. 86 */ 87 bus_size_t sc_dma_maxsegsz; 88 bus_size_t sc_dma_boundary; 89 90 /* For VIA/AMD/nVidia */ 91 bus_addr_t sc_apo_regbase; 92 93 /* For Cypress */ 94 const struct cy82c693_handle *sc_cy_handle; 95 int sc_cy_compatchan; 96 97 /* for SiS */ 98 u_int8_t sis_type; 99 100 /* For Silicon Image SATALink */ 101 bus_space_tag_t sc_ba5_st; 102 bus_space_handle_t sc_ba5_sh; 103 int sc_ba5_en; 104 105 /* Vendor info (for interpreting Chip description) */ 106 pcireg_t sc_pci_id; 107 /* Chip description */ 108 const struct pciide_product_desc *sc_pp; 109 /* common definitions */ 110 struct channel_softc *wdc_chanarray[PCIIDE_NUM_CHANNELS]; 111 /* internal bookkeeping */ 112 struct pciide_channel { /* per-channel data */ 113 struct channel_softc wdc_channel; /* generic part */ 114 const char *name; 115 int compat; /* is it compat? */ 116 void *ih; /* compat or pci handle */ 117 bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */ 118 /* DMA tables and DMA map for xfer, for each drive */ 119 struct pciide_dma_maps { 120 bus_dmamap_t dmamap_table; 121 struct idedma_table *dma_table; 122 bus_dmamap_t dmamap_xfer; 123 int dma_flags; 124 } dma_maps[2]; 125 bus_space_handle_t dma_iohs[IDEDMA_NREGS]; 126 /* 127 * Some controllers require certain bits to 128 * always be set for proper operation of the 129 * controller. Set those bits here, if they're 130 * required. 131 */ 132 uint8_t idedma_cmd; 133 } pciide_channels[PCIIDE_NUM_CHANNELS]; 134 }; 135 136 struct pciide_product_desc { 137 u_int32_t ide_product; 138 int ide_flags; 139 const char *ide_name; 140 /* map and setup chip, probe drives */ 141 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 142 }; 143 144 /* Flags for ide_flags */ 145 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 146 147 148 /* inlines for reading/writing 8-bit PCI registers */ 149 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 150 int)); 151 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 152 int, u_int8_t)); 153 154 static __inline u_int8_t 155 pciide_pci_read(pc, pa, reg) 156 pci_chipset_tag_t pc; 157 pcitag_t pa; 158 int reg; 159 { 160 161 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 162 ((reg & 0x03) * 8) & 0xff); 163 } 164 165 static __inline void 166 pciide_pci_write(pc, pa, reg, val) 167 pci_chipset_tag_t pc; 168 pcitag_t pa; 169 int reg; 170 u_int8_t val; 171 { 172 pcireg_t pcival; 173 174 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 175 pcival &= ~(0xff << ((reg & 0x03) * 8)); 176 pcival |= (val << ((reg & 0x03) * 8)); 177 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 178 } 179 180 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void sata_setup_channel __P((struct channel_softc*)); 182 183 void pciide_channel_dma_setup __P((struct pciide_channel *)); 184 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 185 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 186 void pciide_dma_start __P((void*, int, int)); 187 int pciide_dma_finish __P((void*, int, int, int)); 188 void pciide_irqack __P((struct channel_softc *)); 189 190 /* 191 * Functions defined by machine-dependent code. 192 */ 193 194 /* Attach compat interrupt handler, returning handle or NULL if failed. */ 195 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 196 void *pciide_machdep_compat_intr_establish __P((struct device *, 197 struct pci_attach_args *, int, int (*)(void *), void *)); 198 #endif 199 200 const struct pciide_product_desc* pciide_lookup_product 201 __P((u_int32_t, const struct pciide_product_desc *)); 202 void pciide_common_attach 203 __P((struct pciide_softc *, struct pci_attach_args *, 204 const struct pciide_product_desc *)); 205 206 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 207 void pciide_mapregs_compat __P(( struct pci_attach_args *, 208 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 209 void pciide_mapregs_native __P((struct pci_attach_args *, 210 struct pciide_channel *, bus_size_t *, bus_size_t *, 211 int (*pci_intr) __P((void *)))); 212 void pciide_mapreg_dma __P((struct pciide_softc *, 213 struct pci_attach_args *)); 214 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 215 void pciide_mapchan __P((struct pci_attach_args *, 216 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 217 int (*pci_intr) __P((void *)))); 218 void pciide_map_compat_intr __P(( struct pci_attach_args *, 219 struct pciide_channel *, int)); 220 int pciide_compat_intr __P((void *)); 221 int pciide_pci_intr __P((void *)); 222
Indexes created Wed Sep 24 22:09:59 GMT 2025