pciidevar.h revision 1.22
1 /* $NetBSD: pciidevar.h,v 1.22 2004/08/14 15:08:06 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI IDE driver exported software structures. 35 * 36 * Author: Christopher G. Demetriou, March 2, 1998. 37 */ 38 39 #include <dev/ata/atavar.h> 40 #include <dev/ic/wdcreg.h> 41 #include <dev/ic/wdcvar.h> 42 #include "opt_pciide.h" 43 44 /* options passed via the 'flags' config keyword */ 45 #define PCIIDE_OPTIONS_DMA 0x01 46 #define PCIIDE_OPTIONS_NODMA 0x02 47 48 #ifndef ATADEBUG 49 #define ATADEBUG 50 #endif 51 52 #define DEBUG_DMA 0x01 53 #define DEBUG_XFERS 0x02 54 #define DEBUG_FUNCS 0x08 55 #define DEBUG_PROBE 0x10 56 #ifdef ATADEBUG 57 extern int atadebug_pciide_mask; 58 #define ATADEBUG_PRINT(args, level) \ 59 if (atadebug_pciide_mask & (level)) printf args 60 #else 61 #define ATADEBUG_PRINT(args, level) 62 #endif 63 64 struct device; 65 66 /* 67 * While standard PCI IDE controllers only have 2 channels, it is 68 * common for PCI SATA controllers to have more. Here we define 69 * the maximum number of channels that any one PCI IDE device can 70 * have. 71 */ 72 #define PCIIDE_MAX_CHANNELS 4 73 74 struct pciide_softc { 75 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 76 pci_chipset_tag_t sc_pc; /* PCI registers info */ 77 pcitag_t sc_tag; 78 void *sc_pci_ih; /* PCI interrupt handle */ 79 int sc_dma_ok; /* bus-master DMA info */ 80 /* 81 * sc_dma_ioh may only be used to allocate the dma_iohs 82 * array in the channels (see below), or by chip-dependent 83 * code that knows what it's doing, as the registers may 84 * be laid out differently. All code in pciide_common.c 85 * must use the channel->dma_iohs array. 86 */ 87 bus_space_tag_t sc_dma_iot; 88 bus_space_handle_t sc_dma_ioh; 89 bus_dma_tag_t sc_dmat; 90 91 /* 92 * Some controllers might have DMA restrictions other than 93 * the norm. 94 */ 95 bus_size_t sc_dma_maxsegsz; 96 bus_size_t sc_dma_boundary; 97 98 /* For VIA/AMD/nVidia */ 99 bus_addr_t sc_apo_regbase; 100 101 /* For Cypress */ 102 const struct cy82c693_handle *sc_cy_handle; 103 int sc_cy_compatchan; 104 105 /* for SiS */ 106 u_int8_t sis_type; 107 108 /* For Silicon Image SATALink */ 109 bus_space_tag_t sc_ba5_st; 110 bus_space_handle_t sc_ba5_sh; 111 int sc_ba5_en; 112 113 /* Vendor info (for interpreting Chip description) */ 114 pcireg_t sc_pci_id; 115 /* Chip description */ 116 const struct pciide_product_desc *sc_pp; 117 /* common definitions */ 118 struct ata_channel *wdc_chanarray[PCIIDE_MAX_CHANNELS]; 119 /* internal bookkeeping */ 120 struct pciide_channel { /* per-channel data */ 121 struct ata_channel ata_channel; /* generic part */ 122 const char *name; 123 int compat; /* is it compat? */ 124 void *ih; /* compat or pci handle */ 125 bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */ 126 /* DMA tables and DMA map for xfer, for each drive */ 127 struct pciide_dma_maps { 128 bus_dmamap_t dmamap_table; 129 struct idedma_table *dma_table; 130 bus_dmamap_t dmamap_xfer; 131 int dma_flags; 132 } dma_maps[2]; 133 bus_space_handle_t dma_iohs[IDEDMA_NREGS]; 134 /* 135 * Some controllers require certain bits to 136 * always be set for proper operation of the 137 * controller. Set those bits here, if they're 138 * required. 139 */ 140 uint8_t idedma_cmd; 141 } pciide_channels[PCIIDE_MAX_CHANNELS]; 142 }; 143 144 struct pciide_product_desc { 145 u_int32_t ide_product; 146 int ide_flags; 147 const char *ide_name; 148 /* map and setup chip, probe drives */ 149 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 150 }; 151 152 /* Flags for ide_flags */ 153 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 154 155 156 /* inlines for reading/writing 8-bit PCI registers */ 157 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 158 int)); 159 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 160 int, u_int8_t)); 161 162 static __inline u_int8_t 163 pciide_pci_read(pc, pa, reg) 164 pci_chipset_tag_t pc; 165 pcitag_t pa; 166 int reg; 167 { 168 169 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 170 ((reg & 0x03) * 8) & 0xff); 171 } 172 173 static __inline void 174 pciide_pci_write(pc, pa, reg, val) 175 pci_chipset_tag_t pc; 176 pcitag_t pa; 177 int reg; 178 u_int8_t val; 179 { 180 pcireg_t pcival; 181 182 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 183 pcival &= ~(0xff << ((reg & 0x03) * 8)); 184 pcival |= (val << ((reg & 0x03) * 8)); 185 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 186 } 187 188 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void sata_setup_channel __P((struct ata_channel*)); 190 191 void pciide_channel_dma_setup __P((struct pciide_channel *)); 192 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 193 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 194 void pciide_dma_start __P((void*, int, int)); 195 int pciide_dma_finish __P((void*, int, int, int)); 196 void pciide_irqack __P((struct ata_channel *)); 197 198 /* 199 * Functions defined by machine-dependent code. 200 */ 201 202 /* Attach compat interrupt handler, returning handle or NULL if failed. */ 203 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 204 void *pciide_machdep_compat_intr_establish __P((struct device *, 205 struct pci_attach_args *, int, int (*)(void *), void *)); 206 #endif 207 208 const struct pciide_product_desc* pciide_lookup_product 209 __P((u_int32_t, const struct pciide_product_desc *)); 210 void pciide_common_attach 211 __P((struct pciide_softc *, struct pci_attach_args *, 212 const struct pciide_product_desc *)); 213 214 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 215 void pciide_mapregs_compat __P(( struct pci_attach_args *, 216 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 217 void pciide_mapregs_native __P((struct pci_attach_args *, 218 struct pciide_channel *, bus_size_t *, bus_size_t *, 219 int (*pci_intr) __P((void *)))); 220 void pciide_mapreg_dma __P((struct pciide_softc *, 221 struct pci_attach_args *)); 222 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 223 void pciide_mapchan __P((struct pci_attach_args *, 224 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 225 int (*pci_intr) __P((void *)))); 226 void pciide_map_compat_intr __P(( struct pci_attach_args *, 227 struct pciide_channel *, int)); 228 int pciide_compat_intr __P((void *)); 229 int pciide_pci_intr __P((void *)); 230
Indexes created Tue Sep 23 07:09:52 GMT 2025