pciidevar.h revision 1.26
1 /* $NetBSD: pciidevar.h,v 1.26 2004/11/24 19:52:50 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_PCI_PCIIDEVAR_H_ 34 #define _DEV_PCI_PCIIDEVAR_H_ 35 36 /* 37 * PCI IDE driver exported software structures. 38 * 39 * Author: Christopher G. Demetriou, March 2, 1998. 40 */ 41 42 #include <dev/ata/atavar.h> 43 #include <dev/ic/wdcreg.h> 44 #include <dev/ic/wdcvar.h> 45 #include "opt_pciide.h" 46 47 /* options passed via the 'flags' config keyword */ 48 #define PCIIDE_OPTIONS_DMA 0x01 49 #define PCIIDE_OPTIONS_NODMA 0x02 50 51 #ifndef ATADEBUG 52 #define ATADEBUG 53 #endif 54 55 #define DEBUG_DMA 0x01 56 #define DEBUG_XFERS 0x02 57 #define DEBUG_FUNCS 0x08 58 #define DEBUG_PROBE 0x10 59 #ifdef ATADEBUG 60 extern int atadebug_pciide_mask; 61 #define ATADEBUG_PRINT(args, level) \ 62 if (atadebug_pciide_mask & (level)) printf args 63 #else 64 #define ATADEBUG_PRINT(args, level) 65 #endif 66 67 struct device; 68 69 /* 70 * While standard PCI IDE controllers only have 2 channels, it is 71 * common for PCI SATA controllers to have more. Here we define 72 * the maximum number of channels that any one PCI IDE device can 73 * have. 74 */ 75 #define PCIIDE_MAX_CHANNELS 4 76 77 struct pciide_softc { 78 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 79 pci_chipset_tag_t sc_pc; /* PCI registers info */ 80 pcitag_t sc_tag; 81 void *sc_pci_ih; /* PCI interrupt handle */ 82 int sc_dma_ok; /* bus-master DMA info */ 83 /* 84 * sc_dma_ioh may only be used to allocate the dma_iohs 85 * array in the channels (see below), or by chip-dependent 86 * code that knows what it's doing, as the registers may 87 * be laid out differently. All code in pciide_common.c 88 * must use the channel->dma_iohs array. 89 */ 90 bus_space_tag_t sc_dma_iot; 91 bus_space_handle_t sc_dma_ioh; 92 bus_dma_tag_t sc_dmat; 93 94 /* 95 * Some controllers might have DMA restrictions other than 96 * the norm. 97 */ 98 bus_size_t sc_dma_maxsegsz; 99 bus_size_t sc_dma_boundary; 100 101 /* For VIA/AMD/nVidia */ 102 bus_addr_t sc_apo_regbase; 103 104 /* For Cypress */ 105 const struct cy82c693_handle *sc_cy_handle; 106 int sc_cy_compatchan; 107 108 /* for SiS */ 109 u_int8_t sis_type; 110 111 /* For Silicon Image SATALink, and Promise SATA */ 112 bus_space_tag_t sc_ba5_st; 113 bus_space_handle_t sc_ba5_sh; 114 int sc_ba5_en; 115 116 /* Vendor info (for interpreting Chip description) */ 117 pcireg_t sc_pci_id; 118 /* Chip description */ 119 const struct pciide_product_desc *sc_pp; 120 /* common definitions */ 121 struct ata_channel *wdc_chanarray[PCIIDE_MAX_CHANNELS]; 122 /* internal bookkeeping */ 123 struct pciide_channel { /* per-channel data */ 124 struct ata_channel ata_channel; /* generic part */ 125 const char *name; 126 int compat; /* is it compat? */ 127 void *ih; /* compat or pci handle */ 128 bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */ 129 /* DMA tables and DMA map for xfer, for each drive */ 130 struct pciide_dma_maps { 131 bus_dmamap_t dmamap_table; 132 struct idedma_table *dma_table; 133 bus_dmamap_t dmamap_xfer; 134 int dma_flags; 135 } dma_maps[2]; 136 bus_space_handle_t dma_iohs[IDEDMA_NREGS]; 137 /* 138 * Some controllers require certain bits to 139 * always be set for proper operation of the 140 * controller. Set those bits here, if they're 141 * required. 142 */ 143 uint8_t idedma_cmd; 144 } pciide_channels[PCIIDE_MAX_CHANNELS]; 145 }; 146 147 /* Given an ata_channel, get the pciide_softc. */ 148 #define CHAN_TO_PCIIDE(chp) ((struct pciide_softc *) (chp)->ch_atac) 149 150 /* Given an ata_channel, get the pciide_channel. */ 151 #define CHAN_TO_PCHAN(chp) ((struct pciide_channel *) (chp)) 152 153 struct pciide_product_desc { 154 u_int32_t ide_product; 155 int ide_flags; 156 const char *ide_name; 157 /* map and setup chip, probe drives */ 158 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 159 }; 160 161 /* Flags for ide_flags */ 162 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 163 164 165 /* inlines for reading/writing 8-bit PCI registers */ 166 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 167 int)); 168 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 169 int, u_int8_t)); 170 171 static __inline u_int8_t 172 pciide_pci_read(pc, pa, reg) 173 pci_chipset_tag_t pc; 174 pcitag_t pa; 175 int reg; 176 { 177 178 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 179 ((reg & 0x03) * 8) & 0xff); 180 } 181 182 static __inline void 183 pciide_pci_write(pc, pa, reg, val) 184 pci_chipset_tag_t pc; 185 pcitag_t pa; 186 int reg; 187 u_int8_t val; 188 { 189 pcireg_t pcival; 190 191 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 192 pcival &= ~(0xff << ((reg & 0x03) * 8)); 193 pcival |= (val << ((reg & 0x03) * 8)); 194 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 195 } 196 197 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 198 void sata_setup_channel __P((struct ata_channel*)); 199 200 void pciide_channel_dma_setup __P((struct pciide_channel *)); 201 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 202 int pciide_dma_dmamap_setup __P((struct pciide_softc *, int, int, 203 void *, size_t, int)); 204 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 205 void pciide_dma_start __P((void*, int, int)); 206 int pciide_dma_finish __P((void*, int, int, int)); 207 void pciide_irqack __P((struct ata_channel *)); 208 209 /* 210 * Functions defined by machine-dependent code. 211 */ 212 213 /* Attach compat interrupt handler, returning handle or NULL if failed. */ 214 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 215 void *pciide_machdep_compat_intr_establish __P((struct device *, 216 struct pci_attach_args *, int, int (*)(void *), void *)); 217 #endif 218 219 const struct pciide_product_desc* pciide_lookup_product 220 __P((u_int32_t, const struct pciide_product_desc *)); 221 void pciide_common_attach 222 __P((struct pciide_softc *, struct pci_attach_args *, 223 const struct pciide_product_desc *)); 224 225 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 226 void pciide_mapregs_compat __P(( struct pci_attach_args *, 227 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 228 void pciide_mapregs_native __P((struct pci_attach_args *, 229 struct pciide_channel *, bus_size_t *, bus_size_t *, 230 int (*pci_intr) __P((void *)))); 231 void pciide_mapreg_dma __P((struct pciide_softc *, 232 struct pci_attach_args *)); 233 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 234 void pciide_mapchan __P((struct pci_attach_args *, 235 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 236 int (*pci_intr) __P((void *)))); 237 void pciide_map_compat_intr __P(( struct pci_attach_args *, 238 struct pciide_channel *, int)); 239 int pciide_compat_intr __P((void *)); 240 int pciide_pci_intr __P((void *)); 241 242 #endif /* _DEV_PCI_PCIIDEVAR_H_ */ 243
Indexes created Thu Sep 25 06:09:39 GMT 2025