pciidevar.h revision 1.35
1 /* $NetBSD: pciidevar.h,v 1.35 2006/10/17 13:45:05 itohy Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_PCI_PCIIDEVAR_H_ 34 #define _DEV_PCI_PCIIDEVAR_H_ 35 36 /* 37 * PCI IDE driver exported software structures. 38 * 39 * Author: Christopher G. Demetriou, March 2, 1998. 40 */ 41 42 #include <dev/ata/atavar.h> 43 #include <dev/ic/wdcreg.h> 44 #include <dev/ic/wdcvar.h> 45 #include "opt_pciide.h" 46 47 /* options passed via the 'flags' config keyword */ 48 #define PCIIDE_OPTIONS_DMA 0x01 49 #define PCIIDE_OPTIONS_NODMA 0x02 50 51 #ifndef ATADEBUG 52 #define ATADEBUG 53 #endif 54 55 #define DEBUG_DMA 0x01 56 #define DEBUG_XFERS 0x02 57 #define DEBUG_FUNCS 0x08 58 #define DEBUG_PROBE 0x10 59 #ifdef ATADEBUG 60 extern int atadebug_pciide_mask; 61 #define ATADEBUG_PRINT(args, level) \ 62 if (atadebug_pciide_mask & (level)) printf args 63 #else 64 #define ATADEBUG_PRINT(args, level) 65 #endif 66 67 struct device; 68 69 /* 70 * While standard PCI IDE controllers only have 2 channels, it is 71 * common for PCI SATA controllers to have more. Here we define 72 * the maximum number of channels that any one PCI IDE device can 73 * have. 74 */ 75 #define PCIIDE_MAX_CHANNELS 4 76 77 struct pciide_softc { 78 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 79 pci_chipset_tag_t sc_pc; /* PCI registers info */ 80 pcitag_t sc_tag; 81 void *sc_pci_ih; /* PCI interrupt handle */ 82 #if NATA_DMA 83 int sc_dma_ok; /* bus-master DMA info */ 84 /* 85 * sc_dma_ioh may only be used to allocate the dma_iohs 86 * array in the channels (see below), or by chip-dependent 87 * code that knows what it's doing, as the registers may 88 * be laid out differently. All code in pciide_common.c 89 * must use the channel->dma_iohs array. 90 */ 91 bus_space_tag_t sc_dma_iot; 92 bus_space_handle_t sc_dma_ioh; 93 bus_dma_tag_t sc_dmat; 94 95 /* 96 * Some controllers might have DMA restrictions other than 97 * the norm. 98 */ 99 bus_size_t sc_dma_maxsegsz; 100 bus_size_t sc_dma_boundary; 101 102 /* For VIA/AMD/nVidia */ 103 bus_addr_t sc_apo_regbase; 104 105 /* For Cypress */ 106 const struct cy82c693_handle *sc_cy_handle; 107 int sc_cy_compatchan; 108 109 /* for SiS */ 110 u_int8_t sis_type; 111 112 /* 113 * For Silicon Image SATALink, Serverworks SATA, Artisea SATA 114 * and Promise SATA 115 */ 116 bus_space_tag_t sc_ba5_st; 117 bus_space_handle_t sc_ba5_sh; 118 int sc_ba5_en; 119 #endif /* NATA_DMA */ 120 121 /* Vendor info (for interpreting Chip description) */ 122 pcireg_t sc_pci_id; 123 /* Chip description */ 124 const struct pciide_product_desc *sc_pp; 125 /* common definitions */ 126 struct ata_channel *wdc_chanarray[PCIIDE_MAX_CHANNELS]; 127 /* internal bookkeeping */ 128 struct pciide_channel { /* per-channel data */ 129 struct ata_channel ata_channel; /* generic part */ 130 const char *name; 131 int compat; /* is it compat? */ 132 void *ih; /* compat or pci handle */ 133 bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */ 134 #if NATA_DMA 135 /* DMA tables and DMA map for xfer, for each drive */ 136 struct pciide_dma_maps { 137 bus_dmamap_t dmamap_table; 138 struct idedma_table *dma_table; 139 bus_dmamap_t dmamap_xfer; 140 int dma_flags; 141 } dma_maps[2]; 142 bus_space_handle_t dma_iohs[IDEDMA_NREGS]; 143 /* 144 * Some controllers require certain bits to 145 * always be set for proper operation of the 146 * controller. Set those bits here, if they're 147 * required. 148 */ 149 uint8_t idedma_cmd; 150 #endif /* NATA_DMA */ 151 } pciide_channels[PCIIDE_MAX_CHANNELS]; 152 153 /* Power management */ 154 void *sc_powerhook; 155 struct pci_conf_state sc_pciconf; /* Restore buffer */ 156 /* Intel power management */ 157 pcireg_t sc_idetim; 158 pcireg_t sc_udmatim; 159 }; 160 161 /* Given an ata_channel, get the pciide_softc. */ 162 #define CHAN_TO_PCIIDE(chp) ((struct pciide_softc *) (chp)->ch_atac) 163 164 /* Given an ata_channel, get the pciide_channel. */ 165 #define CHAN_TO_PCHAN(chp) ((struct pciide_channel *) (chp)) 166 167 struct pciide_product_desc { 168 u_int32_t ide_product; 169 int ide_flags; 170 const char *ide_name; 171 /* map and setup chip, probe drives */ 172 void (*chip_map)(struct pciide_softc*, struct pci_attach_args*); 173 }; 174 175 /* Flags for ide_flags */ 176 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 177 178 179 /* inlines for reading/writing 8-bit PCI registers */ 180 static inline u_int8_t pciide_pci_read(pci_chipset_tag_t, pcitag_t, int); 181 static inline void pciide_pci_write(pci_chipset_tag_t, pcitag_t, 182 int, u_int8_t); 183 184 static inline u_int8_t 185 pciide_pci_read(pc, pa, reg) 186 pci_chipset_tag_t pc; 187 pcitag_t pa; 188 int reg; 189 { 190 191 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 192 ((reg & 0x03) * 8) & 0xff); 193 } 194 195 static inline void 196 pciide_pci_write(pc, pa, reg, val) 197 pci_chipset_tag_t pc; 198 pcitag_t pa; 199 int reg; 200 u_int8_t val; 201 { 202 pcireg_t pcival; 203 204 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 205 pcival &= ~(0xff << ((reg & 0x03) * 8)); 206 pcival |= (val << ((reg & 0x03) * 8)); 207 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 208 } 209 210 void default_chip_map(struct pciide_softc*, struct pci_attach_args*); 211 void sata_setup_channel(struct ata_channel*); 212 213 void pciide_channel_dma_setup(struct pciide_channel *); 214 int pciide_dma_table_setup(struct pciide_softc*, int, int); 215 int pciide_dma_dmamap_setup(struct pciide_softc *, int, int, 216 void *, size_t, int); 217 int pciide_dma_init(void*, int, int, void *, size_t, int); 218 void pciide_dma_start(void*, int, int); 219 int pciide_dma_finish(void*, int, int, int); 220 void pciide_irqack(struct ata_channel *); 221 222 /* 223 * Functions defined by machine-dependent code. 224 */ 225 226 /* Attach compat interrupt handler, returning handle or NULL if failed. */ 227 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 228 void *pciide_machdep_compat_intr_establish(struct device *, 229 struct pci_attach_args *, int, int (*)(void *), void *); 230 #endif 231 232 const struct pciide_product_desc* pciide_lookup_product 233 (u_int32_t, const struct pciide_product_desc *); 234 void pciide_common_attach(struct pciide_softc *, struct pci_attach_args *, 235 const struct pciide_product_desc *); 236 237 int pciide_chipen(struct pciide_softc *, struct pci_attach_args *); 238 void pciide_mapregs_compat(struct pci_attach_args *, 239 struct pciide_channel *, int, bus_size_t *, bus_size_t*); 240 void pciide_mapregs_native(struct pci_attach_args *, 241 struct pciide_channel *, bus_size_t *, bus_size_t *, 242 int (*pci_intr)(void *)); 243 void pciide_mapreg_dma(struct pciide_softc *, 244 struct pci_attach_args *); 245 int pciide_chansetup(struct pciide_softc *, int, pcireg_t); 246 void pciide_mapchan(struct pci_attach_args *, 247 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 248 int (*pci_intr)(void *)); 249 void pciide_map_compat_intr(struct pci_attach_args *, 250 struct pciide_channel *, int); 251 int pciide_compat_intr(void *); 252 int pciide_pci_intr(void *); 253 254 #endif /* _DEV_PCI_PCIIDEVAR_H_ */ 255
Indexes created Wed Sep 24 05:09:52 GMT 2025