pciidevar.h revision 1.43
1 /* $NetBSD: pciidevar.h,v 1.43 2011/04/04 20:37:56 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_PCI_PCIIDEVAR_H_ 34 #define _DEV_PCI_PCIIDEVAR_H_ 35 36 /* 37 * PCI IDE driver exported software structures. 38 * 39 * Author: Christopher G. Demetriou, March 2, 1998. 40 */ 41 42 #include <dev/ata/atavar.h> 43 #include <dev/ic/wdcreg.h> 44 #include <dev/ic/wdcvar.h> 45 #include <sys/device_if.h> 46 #include "opt_pciide.h" 47 48 /* options passed via the 'flags' config keyword */ 49 #define PCIIDE_OPTIONS_DMA 0x01 50 #define PCIIDE_OPTIONS_NODMA 0x02 51 52 #ifndef ATADEBUG 53 #define ATADEBUG 54 #endif 55 56 #define DEBUG_DMA 0x01 57 #define DEBUG_XFERS 0x02 58 #define DEBUG_FUNCS 0x08 59 #define DEBUG_PROBE 0x10 60 #ifdef ATADEBUG 61 extern int atadebug_pciide_mask; 62 #define ATADEBUG_PRINT(args, level) \ 63 if (atadebug_pciide_mask & (level)) printf args 64 #else 65 #define ATADEBUG_PRINT(args, level) 66 #endif 67 68 /* 69 * While standard PCI IDE controllers only have 2 channels, it is 70 * common for PCI SATA controllers to have more. Here we define 71 * the maximum number of channels that any one PCI IDE device can 72 * have. 73 */ 74 #define PCIIDE_MAX_CHANNELS 4 75 76 struct pciide_softc { 77 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 78 pci_chipset_tag_t sc_pc; /* PCI registers info */ 79 pcitag_t sc_tag; 80 void *sc_pci_ih; /* PCI interrupt handle */ 81 #if NATA_DMA 82 int sc_dma_ok; /* bus-master DMA info */ 83 /* 84 * sc_dma_ioh may only be used to allocate the dma_iohs 85 * array in the channels (see below), or by chip-dependent 86 * code that knows what it's doing, as the registers may 87 * be laid out differently. All code in pciide_common.c 88 * must use the channel->dma_iohs array. 89 */ 90 bus_space_tag_t sc_dma_iot; 91 bus_space_handle_t sc_dma_ioh; 92 bus_size_t sc_dma_ios; 93 bus_dma_tag_t sc_dmat; 94 95 /* 96 * Some controllers might have DMA restrictions other than 97 * the norm. 98 */ 99 bus_size_t sc_dma_maxsegsz; 100 bus_size_t sc_dma_boundary; 101 102 /* For VIA/AMD/nVidia */ 103 bus_addr_t sc_apo_regbase; 104 105 /* For Cypress */ 106 const struct cy82c693_handle *sc_cy_handle; 107 int sc_cy_compatchan; 108 109 /* for SiS */ 110 u_int8_t sis_type; 111 112 /* 113 * For Silicon Image SATALink, Serverworks SATA, Artisea SATA 114 * and Promise SATA 115 */ 116 bus_space_tag_t sc_ba5_st; 117 bus_space_handle_t sc_ba5_sh; 118 bus_size_t sc_ba5_ss; 119 int sc_ba5_en; 120 #endif /* NATA_DMA */ 121 122 /* Vendor info (for interpreting Chip description) */ 123 pcireg_t sc_pci_id; 124 /* Chip description */ 125 const struct pciide_product_desc *sc_pp; 126 /* common definitions */ 127 struct ata_channel *wdc_chanarray[PCIIDE_MAX_CHANNELS]; 128 /* internal bookkeeping */ 129 struct pciide_channel { /* per-channel data */ 130 struct ata_channel ata_channel; /* generic part */ 131 const char *name; 132 int compat; /* is it compat? */ 133 void *ih; /* compat or pci handle */ 134 bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */ 135 bus_size_t ctl_ios; 136 #if NATA_DMA 137 /* DMA tables and DMA map for xfer, for each drive */ 138 struct pciide_dma_maps { 139 bus_dma_segment_t dmamap_table_seg; 140 int dmamap_table_nseg; 141 bus_dmamap_t dmamap_table; 142 struct idedma_table *dma_table; 143 bus_dmamap_t dmamap_xfer; 144 int dma_flags; 145 } dma_maps[ATA_MAXDRIVES]; 146 bus_space_handle_t dma_iohs[IDEDMA_NREGS]; 147 /* 148 * Some controllers require certain bits to 149 * always be set for proper operation of the 150 * controller. Set those bits here, if they're 151 * required. 152 */ 153 uint8_t idedma_cmd; 154 #endif /* NATA_DMA */ 155 } pciide_channels[PCIIDE_MAX_CHANNELS]; 156 157 pcireg_t sc_pm_reg[4]; 158 }; 159 160 /* Given an ata_channel, get the pciide_softc. */ 161 #define CHAN_TO_PCIIDE(chp) ((struct pciide_softc *) (chp)->ch_atac) 162 163 /* Given an ata_channel, get the pciide_channel. */ 164 #define CHAN_TO_PCHAN(chp) ((struct pciide_channel *) (chp)) 165 166 struct pciide_product_desc { 167 u_int32_t ide_product; 168 int ide_flags; 169 const char *ide_name; 170 /* map and setup chip, probe drives */ 171 void (*chip_map)(struct pciide_softc*, const struct pci_attach_args*); 172 }; 173 174 /* Flags for ide_flags */ 175 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 176 177 178 /* inlines for reading/writing 8-bit PCI registers */ 179 static inline u_int8_t pciide_pci_read(pci_chipset_tag_t, pcitag_t, int); 180 static inline void pciide_pci_write(pci_chipset_tag_t, pcitag_t, 181 int, u_int8_t); 182 183 static inline u_int8_t 184 pciide_pci_read(pci_chipset_tag_t pc, pcitag_t pa, int reg) 185 { 186 187 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 188 ((reg & 0x03) * 8) & 0xff); 189 } 190 191 static inline void 192 pciide_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, uint8_t val) 193 { 194 pcireg_t pcival; 195 196 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 197 pcival &= ~(0xff << ((reg & 0x03) * 8)); 198 pcival |= (val << ((reg & 0x03) * 8)); 199 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 200 } 201 202 void default_chip_map(struct pciide_softc*, const struct pci_attach_args*); 203 void sata_setup_channel(struct ata_channel*); 204 205 void pciide_channel_dma_setup(struct pciide_channel *); 206 int pciide_dma_table_setup(struct pciide_softc*, int, int); 207 void pciide_dma_table_teardown(struct pciide_softc *, int, int); 208 209 int pciide_dma_dmamap_setup(struct pciide_softc *, int, int, 210 void *, size_t, int); 211 int pciide_dma_init(void*, int, int, void *, size_t, int); 212 void pciide_dma_start(void*, int, int); 213 int pciide_dma_finish(void*, int, int, int); 214 void pciide_irqack(struct ata_channel *); 215 216 /* 217 * Functions defined by machine-dependent code. 218 */ 219 220 /* Attach compat interrupt handler, returning handle or NULL if failed. */ 221 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 222 void *pciide_machdep_compat_intr_establish(device_t, 223 const struct pci_attach_args *, int, int (*)(void *), void *); 224 #endif 225 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH 226 void pciide_machdep_compat_intr_disestablish(device_t, 227 pci_chipset_tag_t, int, void *); 228 #endif 229 230 const struct pciide_product_desc* pciide_lookup_product 231 (u_int32_t, const struct pciide_product_desc *); 232 void pciide_common_attach(struct pciide_softc *, 233 const struct pci_attach_args *, 234 const struct pciide_product_desc *); 235 int pciide_common_detach(struct pciide_softc *, int); 236 int pciide_detach(device_t, int); 237 238 int pciide_chipen(struct pciide_softc *, const struct pci_attach_args *); 239 void pciide_mapregs_compat(const struct pci_attach_args *, 240 struct pciide_channel *, int); 241 void pciide_mapregs_native(const struct pci_attach_args *, 242 struct pciide_channel *, int (*pci_intr)(void *)); 243 void pciide_mapreg_dma(struct pciide_softc *, 244 const struct pci_attach_args *); 245 int pciide_chansetup(struct pciide_softc *, int, pcireg_t); 246 void pciide_mapchan(const struct pci_attach_args *, 247 struct pciide_channel *, pcireg_t, int (*pci_intr)(void *)); 248 void pciide_map_compat_intr(const struct pci_attach_args *, 249 struct pciide_channel *, int); 250 void pciide_unmap_compat_intr(pci_chipset_tag_t, 251 struct pciide_channel *, int); 252 int pciide_compat_intr(void *); 253 int pciide_pci_intr(void *); 254 255 #endif /* _DEV_PCI_PCIIDEVAR_H_ */ 256
Indexes created Tue Sep 23 23:09:58 GMT 2025