pcivar.h revision 1.50.2.3
1 1.50.2.3 gehenna /* $NetBSD: pcivar.h,v 1.50.2.3 2002/06/20 16:33:49 gehenna Exp $ */ 2 1.50.2.2 gehenna 3 1.50.2.2 gehenna /* 4 1.50.2.2 gehenna * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 5 1.50.2.2 gehenna * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 1.50.2.2 gehenna * 7 1.50.2.2 gehenna * Redistribution and use in source and binary forms, with or without 8 1.50.2.2 gehenna * modification, are permitted provided that the following conditions 9 1.50.2.2 gehenna * are met: 10 1.50.2.2 gehenna * 1. Redistributions of source code must retain the above copyright 11 1.50.2.2 gehenna * notice, this list of conditions and the following disclaimer. 12 1.50.2.2 gehenna * 2. Redistributions in binary form must reproduce the above copyright 13 1.50.2.2 gehenna * notice, this list of conditions and the following disclaimer in the 14 1.50.2.2 gehenna * documentation and/or other materials provided with the distribution. 15 1.50.2.2 gehenna * 3. All advertising materials mentioning features or use of this software 16 1.50.2.2 gehenna * must display the following acknowledgement: 17 1.50.2.2 gehenna * This product includes software developed by Charles M. Hannum. 18 1.50.2.2 gehenna * 4. The name of the author may not be used to endorse or promote products 19 1.50.2.2 gehenna * derived from this software without specific prior written permission. 20 1.50.2.2 gehenna * 21 1.50.2.2 gehenna * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 1.50.2.2 gehenna * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 1.50.2.2 gehenna * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 1.50.2.2 gehenna * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 1.50.2.2 gehenna * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 1.50.2.2 gehenna * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 1.50.2.2 gehenna * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 1.50.2.2 gehenna * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 1.50.2.2 gehenna * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 1.50.2.2 gehenna * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1.50.2.2 gehenna */ 32 1.50.2.2 gehenna 33 1.50.2.2 gehenna #ifndef _DEV_PCI_PCIVAR_H_ 34 1.50.2.2 gehenna #define _DEV_PCI_PCIVAR_H_ 35 1.50.2.2 gehenna 36 1.50.2.2 gehenna /* 37 1.50.2.2 gehenna * Definitions for PCI autoconfiguration. 38 1.50.2.2 gehenna * 39 1.50.2.2 gehenna * This file describes types and functions which are used for PCI 40 1.50.2.2 gehenna * configuration. Some of this information is machine-specific, and is 41 1.50.2.2 gehenna * provided by pci_machdep.h. 42 1.50.2.2 gehenna */ 43 1.50.2.2 gehenna 44 1.50.2.2 gehenna #include <sys/device.h> 45 1.50.2.2 gehenna #include <machine/bus.h> 46 1.50.2.2 gehenna #include <dev/pci/pcireg.h> 47 1.50.2.2 gehenna 48 1.50.2.2 gehenna /* 49 1.50.2.2 gehenna * Structures and definitions needed by the machine-dependent header. 50 1.50.2.2 gehenna */ 51 1.50.2.2 gehenna typedef u_int32_t pcireg_t; /* configuration space register XXX */ 52 1.50.2.2 gehenna struct pcibus_attach_args; 53 1.50.2.2 gehenna struct pci_softc; 54 1.50.2.2 gehenna 55 1.50.2.2 gehenna #ifdef _KERNEL 56 1.50.2.2 gehenna /* 57 1.50.2.2 gehenna * Machine-dependent definitions. 58 1.50.2.2 gehenna */ 59 1.50.2.2 gehenna #include <machine/pci_machdep.h> 60 1.50.2.2 gehenna 61 1.50.2.2 gehenna /* 62 1.50.2.2 gehenna * PCI bus attach arguments. 63 1.50.2.2 gehenna */ 64 1.50.2.2 gehenna struct pcibus_attach_args { 65 1.50.2.2 gehenna char *pba_busname; /* XXX should be common */ 66 1.50.2.2 gehenna bus_space_tag_t pba_iot; /* pci i/o space tag */ 67 1.50.2.2 gehenna bus_space_tag_t pba_memt; /* pci mem space tag */ 68 1.50.2.2 gehenna bus_dma_tag_t pba_dmat; /* DMA tag */ 69 1.50.2.2 gehenna pci_chipset_tag_t pba_pc; 70 1.50.2.2 gehenna int pba_flags; /* flags; see below */ 71 1.50.2.2 gehenna 72 1.50.2.2 gehenna int pba_bus; /* PCI bus number */ 73 1.50.2.2 gehenna 74 1.50.2.2 gehenna /* 75 1.50.2.2 gehenna * Pointer to the pcitag of our parent bridge. If there is no 76 1.50.2.2 gehenna * parent bridge, then we assume we are a root bus. 77 1.50.2.2 gehenna */ 78 1.50.2.2 gehenna pcitag_t *pba_bridgetag; 79 1.50.2.2 gehenna 80 1.50.2.2 gehenna /* 81 1.50.2.2 gehenna * Interrupt swizzling information. These fields 82 1.50.2.2 gehenna * are only used by secondary busses. 83 1.50.2.2 gehenna */ 84 1.50.2.2 gehenna u_int pba_intrswiz; /* how to swizzle pins */ 85 1.50.2.2 gehenna pcitag_t pba_intrtag; /* intr. appears to come from here */ 86 1.50.2.2 gehenna }; 87 1.50.2.2 gehenna 88 1.50.2.2 gehenna /* 89 1.50.2.2 gehenna * PCI device attach arguments. 90 1.50.2.2 gehenna */ 91 1.50.2.2 gehenna struct pci_attach_args { 92 1.50.2.2 gehenna bus_space_tag_t pa_iot; /* pci i/o space tag */ 93 1.50.2.2 gehenna bus_space_tag_t pa_memt; /* pci mem space tag */ 94 1.50.2.2 gehenna bus_dma_tag_t pa_dmat; /* DMA tag */ 95 1.50.2.2 gehenna pci_chipset_tag_t pa_pc; 96 1.50.2.2 gehenna int pa_flags; /* flags; see below */ 97 1.50.2.2 gehenna 98 1.50.2.2 gehenna u_int pa_bus; 99 1.50.2.2 gehenna u_int pa_device; 100 1.50.2.2 gehenna u_int pa_function; 101 1.50.2.2 gehenna pcitag_t pa_tag; 102 1.50.2.2 gehenna pcireg_t pa_id, pa_class; 103 1.50.2.2 gehenna 104 1.50.2.2 gehenna /* 105 1.50.2.2 gehenna * Interrupt information. 106 1.50.2.2 gehenna * 107 1.50.2.2 gehenna * "Intrline" is used on systems whose firmware puts 108 1.50.2.2 gehenna * the right routing data into the line register in 109 1.50.2.2 gehenna * configuration space. The rest are used on systems 110 1.50.2.2 gehenna * that do not. 111 1.50.2.2 gehenna */ 112 1.50.2.2 gehenna u_int pa_intrswiz; /* how to swizzle pins if ppb */ 113 1.50.2.2 gehenna pcitag_t pa_intrtag; /* intr. appears to come from here */ 114 1.50.2.2 gehenna pci_intr_pin_t pa_intrpin; /* intr. appears on this pin */ 115 1.50.2.2 gehenna pci_intr_line_t pa_intrline; /* intr. routing information */ 116 1.50.2.2 gehenna pci_intr_pin_t pa_rawintrpin; /* unswizzled pin */ 117 1.50.2.2 gehenna }; 118 1.50.2.2 gehenna 119 1.50.2.2 gehenna /* 120 1.50.2.2 gehenna * Flags given in the bus and device attachment args. 121 1.50.2.2 gehenna */ 122 1.50.2.2 gehenna #define PCI_FLAGS_IO_ENABLED 0x01 /* I/O space is enabled */ 123 1.50.2.2 gehenna #define PCI_FLAGS_MEM_ENABLED 0x02 /* memory space is enabled */ 124 1.50.2.2 gehenna #define PCI_FLAGS_MRL_OKAY 0x04 /* Memory Read Line okay */ 125 1.50.2.2 gehenna #define PCI_FLAGS_MRM_OKAY 0x08 /* Memory Read Multiple okay */ 126 1.50.2.2 gehenna #define PCI_FLAGS_MWI_OKAY 0x10 /* Memory Write and Invalidate 127 1.50.2.2 gehenna okay */ 128 1.50.2.2 gehenna 129 1.50.2.2 gehenna /* 130 1.50.2.2 gehenna * PCI device 'quirks'. 131 1.50.2.2 gehenna * 132 1.50.2.2 gehenna * In general strange behaviour which can be handled by a driver (e.g. 133 1.50.2.2 gehenna * a bridge's inability to pass a type of access correctly) should be. 134 1.50.2.2 gehenna * The quirks table should only contain information which impacts 135 1.50.2.2 gehenna * the operation of the MI PCI code and which can't be pushed lower 136 1.50.2.2 gehenna * (e.g. because it's unacceptable to require a driver to be present 137 1.50.2.2 gehenna * for the information to be known). 138 1.50.2.2 gehenna */ 139 1.50.2.2 gehenna struct pci_quirkdata { 140 1.50.2.2 gehenna pci_vendor_id_t vendor; /* Vendor ID */ 141 1.50.2.2 gehenna pci_product_id_t product; /* Product ID */ 142 1.50.2.2 gehenna int quirks; /* quirks; see below */ 143 1.50.2.2 gehenna }; 144 1.50.2.2 gehenna #define PCI_QUIRK_MULTIFUNCTION 1 145 1.50.2.2 gehenna 146 1.50.2.2 gehenna #include "locators.h" 147 1.50.2.2 gehenna 148 1.50.2.2 gehenna struct pci_softc { 149 1.50.2.2 gehenna struct device sc_dev; 150 1.50.2.2 gehenna bus_space_tag_t sc_iot, sc_memt; 151 1.50.2.2 gehenna bus_dma_tag_t sc_dmat; 152 1.50.2.2 gehenna pci_chipset_tag_t sc_pc; 153 1.50.2.2 gehenna int sc_bus, sc_maxndevs; 154 1.50.2.2 gehenna pcitag_t *sc_bridgetag; 155 1.50.2.2 gehenna u_int sc_intrswiz; 156 1.50.2.2 gehenna pcitag_t sc_intrtag; 157 1.50.2.2 gehenna int sc_flags; 158 1.50.2.2 gehenna }; 159 1.50.2.2 gehenna 160 1.50.2.2 gehenna extern struct cfdriver pci_cd; 161 1.50.2.2 gehenna 162 1.50.2.2 gehenna /* 163 1.50.2.2 gehenna * Locators devices that attach to 'pcibus', as specified to config. 164 1.50.2.2 gehenna */ 165 1.50.2.2 gehenna #define pcibuscf_bus cf_loc[PCIBUSCF_BUS] 166 1.50.2.2 gehenna #define PCIBUS_UNK_BUS PCIBUSCF_BUS_DEFAULT /* wildcarded 'bus' */ 167 1.50.2.2 gehenna 168 1.50.2.2 gehenna /* 169 1.50.2.2 gehenna * Locators for PCI devices, as specified to config. 170 1.50.2.2 gehenna */ 171 1.50.2.2 gehenna #define pcicf_dev cf_loc[PCICF_DEV] 172 1.50.2.2 gehenna #define PCI_UNK_DEV PCICF_DEV_DEFAULT /* wildcarded 'dev' */ 173 1.50.2.2 gehenna 174 1.50.2.2 gehenna #define pcicf_function cf_loc[PCICF_FUNCTION] 175 1.50.2.2 gehenna #define PCI_UNK_FUNCTION PCICF_FUNCTION_DEFAULT /* wildcarded 'function' */ 176 1.50.2.2 gehenna 177 1.50.2.2 gehenna /* 178 1.50.2.2 gehenna * Configuration space access and utility functions. (Note that most, 179 1.50.2.2 gehenna * e.g. make_tag, conf_read, conf_write are declared by pci_machdep.h.) 180 1.50.2.2 gehenna */ 181 1.50.2.3 gehenna int pci_mapreg_probe __P((pci_chipset_tag_t, pcitag_t, int, pcireg_t *)); 182 1.50.2.2 gehenna pcireg_t pci_mapreg_type __P((pci_chipset_tag_t, pcitag_t, int)); 183 1.50.2.2 gehenna int pci_mapreg_info __P((pci_chipset_tag_t, pcitag_t, int, pcireg_t, 184 1.50.2.2 gehenna bus_addr_t *, bus_size_t *, int *)); 185 1.50.2.2 gehenna int pci_mapreg_map __P((struct pci_attach_args *, int, pcireg_t, int, 186 1.50.2.2 gehenna bus_space_tag_t *, bus_space_handle_t *, bus_addr_t *, 187 1.50.2.2 gehenna bus_size_t *)); 188 1.50.2.2 gehenna 189 1.50.2.2 gehenna int pci_get_capability __P((pci_chipset_tag_t, pcitag_t, int, 190 1.50.2.2 gehenna int *, pcireg_t *)); 191 1.50.2.2 gehenna 192 1.50.2.2 gehenna /* 193 1.50.2.2 gehenna * Helper functions for autoconfiguration. 194 1.50.2.2 gehenna */ 195 1.50.2.2 gehenna int pci_enumerate_bus_generic(struct pci_softc *, 196 1.50.2.2 gehenna int (*)(struct pci_attach_args *), struct pci_attach_args *); 197 1.50.2.2 gehenna int pci_probe_device(struct pci_softc *, pcitag_t tag, 198 1.50.2.2 gehenna int (*)(struct pci_attach_args *), struct pci_attach_args *); 199 1.50.2.2 gehenna void pci_devinfo __P((pcireg_t, pcireg_t, int, char *)); 200 1.50.2.2 gehenna void pci_conf_print __P((pci_chipset_tag_t, pcitag_t, 201 1.50.2.2 gehenna void (*)(pci_chipset_tag_t, pcitag_t, const pcireg_t *))); 202 1.50.2.2 gehenna const struct pci_quirkdata * 203 1.50.2.2 gehenna pci_lookup_quirkdata __P((pci_vendor_id_t, pci_product_id_t)); 204 1.50.2.2 gehenna 205 1.50.2.2 gehenna /* 206 1.50.2.2 gehenna * Helper functions for user access to the PCI bus. 207 1.50.2.2 gehenna */ 208 1.50.2.2 gehenna struct proc; 209 1.50.2.2 gehenna int pci_devioctl __P((pci_chipset_tag_t, pcitag_t, u_long, caddr_t, 210 1.50.2.2 gehenna int flag, struct proc *)); 211 1.50.2.2 gehenna 212 1.50.2.2 gehenna /* 213 1.50.2.2 gehenna * Misc. 214 1.50.2.2 gehenna */ 215 1.50.2.2 gehenna char *pci_findvendor __P((pcireg_t)); 216 1.50.2.2 gehenna int pci_find_device(struct pci_attach_args *pa, 217 1.50.2.2 gehenna int (*match)(struct pci_attach_args *)); 218 1.50.2.2 gehenna 219 1.50.2.2 gehenna #endif /* _KERNEL */ 220 1.50.2.2 gehenna 221 1.50.2.2 gehenna #endif /* _DEV_PCI_PCIVAR_H_ */ 222
Indexes created Thu Oct 30 03:10:01 GMT 2025