pcivar.h revision 1.89
1 /* $NetBSD: pcivar.h,v 1.89 2010/05/27 05:53:35 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_PCI_PCIVAR_H_ 34 #define _DEV_PCI_PCIVAR_H_ 35 36 /* 37 * Definitions for PCI autoconfiguration. 38 * 39 * This file describes types and functions which are used for PCI 40 * configuration. Some of this information is machine-specific, and is 41 * provided by pci_machdep.h. 42 */ 43 44 #include <sys/device.h> 45 #include <sys/pmf.h> 46 #include <sys/bus.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_verbose.h> 49 50 /* 51 * Structures and definitions needed by the machine-dependent header. 52 */ 53 struct pcibus_attach_args; 54 struct pci_softc; 55 56 #ifdef _KERNEL 57 /* 58 * Machine-dependent definitions. 59 */ 60 #include <machine/pci_machdep.h> 61 62 enum pci_override_idx { 63 PCI_OVERRIDE_CONF_READ = __BIT(0) 64 , PCI_OVERRIDE_CONF_WRITE = __BIT(1) 65 , PCI_OVERRIDE_INTR_MAP = __BIT(2) 66 , PCI_OVERRIDE_INTR_STRING = __BIT(3) 67 , PCI_OVERRIDE_INTR_EVCNT = __BIT(4) 68 , PCI_OVERRIDE_INTR_ESTABLISH = __BIT(5) 69 , PCI_OVERRIDE_INTR_DISESTABLISH = __BIT(6) 70 , PCI_OVERRIDE_MAKE_TAG = __BIT(7) 71 , PCI_OVERRIDE_DECOMPOSE_TAG = __BIT(8) 72 }; 73 74 /* Only add new fields to the end of this structure! */ 75 struct pci_overrides { 76 pcireg_t (*ov_conf_read)(void *, pci_chipset_tag_t, pcitag_t, int); 77 void (*ov_conf_write)(void *, pci_chipset_tag_t, pcitag_t, int, 78 pcireg_t); 79 int (*ov_intr_map)(void *, struct pci_attach_args *, 80 pci_intr_handle_t *); 81 const char *(*ov_intr_string)(void *, pci_chipset_tag_t, 82 pci_intr_handle_t); 83 const struct evcnt *(*ov_intr_evcnt)(void *, pci_chipset_tag_t, 84 pci_intr_handle_t); 85 void *(*ov_intr_establish)(void *, pci_chipset_tag_t, pci_intr_handle_t, 86 int, int (*)(void *), void *); 87 void (*ov_intr_disestablish)(void *, pci_chipset_tag_t, void *); 88 pcitag_t (*ov_make_tag)(void *, pci_chipset_tag_t, int, int, int); 89 void (*ov_decompose_tag)(void *, pci_chipset_tag_t, pcitag_t, 90 int *, int *, int *); 91 }; 92 93 /* 94 * PCI bus attach arguments. 95 */ 96 struct pcibus_attach_args { 97 char *_pba_busname; /* XXX placeholder */ 98 bus_space_tag_t pba_iot; /* pci i/o space tag */ 99 bus_space_tag_t pba_memt; /* pci mem space tag */ 100 bus_dma_tag_t pba_dmat; /* DMA tag */ 101 bus_dma_tag_t pba_dmat64; /* DMA tag */ 102 pci_chipset_tag_t pba_pc; 103 int pba_flags; /* flags; see below */ 104 105 int pba_bus; /* PCI bus number */ 106 107 /* 108 * Pointer to the pcitag of our parent bridge. If there is no 109 * parent bridge, then we assume we are a root bus. 110 */ 111 pcitag_t *pba_bridgetag; 112 113 /* 114 * Interrupt swizzling information. These fields 115 * are only used by secondary busses. 116 */ 117 u_int pba_intrswiz; /* how to swizzle pins */ 118 pcitag_t pba_intrtag; /* intr. appears to come from here */ 119 }; 120 121 /* 122 * PCI device attach arguments. 123 */ 124 struct pci_attach_args { 125 bus_space_tag_t pa_iot; /* pci i/o space tag */ 126 bus_space_tag_t pa_memt; /* pci mem space tag */ 127 bus_dma_tag_t pa_dmat; /* DMA tag */ 128 bus_dma_tag_t pa_dmat64; /* DMA tag */ 129 pci_chipset_tag_t pa_pc; 130 int pa_flags; /* flags; see below */ 131 132 u_int pa_bus; 133 u_int pa_device; 134 u_int pa_function; 135 pcitag_t pa_tag; 136 pcireg_t pa_id, pa_class; 137 138 /* 139 * Interrupt information. 140 * 141 * "Intrline" is used on systems whose firmware puts 142 * the right routing data into the line register in 143 * configuration space. The rest are used on systems 144 * that do not. 145 */ 146 u_int pa_intrswiz; /* how to swizzle pins if ppb */ 147 pcitag_t pa_intrtag; /* intr. appears to come from here */ 148 pci_intr_pin_t pa_intrpin; /* intr. appears on this pin */ 149 pci_intr_line_t pa_intrline; /* intr. routing information */ 150 pci_intr_pin_t pa_rawintrpin; /* unswizzled pin */ 151 }; 152 153 /* 154 * Flags given in the bus and device attachment args. 155 */ 156 #define PCI_FLAGS_IO_ENABLED 0x01 /* I/O space is enabled */ 157 #define PCI_FLAGS_MEM_ENABLED 0x02 /* memory space is enabled */ 158 #define PCI_FLAGS_MRL_OKAY 0x04 /* Memory Read Line okay */ 159 #define PCI_FLAGS_MRM_OKAY 0x08 /* Memory Read Multiple okay */ 160 #define PCI_FLAGS_MWI_OKAY 0x10 /* Memory Write and Invalidate 161 okay */ 162 #define PCI_FLAGS_MSI_OKAY 0x20 /* Message Signaled Interrupts 163 okay */ 164 #define PCI_FLAGS_MSIX_OKAY 0x40 /* Message Signaled Interrupts 165 (Extended) okay */ 166 167 /* 168 * PCI device 'quirks'. 169 * 170 * In general strange behaviour which can be handled by a driver (e.g. 171 * a bridge's inability to pass a type of access correctly) should be. 172 * The quirks table should only contain information which impacts 173 * the operation of the MI PCI code and which can't be pushed lower 174 * (e.g. because it's unacceptable to require a driver to be present 175 * for the information to be known). 176 */ 177 struct pci_quirkdata { 178 pci_vendor_id_t vendor; /* Vendor ID */ 179 pci_product_id_t product; /* Product ID */ 180 int quirks; /* quirks; see below */ 181 }; 182 #define PCI_QUIRK_MULTIFUNCTION 1 183 #define PCI_QUIRK_MONOFUNCTION 2 184 #define PCI_QUIRK_SKIP_FUNC(n) (4 << n) 185 #define PCI_QUIRK_SKIP_FUNC0 PCI_QUIRK_SKIP_FUNC(0) 186 #define PCI_QUIRK_SKIP_FUNC1 PCI_QUIRK_SKIP_FUNC(1) 187 #define PCI_QUIRK_SKIP_FUNC2 PCI_QUIRK_SKIP_FUNC(2) 188 #define PCI_QUIRK_SKIP_FUNC3 PCI_QUIRK_SKIP_FUNC(3) 189 #define PCI_QUIRK_SKIP_FUNC4 PCI_QUIRK_SKIP_FUNC(4) 190 #define PCI_QUIRK_SKIP_FUNC5 PCI_QUIRK_SKIP_FUNC(5) 191 #define PCI_QUIRK_SKIP_FUNC6 PCI_QUIRK_SKIP_FUNC(6) 192 #define PCI_QUIRK_SKIP_FUNC7 PCI_QUIRK_SKIP_FUNC(7) 193 194 struct pci_conf_state { 195 pcireg_t reg[16]; 196 }; 197 198 struct pci_child { 199 device_t c_dev; 200 bool c_psok; 201 pcireg_t c_powerstate; 202 struct pci_conf_state c_conf; 203 }; 204 205 struct pci_softc { 206 device_t sc_dev; 207 bus_space_tag_t sc_iot, sc_memt; 208 bus_dma_tag_t sc_dmat; 209 bus_dma_tag_t sc_dmat64; 210 pci_chipset_tag_t sc_pc; 211 int sc_bus, sc_maxndevs; 212 pcitag_t *sc_bridgetag; 213 u_int sc_intrswiz; 214 pcitag_t sc_intrtag; 215 int sc_flags; 216 /* accounting of child devices */ 217 struct pci_child sc_devices[32*8]; 218 #define PCI_SC_DEVICESC(d, f) sc_devices[(d) * 8 + (f)] 219 }; 220 221 extern struct cfdriver pci_cd; 222 223 int pcibusprint(void *, const char *); 224 225 /* 226 * Configuration space access and utility functions. (Note that most, 227 * e.g. make_tag, conf_read, conf_write are declared by pci_machdep.h.) 228 */ 229 int pci_mapreg_probe(pci_chipset_tag_t, pcitag_t, int, pcireg_t *); 230 pcireg_t pci_mapreg_type(pci_chipset_tag_t, pcitag_t, int); 231 int pci_mapreg_info(pci_chipset_tag_t, pcitag_t, int, pcireg_t, 232 bus_addr_t *, bus_size_t *, int *); 233 int pci_mapreg_map(struct pci_attach_args *, int, pcireg_t, int, 234 bus_space_tag_t *, bus_space_handle_t *, bus_addr_t *, 235 bus_size_t *); 236 int pci_mapreg_submap(struct pci_attach_args *, int, pcireg_t, int, 237 bus_size_t, bus_size_t, bus_space_tag_t *, bus_space_handle_t *, 238 bus_addr_t *, bus_size_t *); 239 240 int pci_find_rom(struct pci_attach_args *, bus_space_tag_t, bus_space_handle_t, 241 int, bus_space_handle_t *, bus_size_t *); 242 243 int pci_get_capability(pci_chipset_tag_t, pcitag_t, int, int *, pcireg_t *); 244 245 /* 246 * Helper functions for autoconfiguration. 247 */ 248 int pci_probe_device(struct pci_softc *, pcitag_t tag, 249 int (*)(struct pci_attach_args *), struct pci_attach_args *); 250 void pci_devinfo(pcireg_t, pcireg_t, int, char *, size_t); 251 void pci_conf_print(pci_chipset_tag_t, pcitag_t, 252 void (*)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)); 253 const struct pci_quirkdata * 254 pci_lookup_quirkdata(pci_vendor_id_t, pci_product_id_t); 255 256 /* 257 * Helper functions for user access to the PCI bus. 258 */ 259 struct proc; 260 int pci_devioctl(pci_chipset_tag_t, pcitag_t, u_long, void *, 261 int flag, struct lwp *); 262 263 /* 264 * Power Management (PCI 2.2) 265 */ 266 267 #define PCI_PWR_D0 0 268 #define PCI_PWR_D1 1 269 #define PCI_PWR_D2 2 270 #define PCI_PWR_D3 3 271 int pci_powerstate(pci_chipset_tag_t, pcitag_t, const int *, int *); 272 273 /* 274 * Vital Product Data (PCI 2.2) 275 */ 276 int pci_vpd_read(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *); 277 int pci_vpd_write(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *); 278 279 /* 280 * Misc. 281 */ 282 int pci_find_device(struct pci_attach_args *pa, 283 int (*match)(struct pci_attach_args *)); 284 int pci_dma64_available(struct pci_attach_args *); 285 void pci_conf_capture(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *); 286 void pci_conf_restore(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *); 287 int pci_get_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t *); 288 int pci_set_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t); 289 int pci_activate(pci_chipset_tag_t, pcitag_t, device_t, 290 int (*)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)); 291 int pci_activate_null(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t); 292 int pci_chipset_tag_create(pci_chipset_tag_t, uint64_t, 293 const struct pci_overrides *, 294 void *, pci_chipset_tag_t *); 295 void pci_chipset_tag_destroy(pci_chipset_tag_t); 296 297 /* 298 * Device abstraction for inheritance by elanpci(4), for example. 299 */ 300 int pcimatch(device_t, cfdata_t, void *); 301 void pciattach(device_t, device_t, void *); 302 int pcidetach(device_t, int); 303 void pcidevdetached(device_t, device_t); 304 int pcirescan(device_t, const char *, const int *); 305 306 /* 307 * Interrupts. 308 */ 309 #define PCI_INTR_MPSAFE 1 310 311 int pci_intr_setattr(pci_chipset_tag_t, pci_intr_handle_t *, int, uint64_t); 312 313 #endif /* _KERNEL */ 314 315 #endif /* _DEV_PCI_PCIVAR_H_ */ 316
Indexes created Tue Sep 30 11:09:46 GMT 2025