pcivar.h revision 1.93
1 /* $NetBSD: pcivar.h,v 1.93 2011/05/17 17:34:54 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_PCI_PCIVAR_H_ 34 #define _DEV_PCI_PCIVAR_H_ 35 36 /* 37 * Definitions for PCI autoconfiguration. 38 * 39 * This file describes types and functions which are used for PCI 40 * configuration. Some of this information is machine-specific, and is 41 * provided by pci_machdep.h. 42 */ 43 44 #include <sys/device.h> 45 #include <sys/pmf.h> 46 #include <sys/bus.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_verbose.h> 49 50 /* 51 * Structures and definitions needed by the machine-dependent header. 52 */ 53 struct pcibus_attach_args; 54 struct pci_attach_args; 55 struct pci_softc; 56 57 #ifdef _KERNEL 58 /* 59 * Machine-dependent definitions. 60 */ 61 #include <machine/pci_machdep.h> 62 63 enum pci_override_idx { 64 PCI_OVERRIDE_CONF_READ = __BIT(0) 65 , PCI_OVERRIDE_CONF_WRITE = __BIT(1) 66 , PCI_OVERRIDE_INTR_MAP = __BIT(2) 67 , PCI_OVERRIDE_INTR_STRING = __BIT(3) 68 , PCI_OVERRIDE_INTR_EVCNT = __BIT(4) 69 , PCI_OVERRIDE_INTR_ESTABLISH = __BIT(5) 70 , PCI_OVERRIDE_INTR_DISESTABLISH = __BIT(6) 71 , PCI_OVERRIDE_MAKE_TAG = __BIT(7) 72 , PCI_OVERRIDE_DECOMPOSE_TAG = __BIT(8) 73 }; 74 75 /* Only add new fields to the end of this structure! */ 76 struct pci_overrides { 77 pcireg_t (*ov_conf_read)(void *, pci_chipset_tag_t, pcitag_t, int); 78 void (*ov_conf_write)(void *, pci_chipset_tag_t, pcitag_t, int, 79 pcireg_t); 80 int (*ov_intr_map)(void *, const struct pci_attach_args *, 81 pci_intr_handle_t *); 82 const char *(*ov_intr_string)(void *, pci_chipset_tag_t, 83 pci_intr_handle_t); 84 const struct evcnt *(*ov_intr_evcnt)(void *, pci_chipset_tag_t, 85 pci_intr_handle_t); 86 void *(*ov_intr_establish)(void *, pci_chipset_tag_t, pci_intr_handle_t, 87 int, int (*)(void *), void *); 88 void (*ov_intr_disestablish)(void *, pci_chipset_tag_t, void *); 89 pcitag_t (*ov_make_tag)(void *, pci_chipset_tag_t, int, int, int); 90 void (*ov_decompose_tag)(void *, pci_chipset_tag_t, pcitag_t, 91 int *, int *, int *); 92 }; 93 94 /* 95 * PCI bus attach arguments. 96 */ 97 struct pcibus_attach_args { 98 char *_pba_busname; /* XXX placeholder */ 99 bus_space_tag_t pba_iot; /* pci i/o space tag */ 100 bus_space_tag_t pba_memt; /* pci mem space tag */ 101 bus_dma_tag_t pba_dmat; /* DMA tag */ 102 bus_dma_tag_t pba_dmat64; /* DMA tag */ 103 pci_chipset_tag_t pba_pc; 104 int pba_flags; /* flags; see below */ 105 106 int pba_bus; /* PCI bus number */ 107 108 /* 109 * Pointer to the pcitag of our parent bridge. If there is no 110 * parent bridge, then we assume we are a root bus. 111 */ 112 pcitag_t *pba_bridgetag; 113 114 /* 115 * Interrupt swizzling information. These fields 116 * are only used by secondary busses. 117 */ 118 u_int pba_intrswiz; /* how to swizzle pins */ 119 pcitag_t pba_intrtag; /* intr. appears to come from here */ 120 }; 121 122 /* 123 * PCI device attach arguments. 124 */ 125 struct pci_attach_args { 126 bus_space_tag_t pa_iot; /* pci i/o space tag */ 127 bus_space_tag_t pa_memt; /* pci mem space tag */ 128 bus_dma_tag_t pa_dmat; /* DMA tag */ 129 bus_dma_tag_t pa_dmat64; /* DMA tag */ 130 pci_chipset_tag_t pa_pc; 131 int pa_flags; /* flags; see below */ 132 133 u_int pa_bus; 134 u_int pa_device; 135 u_int pa_function; 136 pcitag_t pa_tag; 137 pcireg_t pa_id, pa_class; 138 139 /* 140 * Interrupt information. 141 * 142 * "Intrline" is used on systems whose firmware puts 143 * the right routing data into the line register in 144 * configuration space. The rest are used on systems 145 * that do not. 146 */ 147 u_int pa_intrswiz; /* how to swizzle pins if ppb */ 148 pcitag_t pa_intrtag; /* intr. appears to come from here */ 149 pci_intr_pin_t pa_intrpin; /* intr. appears on this pin */ 150 pci_intr_line_t pa_intrline; /* intr. routing information */ 151 pci_intr_pin_t pa_rawintrpin; /* unswizzled pin */ 152 }; 153 154 /* 155 * Flags given in the bus and device attachment args. 156 */ 157 #define PCI_FLAGS_IO_OKAY 0x01 /* I/O space is okay */ 158 #define PCI_FLAGS_MEM_OKAY 0x02 /* memory space is okay */ 159 #define PCI_FLAGS_MRL_OKAY 0x04 /* Memory Read Line okay */ 160 #define PCI_FLAGS_MRM_OKAY 0x08 /* Memory Read Multiple okay */ 161 #define PCI_FLAGS_MWI_OKAY 0x10 /* Memory Write and Invalidate 162 okay */ 163 #define PCI_FLAGS_MSI_OKAY 0x20 /* Message Signaled Interrupts 164 okay */ 165 #define PCI_FLAGS_MSIX_OKAY 0x40 /* Message Signaled Interrupts 166 (Extended) okay */ 167 168 /* 169 * PCI device 'quirks'. 170 * 171 * In general strange behaviour which can be handled by a driver (e.g. 172 * a bridge's inability to pass a type of access correctly) should be. 173 * The quirks table should only contain information which impacts 174 * the operation of the MI PCI code and which can't be pushed lower 175 * (e.g. because it's unacceptable to require a driver to be present 176 * for the information to be known). 177 */ 178 struct pci_quirkdata { 179 pci_vendor_id_t vendor; /* Vendor ID */ 180 pci_product_id_t product; /* Product ID */ 181 int quirks; /* quirks; see below */ 182 }; 183 #define PCI_QUIRK_MULTIFUNCTION 1 184 #define PCI_QUIRK_MONOFUNCTION 2 185 #define PCI_QUIRK_SKIP_FUNC(n) (4 << n) 186 #define PCI_QUIRK_SKIP_FUNC0 PCI_QUIRK_SKIP_FUNC(0) 187 #define PCI_QUIRK_SKIP_FUNC1 PCI_QUIRK_SKIP_FUNC(1) 188 #define PCI_QUIRK_SKIP_FUNC2 PCI_QUIRK_SKIP_FUNC(2) 189 #define PCI_QUIRK_SKIP_FUNC3 PCI_QUIRK_SKIP_FUNC(3) 190 #define PCI_QUIRK_SKIP_FUNC4 PCI_QUIRK_SKIP_FUNC(4) 191 #define PCI_QUIRK_SKIP_FUNC5 PCI_QUIRK_SKIP_FUNC(5) 192 #define PCI_QUIRK_SKIP_FUNC6 PCI_QUIRK_SKIP_FUNC(6) 193 #define PCI_QUIRK_SKIP_FUNC7 PCI_QUIRK_SKIP_FUNC(7) 194 195 struct pci_conf_state { 196 pcireg_t reg[16]; 197 }; 198 199 struct pci_range { 200 bus_addr_t r_offset; 201 bus_size_t r_size; 202 int r_flags; 203 }; 204 205 struct pci_child { 206 device_t c_dev; 207 bool c_psok; 208 pcireg_t c_powerstate; 209 struct pci_conf_state c_conf; 210 struct pci_range c_range[8]; 211 }; 212 213 struct pci_softc { 214 device_t sc_dev; 215 bus_space_tag_t sc_iot, sc_memt; 216 bus_dma_tag_t sc_dmat; 217 bus_dma_tag_t sc_dmat64; 218 pci_chipset_tag_t sc_pc; 219 int sc_bus, sc_maxndevs; 220 pcitag_t *sc_bridgetag; 221 u_int sc_intrswiz; 222 pcitag_t sc_intrtag; 223 int sc_flags; 224 /* accounting of child devices */ 225 struct pci_child sc_devices[32*8]; 226 #define PCI_SC_DEVICESC(d, f) sc_devices[(d) * 8 + (f)] 227 }; 228 229 extern struct cfdriver pci_cd; 230 231 int pcibusprint(void *, const char *); 232 233 /* 234 * Configuration space access and utility functions. (Note that most, 235 * e.g. make_tag, conf_read, conf_write are declared by pci_machdep.h.) 236 */ 237 int pci_mapreg_probe(pci_chipset_tag_t, pcitag_t, int, pcireg_t *); 238 pcireg_t pci_mapreg_type(pci_chipset_tag_t, pcitag_t, int); 239 int pci_mapreg_info(pci_chipset_tag_t, pcitag_t, int, pcireg_t, 240 bus_addr_t *, bus_size_t *, int *); 241 int pci_mapreg_map(const struct pci_attach_args *, int, pcireg_t, int, 242 bus_space_tag_t *, bus_space_handle_t *, bus_addr_t *, 243 bus_size_t *); 244 245 int pci_find_rom(const struct pci_attach_args *, bus_space_tag_t, 246 bus_space_handle_t, 247 int, bus_space_handle_t *, bus_size_t *); 248 249 int pci_get_capability(pci_chipset_tag_t, pcitag_t, int, int *, pcireg_t *); 250 251 /* 252 * Helper functions for autoconfiguration. 253 */ 254 int pci_probe_device(struct pci_softc *, pcitag_t tag, 255 int (*)(const struct pci_attach_args *), 256 struct pci_attach_args *); 257 void pci_devinfo(pcireg_t, pcireg_t, int, char *, size_t); 258 void pci_conf_print(pci_chipset_tag_t, pcitag_t, 259 void (*)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)); 260 const struct pci_quirkdata * 261 pci_lookup_quirkdata(pci_vendor_id_t, pci_product_id_t); 262 263 /* 264 * Helper functions for user access to the PCI bus. 265 */ 266 struct proc; 267 int pci_devioctl(pci_chipset_tag_t, pcitag_t, u_long, void *, 268 int flag, struct lwp *); 269 270 /* 271 * Power Management (PCI 2.2) 272 */ 273 274 #define PCI_PWR_D0 0 275 #define PCI_PWR_D1 1 276 #define PCI_PWR_D2 2 277 #define PCI_PWR_D3 3 278 int pci_powerstate(pci_chipset_tag_t, pcitag_t, const int *, int *); 279 280 /* 281 * Vital Product Data (PCI 2.2) 282 */ 283 int pci_vpd_read(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *); 284 int pci_vpd_write(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *); 285 286 /* 287 * Misc. 288 */ 289 int pci_find_device(struct pci_attach_args *pa, 290 int (*match)(const struct pci_attach_args *)); 291 int pci_dma64_available(const struct pci_attach_args *); 292 void pci_conf_capture(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *); 293 void pci_conf_restore(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *); 294 int pci_get_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t *); 295 int pci_set_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t); 296 int pci_activate(pci_chipset_tag_t, pcitag_t, device_t, 297 int (*)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)); 298 int pci_activate_null(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t); 299 int pci_chipset_tag_create(pci_chipset_tag_t, uint64_t, 300 const struct pci_overrides *, 301 void *, pci_chipset_tag_t *); 302 void pci_chipset_tag_destroy(pci_chipset_tag_t); 303 304 /* 305 * Device abstraction for inheritance by elanpci(4), for example. 306 */ 307 int pcimatch(device_t, cfdata_t, void *); 308 void pciattach(device_t, device_t, void *); 309 int pcidetach(device_t, int); 310 void pcidevdetached(device_t, device_t); 311 int pcirescan(device_t, const char *, const int *); 312 313 /* 314 * Interrupts. 315 */ 316 #define PCI_INTR_MPSAFE 1 317 318 int pci_intr_setattr(pci_chipset_tag_t, pci_intr_handle_t *, int, uint64_t); 319 320 #endif /* _KERNEL */ 321 322 #endif /* _DEV_PCI_PCIVAR_H_ */ 323
Indexes created Fri Sep 26 20:09:58 GMT 2025