pcivar.h revision 1.94
1 /* $NetBSD: pcivar.h,v 1.94 2011/06/22 18:03:30 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_PCI_PCIVAR_H_ 34 #define _DEV_PCI_PCIVAR_H_ 35 36 /* 37 * Definitions for PCI autoconfiguration. 38 * 39 * This file describes types and functions which are used for PCI 40 * configuration. Some of this information is machine-specific, and is 41 * provided by pci_machdep.h. 42 */ 43 44 #include <sys/device.h> 45 #include <sys/pmf.h> 46 #include <sys/bus.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_verbose.h> 49 50 /* 51 * Structures and definitions needed by the machine-dependent header. 52 */ 53 struct pcibus_attach_args; 54 struct pci_attach_args; 55 struct pci_softc; 56 57 #ifdef _KERNEL 58 /* 59 * Machine-dependent definitions. 60 */ 61 #include <machine/pci_machdep.h> 62 63 enum pci_override_idx { 64 PCI_OVERRIDE_CONF_READ = __BIT(0) 65 , PCI_OVERRIDE_CONF_WRITE = __BIT(1) 66 , PCI_OVERRIDE_INTR_MAP = __BIT(2) 67 , PCI_OVERRIDE_INTR_STRING = __BIT(3) 68 , PCI_OVERRIDE_INTR_EVCNT = __BIT(4) 69 , PCI_OVERRIDE_INTR_ESTABLISH = __BIT(5) 70 , PCI_OVERRIDE_INTR_DISESTABLISH = __BIT(6) 71 , PCI_OVERRIDE_MAKE_TAG = __BIT(7) 72 , PCI_OVERRIDE_DECOMPOSE_TAG = __BIT(8) 73 }; 74 75 /* Only add new fields to the end of this structure! */ 76 struct pci_overrides { 77 pcireg_t (*ov_conf_read)(void *, pci_chipset_tag_t, pcitag_t, int); 78 void (*ov_conf_write)(void *, pci_chipset_tag_t, pcitag_t, int, 79 pcireg_t); 80 int (*ov_intr_map)(void *, const struct pci_attach_args *, 81 pci_intr_handle_t *); 82 const char *(*ov_intr_string)(void *, pci_chipset_tag_t, 83 pci_intr_handle_t); 84 const struct evcnt *(*ov_intr_evcnt)(void *, pci_chipset_tag_t, 85 pci_intr_handle_t); 86 void *(*ov_intr_establish)(void *, pci_chipset_tag_t, pci_intr_handle_t, 87 int, int (*)(void *), void *); 88 void (*ov_intr_disestablish)(void *, pci_chipset_tag_t, void *); 89 pcitag_t (*ov_make_tag)(void *, pci_chipset_tag_t, int, int, int); 90 void (*ov_decompose_tag)(void *, pci_chipset_tag_t, pcitag_t, 91 int *, int *, int *); 92 }; 93 94 /* 95 * PCI bus attach arguments. 96 */ 97 struct pcibus_attach_args { 98 char *_pba_busname; /* XXX placeholder */ 99 bus_space_tag_t pba_iot; /* pci i/o space tag */ 100 bus_space_tag_t pba_memt; /* pci mem space tag */ 101 bus_dma_tag_t pba_dmat; /* DMA tag */ 102 bus_dma_tag_t pba_dmat64; /* DMA tag */ 103 pci_chipset_tag_t pba_pc; 104 int pba_flags; /* flags; see below */ 105 106 int pba_bus; /* PCI bus number */ 107 108 /* 109 * Pointer to the pcitag of our parent bridge. If there is no 110 * parent bridge, then we assume we are a root bus. 111 */ 112 pcitag_t *pba_bridgetag; 113 114 /* 115 * Interrupt swizzling information. These fields 116 * are only used by secondary busses. 117 */ 118 u_int pba_intrswiz; /* how to swizzle pins */ 119 pcitag_t pba_intrtag; /* intr. appears to come from here */ 120 }; 121 122 /* 123 * This is used by <machine/pci_machdep.h> to access the pba_pc member. It 124 * can't use it directly since pcibus_attach_args has yet to be defined. 125 */ 126 static inline pci_chipset_tag_t 127 pcibus_attach_args_pc(struct pcibus_attach_args *pba) 128 { 129 return pba->pba_pc; 130 } 131 132 /* 133 * PCI device attach arguments. 134 */ 135 struct pci_attach_args { 136 bus_space_tag_t pa_iot; /* pci i/o space tag */ 137 bus_space_tag_t pa_memt; /* pci mem space tag */ 138 bus_dma_tag_t pa_dmat; /* DMA tag */ 139 bus_dma_tag_t pa_dmat64; /* DMA tag */ 140 pci_chipset_tag_t pa_pc; 141 int pa_flags; /* flags; see below */ 142 143 u_int pa_bus; 144 u_int pa_device; 145 u_int pa_function; 146 pcitag_t pa_tag; 147 pcireg_t pa_id, pa_class; 148 149 /* 150 * Interrupt information. 151 * 152 * "Intrline" is used on systems whose firmware puts 153 * the right routing data into the line register in 154 * configuration space. The rest are used on systems 155 * that do not. 156 */ 157 u_int pa_intrswiz; /* how to swizzle pins if ppb */ 158 pcitag_t pa_intrtag; /* intr. appears to come from here */ 159 pci_intr_pin_t pa_intrpin; /* intr. appears on this pin */ 160 pci_intr_line_t pa_intrline; /* intr. routing information */ 161 pci_intr_pin_t pa_rawintrpin; /* unswizzled pin */ 162 }; 163 164 /* 165 * This is used by <machine/pci_machdep.h> to access the pa_pc member. It 166 * can't use it directly since pci_attach_args has yet to be defined. 167 */ 168 static inline pci_chipset_tag_t 169 pci_attach_args_pc(const struct pci_attach_args *pa) 170 { 171 return pa->pa_pc; 172 } 173 174 /* 175 * Flags given in the bus and device attachment args. 176 */ 177 #define PCI_FLAGS_IO_OKAY 0x01 /* I/O space is okay */ 178 #define PCI_FLAGS_MEM_OKAY 0x02 /* memory space is okay */ 179 #define PCI_FLAGS_MRL_OKAY 0x04 /* Memory Read Line okay */ 180 #define PCI_FLAGS_MRM_OKAY 0x08 /* Memory Read Multiple okay */ 181 #define PCI_FLAGS_MWI_OKAY 0x10 /* Memory Write and Invalidate 182 okay */ 183 #define PCI_FLAGS_MSI_OKAY 0x20 /* Message Signaled Interrupts 184 okay */ 185 #define PCI_FLAGS_MSIX_OKAY 0x40 /* Message Signaled Interrupts 186 (Extended) okay */ 187 188 /* 189 * PCI device 'quirks'. 190 * 191 * In general strange behaviour which can be handled by a driver (e.g. 192 * a bridge's inability to pass a type of access correctly) should be. 193 * The quirks table should only contain information which impacts 194 * the operation of the MI PCI code and which can't be pushed lower 195 * (e.g. because it's unacceptable to require a driver to be present 196 * for the information to be known). 197 */ 198 struct pci_quirkdata { 199 pci_vendor_id_t vendor; /* Vendor ID */ 200 pci_product_id_t product; /* Product ID */ 201 int quirks; /* quirks; see below */ 202 }; 203 #define PCI_QUIRK_MULTIFUNCTION 1 204 #define PCI_QUIRK_MONOFUNCTION 2 205 #define PCI_QUIRK_SKIP_FUNC(n) (4 << n) 206 #define PCI_QUIRK_SKIP_FUNC0 PCI_QUIRK_SKIP_FUNC(0) 207 #define PCI_QUIRK_SKIP_FUNC1 PCI_QUIRK_SKIP_FUNC(1) 208 #define PCI_QUIRK_SKIP_FUNC2 PCI_QUIRK_SKIP_FUNC(2) 209 #define PCI_QUIRK_SKIP_FUNC3 PCI_QUIRK_SKIP_FUNC(3) 210 #define PCI_QUIRK_SKIP_FUNC4 PCI_QUIRK_SKIP_FUNC(4) 211 #define PCI_QUIRK_SKIP_FUNC5 PCI_QUIRK_SKIP_FUNC(5) 212 #define PCI_QUIRK_SKIP_FUNC6 PCI_QUIRK_SKIP_FUNC(6) 213 #define PCI_QUIRK_SKIP_FUNC7 PCI_QUIRK_SKIP_FUNC(7) 214 215 struct pci_conf_state { 216 pcireg_t reg[16]; 217 }; 218 219 struct pci_range { 220 bus_addr_t r_offset; 221 bus_size_t r_size; 222 int r_flags; 223 }; 224 225 struct pci_child { 226 device_t c_dev; 227 bool c_psok; 228 pcireg_t c_powerstate; 229 struct pci_conf_state c_conf; 230 struct pci_range c_range[8]; 231 }; 232 233 struct pci_softc { 234 device_t sc_dev; 235 bus_space_tag_t sc_iot, sc_memt; 236 bus_dma_tag_t sc_dmat; 237 bus_dma_tag_t sc_dmat64; 238 pci_chipset_tag_t sc_pc; 239 int sc_bus, sc_maxndevs; 240 pcitag_t *sc_bridgetag; 241 u_int sc_intrswiz; 242 pcitag_t sc_intrtag; 243 int sc_flags; 244 /* accounting of child devices */ 245 struct pci_child sc_devices[32*8]; 246 #define PCI_SC_DEVICESC(d, f) sc_devices[(d) * 8 + (f)] 247 }; 248 249 extern struct cfdriver pci_cd; 250 251 int pcibusprint(void *, const char *); 252 253 /* 254 * Configuration space access and utility functions. (Note that most, 255 * e.g. make_tag, conf_read, conf_write are declared by pci_machdep.h.) 256 */ 257 int pci_mapreg_probe(pci_chipset_tag_t, pcitag_t, int, pcireg_t *); 258 pcireg_t pci_mapreg_type(pci_chipset_tag_t, pcitag_t, int); 259 int pci_mapreg_info(pci_chipset_tag_t, pcitag_t, int, pcireg_t, 260 bus_addr_t *, bus_size_t *, int *); 261 int pci_mapreg_map(const struct pci_attach_args *, int, pcireg_t, int, 262 bus_space_tag_t *, bus_space_handle_t *, bus_addr_t *, 263 bus_size_t *); 264 265 int pci_find_rom(const struct pci_attach_args *, bus_space_tag_t, 266 bus_space_handle_t, 267 int, bus_space_handle_t *, bus_size_t *); 268 269 int pci_get_capability(pci_chipset_tag_t, pcitag_t, int, int *, pcireg_t *); 270 271 /* 272 * Helper functions for autoconfiguration. 273 */ 274 int pci_probe_device(struct pci_softc *, pcitag_t tag, 275 int (*)(const struct pci_attach_args *), 276 struct pci_attach_args *); 277 void pci_devinfo(pcireg_t, pcireg_t, int, char *, size_t); 278 void pci_conf_print(pci_chipset_tag_t, pcitag_t, 279 void (*)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)); 280 const struct pci_quirkdata * 281 pci_lookup_quirkdata(pci_vendor_id_t, pci_product_id_t); 282 283 /* 284 * Helper functions for user access to the PCI bus. 285 */ 286 struct proc; 287 int pci_devioctl(pci_chipset_tag_t, pcitag_t, u_long, void *, 288 int flag, struct lwp *); 289 290 /* 291 * Power Management (PCI 2.2) 292 */ 293 294 #define PCI_PWR_D0 0 295 #define PCI_PWR_D1 1 296 #define PCI_PWR_D2 2 297 #define PCI_PWR_D3 3 298 int pci_powerstate(pci_chipset_tag_t, pcitag_t, const int *, int *); 299 300 /* 301 * Vital Product Data (PCI 2.2) 302 */ 303 int pci_vpd_read(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *); 304 int pci_vpd_write(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *); 305 306 /* 307 * Misc. 308 */ 309 int pci_find_device(struct pci_attach_args *pa, 310 int (*match)(const struct pci_attach_args *)); 311 int pci_dma64_available(const struct pci_attach_args *); 312 void pci_conf_capture(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *); 313 void pci_conf_restore(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *); 314 int pci_get_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t *); 315 int pci_set_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t); 316 int pci_activate(pci_chipset_tag_t, pcitag_t, device_t, 317 int (*)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)); 318 int pci_activate_null(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t); 319 int pci_chipset_tag_create(pci_chipset_tag_t, uint64_t, 320 const struct pci_overrides *, 321 void *, pci_chipset_tag_t *); 322 void pci_chipset_tag_destroy(pci_chipset_tag_t); 323 324 /* 325 * Device abstraction for inheritance by elanpci(4), for example. 326 */ 327 int pcimatch(device_t, cfdata_t, void *); 328 void pciattach(device_t, device_t, void *); 329 int pcidetach(device_t, int); 330 void pcidevdetached(device_t, device_t); 331 int pcirescan(device_t, const char *, const int *); 332 333 /* 334 * Interrupts. 335 */ 336 #define PCI_INTR_MPSAFE 1 337 338 int pci_intr_setattr(pci_chipset_tag_t, pci_intr_handle_t *, int, uint64_t); 339 340 #endif /* _KERNEL */ 341 342 #endif /* _DEV_PCI_PCIVAR_H_ */ 343
Indexes created Tue Sep 30 11:09:46 GMT 2025