pcscp.c revision 1.10
1 /* $NetBSD: pcscp.c,v 1.10 2000/06/05 15:08:00 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 42 * written by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp> 43 * 44 * Technical manual available at 45 * http://www.amd.com/products/npd/techdocs/techdocs.html 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 #include <machine/endian.h> 56 57 #include <dev/scsipi/scsi_all.h> 58 #include <dev/scsipi/scsipi_all.h> 59 #include <dev/scsipi/scsiconf.h> 60 #include <dev/scsipi/scsi_message.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 69 #include <dev/pci/pcscpreg.h> 70 71 #define IO_MAP_REG 0x10 72 #define MEM_MAP_REG 0x14 73 74 struct pcscp_softc { 75 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 76 77 bus_space_tag_t sc_st; /* bus space tag */ 78 bus_space_handle_t sc_sh; /* bus space handle */ 79 void *sc_ih; /* interrupt cookie */ 80 81 bus_dma_tag_t sc_dmat; /* DMA tag */ 82 83 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 84 85 u_int32_t *sc_mdladdr; /* MDL array */ 86 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 87 88 int sc_active; /* DMA state */ 89 int sc_datain; /* DMA Data Direction */ 90 size_t sc_dmasize; /* DMA size */ 91 char **sc_dmaaddr; /* DMA address */ 92 size_t *sc_dmalen; /* DMA length */ 93 }; 94 95 #define READ_DMAREG(sc, reg) \ 96 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 97 #define WRITE_DMAREG(sc, reg, var) \ 98 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 99 100 /* don't have to use MI defines in MD code... */ 101 #undef NCR_READ_REG 102 #define NCR_READ_REG(sc, reg) pcscp_read_reg((sc), (reg)) 103 #undef NCR_WRITE_REG 104 #define NCR_WRITE_REG(sc, reg, val) pcscp_write_reg((sc), (reg), (val)) 105 106 int pcscp_match __P((struct device *, struct cfdata *, void *)); 107 void pcscp_attach __P((struct device *, struct device *, void *)); 108 109 struct cfattach pcscp_ca = { 110 sizeof(struct pcscp_softc), pcscp_match, pcscp_attach 111 }; 112 113 /* 114 * Functions and the switch for the MI code. 115 */ 116 117 u_char pcscp_read_reg __P((struct ncr53c9x_softc *, int)); 118 void pcscp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 119 int pcscp_dma_isintr __P((struct ncr53c9x_softc *)); 120 void pcscp_dma_reset __P((struct ncr53c9x_softc *)); 121 int pcscp_dma_intr __P((struct ncr53c9x_softc *)); 122 int pcscp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 123 size_t *, int, size_t *)); 124 void pcscp_dma_go __P((struct ncr53c9x_softc *)); 125 void pcscp_dma_stop __P((struct ncr53c9x_softc *)); 126 int pcscp_dma_isactive __P((struct ncr53c9x_softc *)); 127 128 struct ncr53c9x_glue pcscp_glue = { 129 pcscp_read_reg, 130 pcscp_write_reg, 131 pcscp_dma_isintr, 132 pcscp_dma_reset, 133 pcscp_dma_intr, 134 pcscp_dma_setup, 135 pcscp_dma_go, 136 pcscp_dma_stop, 137 pcscp_dma_isactive, 138 NULL, /* gl_clear_latched_intr */ 139 }; 140 141 int 142 pcscp_match(parent, match, aux) 143 struct device *parent; 144 struct cfdata *match; 145 void *aux; 146 { 147 struct pci_attach_args *pa = aux; 148 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 149 return 0; 150 151 switch (PCI_PRODUCT(pa->pa_id)) { 152 case PCI_PRODUCT_AMD_PCSCSI_PCI: 153 #if 0 154 case PCI_PRODUCT_AMD_PCNETS_PCI: 155 #endif 156 return 1; 157 } 158 return 0; 159 } 160 161 /* 162 * Attach this instance, and then all the sub-devices 163 */ 164 void 165 pcscp_attach(parent, self, aux) 166 struct device *parent, *self; 167 void *aux; 168 { 169 struct pci_attach_args *pa = aux; 170 struct pcscp_softc *esc = (void *)self; 171 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 172 bus_space_tag_t st, iot, memt; 173 bus_space_handle_t sh, ioh, memh; 174 int ioh_valid, memh_valid; 175 pci_intr_handle_t ih; 176 const char *intrstr; 177 pcireg_t csr; 178 bus_dma_segment_t seg; 179 int error, rseg; 180 181 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 182 PCI_MAPREG_TYPE_IO, 0, 183 &iot, &ioh, NULL, NULL) == 0); 184 #if 0 /* XXX cannot use memory map? */ 185 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 186 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 187 &memt, &memh, NULL, NULL) == 0); 188 #else 189 memh_valid = 0; 190 #endif 191 192 if (memh_valid) { 193 st = memt; 194 sh = memh; 195 } else if (ioh_valid) { 196 st = iot; 197 sh = ioh; 198 } else { 199 printf(": unable to map registers\n"); 200 return; 201 } 202 printf("\n"); 203 204 sc->sc_glue = &pcscp_glue; 205 206 esc->sc_st = st; 207 esc->sc_sh = sh; 208 esc->sc_dmat = pa->pa_dmat; 209 210 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 211 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 212 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 213 214 /* 215 * XXX More of this should be in ncr53c9x_attach(), but 216 * XXX should we really poke around the chip that much in 217 * XXX the MI code? Think about this more... 218 */ 219 220 /* 221 * Set up static configuration info. 222 */ 223 224 /* 225 * XXX should read configuration from EEPROM? 226 * 227 * MI ncr53c9x driver does not support configuration 228 * per each target device, though... 229 */ 230 sc->sc_id = 7; 231 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 232 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 233 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 234 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 235 sc->sc_rev = NCR_VARIANT_AM53C974; 236 sc->sc_features = NCR_F_FASTSCSI; 237 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 238 sc->sc_freq = 40; /* MHz */ 239 240 /* 241 * XXX minsync and maxxfer _should_ be set up in MI code, 242 * XXX but it appears to have some dependency on what sort 243 * XXX of DMA we're hooked up to, etc. 244 */ 245 246 /* 247 * This is the value used to start sync negotiations 248 * Note that the NCR register "SYNCTP" is programmed 249 * in "clocks per byte", and has a minimum value of 4. 250 * The SCSI period used in negotiation is one-fourth 251 * of the time (in nanoseconds) needed to transfer one byte. 252 * Since the chip's clock is given in MHz, we have the following 253 * formula: 4 * period = (1000 / freq) * 4 254 */ 255 256 sc->sc_minsync = 1000 / sc->sc_freq; 257 258 /* Really no limit, but since we want to fit into the TCR... */ 259 sc->sc_maxxfer = 16 * 1024 * 1024; 260 261 /* map and establish interrupt */ 262 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 263 pa->pa_intrline, &ih)) { 264 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 265 return; 266 } 267 268 intrstr = pci_intr_string(pa->pa_pc, ih); 269 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 270 ncr53c9x_intr, esc); 271 if (esc->sc_ih == NULL) { 272 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 273 if (intrstr != NULL) 274 printf(" at %s", intrstr); 275 printf("\n"); 276 return; 277 } 278 if (intrstr != NULL) 279 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 280 intrstr); 281 282 /* 283 * Create the DMA maps for the data transfers. 284 */ 285 286 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 287 #define MDL_SEG_OFFSET 0x0FFF 288 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 289 290 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MAXPHYS, 0, 291 BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 292 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname); 293 return; 294 } 295 296 /* 297 * Allocate and map memory for the MDL. 298 */ 299 300 if ((error = bus_dmamem_alloc(esc->sc_dmat, 301 sizeof(u_int32_t) * MDL_SIZE, NBPG, 0, &seg, 1, &rseg, 302 BUS_DMA_NOWAIT)) != 0) { 303 printf("%s: unable to allocate memory for the MDL, " 304 "error = %d\n", sc->sc_dev.dv_xname, error); 305 return; 306 } 307 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 308 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 309 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 310 printf("%s: unable to map the MDL memory, error = %d\n", 311 sc->sc_dev.dv_xname, error); 312 return; 313 } 314 if ((error = bus_dmamap_create(esc->sc_dmat, 315 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 316 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 317 printf("%s: unable to map_create for the MDL, error = %d\n", 318 sc->sc_dev.dv_xname, error); 319 return; 320 } 321 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 322 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 323 NULL, BUS_DMA_NOWAIT)) != 0) { 324 printf("%s: unable to load for the MDL, error = %d\n", 325 sc->sc_dev.dv_xname, error); 326 return; 327 } 328 329 /* Do the common parts of attachment. */ 330 printf("%s", sc->sc_dev.dv_xname); 331 332 ncr53c9x_attach(sc, NULL, NULL); 333 334 /* Turn on target selection using the `dma' method */ 335 ncr53c9x_dmaselect = 1; 336 } 337 338 /* 339 * Glue functions. 340 */ 341 342 u_char 343 pcscp_read_reg(sc, reg) 344 struct ncr53c9x_softc *sc; 345 int reg; 346 { 347 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 348 349 return bus_space_read_1(esc->sc_st, esc->sc_sh, reg << 2); 350 } 351 352 void 353 pcscp_write_reg(sc, reg, v) 354 struct ncr53c9x_softc *sc; 355 int reg; 356 u_char v; 357 { 358 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 359 360 bus_space_write_1(esc->sc_st, esc->sc_sh, reg << 2, v); 361 } 362 363 int 364 pcscp_dma_isintr(sc) 365 struct ncr53c9x_softc *sc; 366 { 367 368 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 369 } 370 371 void 372 pcscp_dma_reset(sc) 373 struct ncr53c9x_softc *sc; 374 { 375 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 376 377 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 378 379 esc->sc_active = 0; 380 } 381 382 int 383 pcscp_dma_intr(sc) 384 struct ncr53c9x_softc *sc; 385 { 386 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 387 int trans, resid, i; 388 bus_dmamap_t dmap = esc->sc_xfermap; 389 int datain = esc->sc_datain; 390 u_int32_t dmastat; 391 char *p = NULL; 392 393 dmastat = READ_DMAREG(esc, DMA_STAT); 394 395 if (dmastat & DMASTAT_ERR) { 396 /* XXX not tested... */ 397 WRITE_DMAREG(esc, DMA_CMD, 398 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 399 400 printf("%s: error: DMA error detected; Aborting.\n", 401 sc->sc_dev.dv_xname); 402 bus_dmamap_unload(esc->sc_dmat, dmap); 403 return -1; 404 } 405 406 if (dmastat & DMASTAT_ABT) { 407 /* XXX What should be done? */ 408 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 409 WRITE_DMAREG(esc, DMA_CMD, 410 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 411 esc->sc_active = 0; 412 return 0; 413 } 414 415 /* This is an "assertion" :) */ 416 if (esc->sc_active == 0) 417 panic("pcscp dmaintr: DMA wasn't active"); 418 419 /* DMA has stopped */ 420 421 esc->sc_active = 0; 422 423 if (esc->sc_dmasize == 0) { 424 /* A "Transfer Pad" operation completed */ 425 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 426 NCR_READ_REG(sc, NCR_TCL) | 427 (NCR_READ_REG(sc, NCR_TCM) << 8), 428 NCR_READ_REG(sc, NCR_TCL), 429 NCR_READ_REG(sc, NCR_TCM))); 430 return 0; 431 } 432 433 resid = 0; 434 /* 435 * If a transfer onto the SCSI bus gets interrupted by the device 436 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 437 * as residual since the ESP counter registers get decremented as 438 * bytes are clocked into the FIFO. 439 */ 440 if (!datain && 441 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 442 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 443 } 444 445 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 446 /* 447 * `Terminal count' is off, so read the residue 448 * out of the ESP counter registers. 449 */ 450 if (datain) { 451 resid = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 452 while (resid > 1) 453 resid = 454 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 455 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 456 (datain ? DMACMD_DIR : 0)); 457 458 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 459 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 460 break; 461 462 /* See the below comments... */ 463 if (resid) 464 p = *esc->sc_dmaaddr; 465 } 466 467 resid += (NCR_READ_REG(sc, NCR_TCL) | 468 (NCR_READ_REG(sc, NCR_TCM) << 8) | 469 ((sc->sc_cfg2 & NCRCFG2_FE) 470 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 471 472 if (resid == 0 && esc->sc_dmasize == 65536 && 473 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 474 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 475 resid = 65536; 476 } else { 477 while((dmastat & DMASTAT_DONE) == 0) 478 dmastat = READ_DMAREG(esc, DMA_STAT); 479 } 480 481 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 482 483 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 484 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 485 bus_dmamap_unload(esc->sc_dmat, dmap); 486 487 trans = esc->sc_dmasize - resid; 488 489 /* 490 * From the technical manual notes: 491 * 492 * `In some odd byte conditions, one residual byte will be left 493 * in the SCSI FIFO, and the FIFO flags will never count to 0. 494 * When this happens, the residual byte should be retrieved 495 * via PIO following completion of the BLAST operation.' 496 */ 497 498 if (p) { 499 p += trans; 500 *p = NCR_READ_REG(sc, NCR_FIFO); 501 trans++; 502 } 503 504 if (trans < 0) { /* transferred < 0 ? */ 505 #if 0 506 /* 507 * This situation can happen in perfectly normal operation 508 * if the ESP is reselected while using DMA to select 509 * another target. As such, don't print the warning. 510 */ 511 printf("%s: xfer (%d) > req (%d)\n", 512 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 513 #endif 514 trans = esc->sc_dmasize; 515 } 516 517 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 518 NCR_READ_REG(sc, NCR_TCL), 519 NCR_READ_REG(sc, NCR_TCM), 520 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 521 trans, resid)); 522 523 *esc->sc_dmalen -= trans; 524 *esc->sc_dmaaddr += trans; 525 526 return 0; 527 } 528 529 int 530 pcscp_dma_setup(sc, addr, len, datain, dmasize) 531 struct ncr53c9x_softc *sc; 532 caddr_t *addr; 533 size_t *len; 534 int datain; 535 size_t *dmasize; 536 { 537 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 538 bus_dmamap_t dmap = esc->sc_xfermap; 539 u_int32_t *mdl; 540 int error, nseg, seg; 541 bus_addr_t s_offset, s_addr; 542 long rest, count; 543 544 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 545 546 esc->sc_dmaaddr = addr; 547 esc->sc_dmalen = len; 548 esc->sc_dmasize = *dmasize; 549 esc->sc_datain = datain; 550 551 #ifdef DIAGNOSTIC 552 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 553 panic("pcscp: transfer size too large"); 554 #endif 555 556 /* 557 * No need to set up DMA in `Transfer Pad' operation. 558 * (case of *dmasize == 0) 559 */ 560 if (*dmasize == 0) 561 return 0; 562 563 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 564 *esc->sc_dmalen, NULL, 565 sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP ? 566 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 567 if (error) { 568 printf("%s: unable to load dmamap, error = %d\n", 569 sc->sc_dev.dv_xname, error); 570 return error; 571 } 572 573 /* set transfer length */ 574 WRITE_DMAREG(esc, DMA_STC, *dmasize); 575 576 /* set up MDL */ 577 mdl = esc->sc_mdladdr; 578 nseg = dmap->dm_nsegs; 579 580 /* the first segment is possibly not aligned with 4k MDL boundary */ 581 count = dmap->dm_segs[0].ds_len; 582 s_addr = dmap->dm_segs[0].ds_addr; 583 s_offset = s_addr & MDL_SEG_OFFSET; 584 s_addr -= s_offset; 585 rest = MDL_SEG_SIZE - s_offset; 586 587 /* set the first MDL and offset */ 588 WRITE_DMAREG(esc, DMA_SPA, s_offset); 589 *mdl++ = htole32(s_addr); 590 count -= rest; 591 592 /* rests of the first dmamap segment */ 593 while (count > 0) { 594 s_addr += MDL_SEG_SIZE; 595 *mdl++ = htole32(s_addr); 596 count -= MDL_SEG_SIZE; 597 } 598 599 /* the rest dmamap segments are aligned with 4k boundary */ 600 for (seg = 1; seg < nseg; seg++) { 601 count = dmap->dm_segs[seg].ds_len; 602 s_addr = dmap->dm_segs[seg].ds_addr; 603 604 /* first 4kbyte of each dmamap segment */ 605 *mdl++ = htole32(s_addr); 606 count -= MDL_SEG_SIZE; 607 608 /* trailing contiguous 4k frames of each dmamap segments */ 609 while (count > 0) { 610 s_addr += MDL_SEG_SIZE; 611 *mdl++ = htole32(s_addr); 612 count -= MDL_SEG_SIZE; 613 } 614 } 615 616 return 0; 617 } 618 619 void 620 pcscp_dma_go(sc) 621 struct ncr53c9x_softc *sc; 622 { 623 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 624 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 625 int datain = esc->sc_datain; 626 627 /* No DMA transfer in Transfer Pad operation */ 628 if (esc->sc_dmasize == 0) 629 return; 630 631 /* sync transfer buffer */ 632 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 633 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 634 635 /* sync MDL */ 636 bus_dmamap_sync(esc->sc_dmat, mdldmap, 0, mdldmap->dm_mapsize, 637 BUS_DMASYNC_PREWRITE); 638 639 /* set Starting MDL Address */ 640 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 641 642 /* set DMA command register bits */ 643 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 644 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 645 /* DMACMD_INTE | */ 646 (datain ? DMACMD_DIR : 0)); 647 648 /* issue DMA start command */ 649 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 650 /* DMACMD_INTE | */ 651 (datain ? DMACMD_DIR : 0)); 652 653 esc->sc_active = 1; 654 } 655 656 void 657 pcscp_dma_stop(sc) 658 struct ncr53c9x_softc *sc; 659 { 660 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 661 662 /* dma stop */ 663 /* XXX What should we do here ? */ 664 WRITE_DMAREG(esc, DMA_CMD, 665 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 666 667 esc->sc_active = 0; 668 } 669 670 int 671 pcscp_dma_isactive(sc) 672 struct ncr53c9x_softc *sc; 673 { 674 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 675 676 /* XXX should check esc->sc_active? */ 677 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 678 return 1; 679 return 0; 680 } 681
Indexes created Tue Sep 23 02:09:52 GMT 2025