pcscp.c revision 1.17
1 /* $NetBSD: pcscp.c,v 1.17 2001/11/13 07:48:48 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 42 * written by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp> 43 * 44 * Technical manual available at 45 * http://www.amd.com/products/npd/techdocs/techdocs.html 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: pcscp.c,v 1.17 2001/11/13 07:48:48 lukem Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 #include <machine/endian.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsi_all.h> 64 #include <dev/scsipi/scsiconf.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/ic/ncr53c9xreg.h> 71 #include <dev/ic/ncr53c9xvar.h> 72 73 #include <dev/pci/pcscpreg.h> 74 75 #define IO_MAP_REG 0x10 76 #define MEM_MAP_REG 0x14 77 78 struct pcscp_softc { 79 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 80 81 bus_space_tag_t sc_st; /* bus space tag */ 82 bus_space_handle_t sc_sh; /* bus space handle */ 83 void *sc_ih; /* interrupt cookie */ 84 85 bus_dma_tag_t sc_dmat; /* DMA tag */ 86 87 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 88 89 u_int32_t *sc_mdladdr; /* MDL array */ 90 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 91 92 int sc_active; /* DMA state */ 93 int sc_datain; /* DMA Data Direction */ 94 size_t sc_dmasize; /* DMA size */ 95 char **sc_dmaaddr; /* DMA address */ 96 size_t *sc_dmalen; /* DMA length */ 97 }; 98 99 #define READ_DMAREG(sc, reg) \ 100 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 101 #define WRITE_DMAREG(sc, reg, var) \ 102 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 103 104 /* don't have to use MI defines in MD code... */ 105 #undef NCR_READ_REG 106 #define NCR_READ_REG(sc, reg) pcscp_read_reg((sc), (reg)) 107 #undef NCR_WRITE_REG 108 #define NCR_WRITE_REG(sc, reg, val) pcscp_write_reg((sc), (reg), (val)) 109 110 int pcscp_match __P((struct device *, struct cfdata *, void *)); 111 void pcscp_attach __P((struct device *, struct device *, void *)); 112 113 struct cfattach pcscp_ca = { 114 sizeof(struct pcscp_softc), pcscp_match, pcscp_attach 115 }; 116 117 /* 118 * Functions and the switch for the MI code. 119 */ 120 121 u_char pcscp_read_reg __P((struct ncr53c9x_softc *, int)); 122 void pcscp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 123 int pcscp_dma_isintr __P((struct ncr53c9x_softc *)); 124 void pcscp_dma_reset __P((struct ncr53c9x_softc *)); 125 int pcscp_dma_intr __P((struct ncr53c9x_softc *)); 126 int pcscp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 127 size_t *, int, size_t *)); 128 void pcscp_dma_go __P((struct ncr53c9x_softc *)); 129 void pcscp_dma_stop __P((struct ncr53c9x_softc *)); 130 int pcscp_dma_isactive __P((struct ncr53c9x_softc *)); 131 132 struct ncr53c9x_glue pcscp_glue = { 133 pcscp_read_reg, 134 pcscp_write_reg, 135 pcscp_dma_isintr, 136 pcscp_dma_reset, 137 pcscp_dma_intr, 138 pcscp_dma_setup, 139 pcscp_dma_go, 140 pcscp_dma_stop, 141 pcscp_dma_isactive, 142 NULL, /* gl_clear_latched_intr */ 143 }; 144 145 int 146 pcscp_match(parent, match, aux) 147 struct device *parent; 148 struct cfdata *match; 149 void *aux; 150 { 151 struct pci_attach_args *pa = aux; 152 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 153 return 0; 154 155 switch (PCI_PRODUCT(pa->pa_id)) { 156 case PCI_PRODUCT_AMD_PCSCSI_PCI: 157 #if 0 158 case PCI_PRODUCT_AMD_PCNETS_PCI: 159 #endif 160 return 1; 161 } 162 return 0; 163 } 164 165 /* 166 * Attach this instance, and then all the sub-devices 167 */ 168 void 169 pcscp_attach(parent, self, aux) 170 struct device *parent, *self; 171 void *aux; 172 { 173 struct pci_attach_args *pa = aux; 174 struct pcscp_softc *esc = (void *)self; 175 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 176 bus_space_tag_t st, iot, memt; 177 bus_space_handle_t sh, ioh, memh; 178 int ioh_valid, memh_valid; 179 pci_intr_handle_t ih; 180 const char *intrstr; 181 pcireg_t csr; 182 bus_dma_segment_t seg; 183 int error, rseg; 184 185 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 186 PCI_MAPREG_TYPE_IO, 0, 187 &iot, &ioh, NULL, NULL) == 0); 188 #if 0 /* XXX cannot use memory map? */ 189 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 190 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 191 &memt, &memh, NULL, NULL) == 0); 192 #else 193 memh_valid = 0; 194 #endif 195 196 if (memh_valid) { 197 st = memt; 198 sh = memh; 199 } else if (ioh_valid) { 200 st = iot; 201 sh = ioh; 202 } else { 203 printf(": unable to map registers\n"); 204 return; 205 } 206 printf("\n"); 207 208 sc->sc_glue = &pcscp_glue; 209 210 esc->sc_st = st; 211 esc->sc_sh = sh; 212 esc->sc_dmat = pa->pa_dmat; 213 214 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 215 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 216 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 217 218 /* 219 * XXX More of this should be in ncr53c9x_attach(), but 220 * XXX should we really poke around the chip that much in 221 * XXX the MI code? Think about this more... 222 */ 223 224 /* 225 * Set up static configuration info. 226 */ 227 228 /* 229 * XXX should read configuration from EEPROM? 230 * 231 * MI ncr53c9x driver does not support configuration 232 * per each target device, though... 233 */ 234 sc->sc_id = 7; 235 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 236 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 237 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 238 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 239 sc->sc_rev = NCR_VARIANT_AM53C974; 240 sc->sc_features = NCR_F_FASTSCSI; 241 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 242 sc->sc_freq = 40; /* MHz */ 243 244 /* 245 * XXX minsync and maxxfer _should_ be set up in MI code, 246 * XXX but it appears to have some dependency on what sort 247 * XXX of DMA we're hooked up to, etc. 248 */ 249 250 /* 251 * This is the value used to start sync negotiations 252 * Note that the NCR register "SYNCTP" is programmed 253 * in "clocks per byte", and has a minimum value of 4. 254 * The SCSI period used in negotiation is one-fourth 255 * of the time (in nanoseconds) needed to transfer one byte. 256 * Since the chip's clock is given in MHz, we have the following 257 * formula: 4 * period = (1000 / freq) * 4 258 */ 259 260 sc->sc_minsync = 1000 / sc->sc_freq; 261 262 /* Really no limit, but since we want to fit into the TCR... */ 263 sc->sc_maxxfer = 16 * 1024 * 1024; 264 265 /* map and establish interrupt */ 266 if (pci_intr_map(pa, &ih)) { 267 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 268 return; 269 } 270 271 intrstr = pci_intr_string(pa->pa_pc, ih); 272 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 273 ncr53c9x_intr, esc); 274 if (esc->sc_ih == NULL) { 275 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 276 if (intrstr != NULL) 277 printf(" at %s", intrstr); 278 printf("\n"); 279 return; 280 } 281 if (intrstr != NULL) 282 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 283 intrstr); 284 285 /* 286 * Create the DMA maps for the data transfers. 287 */ 288 289 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 290 #define MDL_SEG_OFFSET 0x0FFF 291 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 292 293 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MAXPHYS, 0, 294 BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 295 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname); 296 return; 297 } 298 299 /* 300 * Allocate and map memory for the MDL. 301 */ 302 303 if ((error = bus_dmamem_alloc(esc->sc_dmat, 304 sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 305 BUS_DMA_NOWAIT)) != 0) { 306 printf("%s: unable to allocate memory for the MDL, " 307 "error = %d\n", sc->sc_dev.dv_xname, error); 308 return; 309 } 310 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 311 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 312 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 313 printf("%s: unable to map the MDL memory, error = %d\n", 314 sc->sc_dev.dv_xname, error); 315 return; 316 } 317 if ((error = bus_dmamap_create(esc->sc_dmat, 318 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 319 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 320 printf("%s: unable to map_create for the MDL, error = %d\n", 321 sc->sc_dev.dv_xname, error); 322 return; 323 } 324 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 325 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 326 NULL, BUS_DMA_NOWAIT)) != 0) { 327 printf("%s: unable to load for the MDL, error = %d\n", 328 sc->sc_dev.dv_xname, error); 329 return; 330 } 331 332 /* Do the common parts of attachment. */ 333 printf("%s", sc->sc_dev.dv_xname); 334 335 sc->sc_adapter.adapt_minphys = minphys; 336 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 337 ncr53c9x_attach(sc); 338 339 /* Turn on target selection using the `dma' method */ 340 sc->sc_features |= NCR_F_DMASELECT; 341 } 342 343 /* 344 * Glue functions. 345 */ 346 347 u_char 348 pcscp_read_reg(sc, reg) 349 struct ncr53c9x_softc *sc; 350 int reg; 351 { 352 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 353 354 return bus_space_read_1(esc->sc_st, esc->sc_sh, reg << 2); 355 } 356 357 void 358 pcscp_write_reg(sc, reg, v) 359 struct ncr53c9x_softc *sc; 360 int reg; 361 u_char v; 362 { 363 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 364 365 bus_space_write_1(esc->sc_st, esc->sc_sh, reg << 2, v); 366 } 367 368 int 369 pcscp_dma_isintr(sc) 370 struct ncr53c9x_softc *sc; 371 { 372 373 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 374 } 375 376 void 377 pcscp_dma_reset(sc) 378 struct ncr53c9x_softc *sc; 379 { 380 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 381 382 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 383 384 esc->sc_active = 0; 385 } 386 387 int 388 pcscp_dma_intr(sc) 389 struct ncr53c9x_softc *sc; 390 { 391 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 392 int trans, resid, i; 393 bus_dmamap_t dmap = esc->sc_xfermap; 394 int datain = esc->sc_datain; 395 u_int32_t dmastat; 396 char *p = NULL; 397 398 dmastat = READ_DMAREG(esc, DMA_STAT); 399 400 if (dmastat & DMASTAT_ERR) { 401 /* XXX not tested... */ 402 WRITE_DMAREG(esc, DMA_CMD, 403 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 404 405 printf("%s: error: DMA error detected; Aborting.\n", 406 sc->sc_dev.dv_xname); 407 bus_dmamap_unload(esc->sc_dmat, dmap); 408 return -1; 409 } 410 411 if (dmastat & DMASTAT_ABT) { 412 /* XXX What should be done? */ 413 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 414 WRITE_DMAREG(esc, DMA_CMD, 415 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 416 esc->sc_active = 0; 417 return 0; 418 } 419 420 /* This is an "assertion" :) */ 421 if (esc->sc_active == 0) 422 panic("pcscp dmaintr: DMA wasn't active"); 423 424 /* DMA has stopped */ 425 426 esc->sc_active = 0; 427 428 if (esc->sc_dmasize == 0) { 429 /* A "Transfer Pad" operation completed */ 430 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 431 NCR_READ_REG(sc, NCR_TCL) | 432 (NCR_READ_REG(sc, NCR_TCM) << 8), 433 NCR_READ_REG(sc, NCR_TCL), 434 NCR_READ_REG(sc, NCR_TCM))); 435 return 0; 436 } 437 438 resid = 0; 439 /* 440 * If a transfer onto the SCSI bus gets interrupted by the device 441 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 442 * as residual since the ESP counter registers get decremented as 443 * bytes are clocked into the FIFO. 444 */ 445 if (!datain && 446 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 447 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 448 } 449 450 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 451 /* 452 * `Terminal count' is off, so read the residue 453 * out of the ESP counter registers. 454 */ 455 if (datain) { 456 resid = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 457 while (resid > 1) 458 resid = 459 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 460 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 461 (datain ? DMACMD_DIR : 0)); 462 463 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 464 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 465 break; 466 467 /* See the below comments... */ 468 if (resid) 469 p = *esc->sc_dmaaddr; 470 } 471 472 resid += (NCR_READ_REG(sc, NCR_TCL) | 473 (NCR_READ_REG(sc, NCR_TCM) << 8) | 474 ((sc->sc_cfg2 & NCRCFG2_FE) 475 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 476 477 if (resid == 0 && esc->sc_dmasize == 65536 && 478 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 479 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 480 resid = 65536; 481 } else { 482 while((dmastat & DMASTAT_DONE) == 0) 483 dmastat = READ_DMAREG(esc, DMA_STAT); 484 } 485 486 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 487 488 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 489 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 490 bus_dmamap_unload(esc->sc_dmat, dmap); 491 492 trans = esc->sc_dmasize - resid; 493 494 /* 495 * From the technical manual notes: 496 * 497 * `In some odd byte conditions, one residual byte will be left 498 * in the SCSI FIFO, and the FIFO flags will never count to 0. 499 * When this happens, the residual byte should be retrieved 500 * via PIO following completion of the BLAST operation.' 501 */ 502 503 if (p) { 504 p += trans; 505 *p = NCR_READ_REG(sc, NCR_FIFO); 506 trans++; 507 } 508 509 if (trans < 0) { /* transferred < 0 ? */ 510 #if 0 511 /* 512 * This situation can happen in perfectly normal operation 513 * if the ESP is reselected while using DMA to select 514 * another target. As such, don't print the warning. 515 */ 516 printf("%s: xfer (%d) > req (%d)\n", 517 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 518 #endif 519 trans = esc->sc_dmasize; 520 } 521 522 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 523 NCR_READ_REG(sc, NCR_TCL), 524 NCR_READ_REG(sc, NCR_TCM), 525 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 526 trans, resid)); 527 528 *esc->sc_dmalen -= trans; 529 *esc->sc_dmaaddr += trans; 530 531 return 0; 532 } 533 534 int 535 pcscp_dma_setup(sc, addr, len, datain, dmasize) 536 struct ncr53c9x_softc *sc; 537 caddr_t *addr; 538 size_t *len; 539 int datain; 540 size_t *dmasize; 541 { 542 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 543 bus_dmamap_t dmap = esc->sc_xfermap; 544 u_int32_t *mdl; 545 int error, nseg, seg; 546 bus_addr_t s_offset, s_addr; 547 long rest, count; 548 549 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 550 551 esc->sc_dmaaddr = addr; 552 esc->sc_dmalen = len; 553 esc->sc_dmasize = *dmasize; 554 esc->sc_datain = datain; 555 556 #ifdef DIAGNOSTIC 557 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 558 panic("pcscp: transfer size too large"); 559 #endif 560 561 /* 562 * No need to set up DMA in `Transfer Pad' operation. 563 * (case of *dmasize == 0) 564 */ 565 if (*dmasize == 0) 566 return 0; 567 568 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 569 *esc->sc_dmalen, NULL, 570 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 571 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 572 ((sc->sc_nexus->xs->xs_control & XS_CTL_DATA_IN) ? 573 BUS_DMA_READ : BUS_DMA_WRITE)); 574 if (error) { 575 printf("%s: unable to load dmamap, error = %d\n", 576 sc->sc_dev.dv_xname, error); 577 return error; 578 } 579 580 /* set transfer length */ 581 WRITE_DMAREG(esc, DMA_STC, *dmasize); 582 583 /* set up MDL */ 584 mdl = esc->sc_mdladdr; 585 nseg = dmap->dm_nsegs; 586 587 /* the first segment is possibly not aligned with 4k MDL boundary */ 588 count = dmap->dm_segs[0].ds_len; 589 s_addr = dmap->dm_segs[0].ds_addr; 590 s_offset = s_addr & MDL_SEG_OFFSET; 591 s_addr -= s_offset; 592 rest = MDL_SEG_SIZE - s_offset; 593 594 /* set the first MDL and offset */ 595 WRITE_DMAREG(esc, DMA_SPA, s_offset); 596 *mdl++ = htole32(s_addr); 597 count -= rest; 598 599 /* rests of the first dmamap segment */ 600 while (count > 0) { 601 s_addr += MDL_SEG_SIZE; 602 *mdl++ = htole32(s_addr); 603 count -= MDL_SEG_SIZE; 604 } 605 606 /* the rest dmamap segments are aligned with 4k boundary */ 607 for (seg = 1; seg < nseg; seg++) { 608 count = dmap->dm_segs[seg].ds_len; 609 s_addr = dmap->dm_segs[seg].ds_addr; 610 611 /* first 4kbyte of each dmamap segment */ 612 *mdl++ = htole32(s_addr); 613 count -= MDL_SEG_SIZE; 614 615 /* trailing contiguous 4k frames of each dmamap segments */ 616 while (count > 0) { 617 s_addr += MDL_SEG_SIZE; 618 *mdl++ = htole32(s_addr); 619 count -= MDL_SEG_SIZE; 620 } 621 } 622 623 return 0; 624 } 625 626 void 627 pcscp_dma_go(sc) 628 struct ncr53c9x_softc *sc; 629 { 630 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 631 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 632 int datain = esc->sc_datain; 633 634 /* No DMA transfer in Transfer Pad operation */ 635 if (esc->sc_dmasize == 0) 636 return; 637 638 /* sync transfer buffer */ 639 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 640 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 641 642 /* sync MDL */ 643 bus_dmamap_sync(esc->sc_dmat, mdldmap, 0, mdldmap->dm_mapsize, 644 BUS_DMASYNC_PREWRITE); 645 646 /* set Starting MDL Address */ 647 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 648 649 /* set DMA command register bits */ 650 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 651 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 652 /* DMACMD_INTE | */ 653 (datain ? DMACMD_DIR : 0)); 654 655 /* issue DMA start command */ 656 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 657 /* DMACMD_INTE | */ 658 (datain ? DMACMD_DIR : 0)); 659 660 esc->sc_active = 1; 661 } 662 663 void 664 pcscp_dma_stop(sc) 665 struct ncr53c9x_softc *sc; 666 { 667 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 668 669 /* dma stop */ 670 /* XXX What should we do here ? */ 671 WRITE_DMAREG(esc, DMA_CMD, 672 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 673 674 esc->sc_active = 0; 675 } 676 677 int 678 pcscp_dma_isactive(sc) 679 struct ncr53c9x_softc *sc; 680 { 681 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 682 683 /* XXX should check esc->sc_active? */ 684 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 685 return 1; 686 return 0; 687 } 688
Indexes created Mon Sep 22 13:09:51 GMT 2025