pcscp.c revision 1.21
1 /* $NetBSD: pcscp.c,v 1.21 2002/11/15 22:13:12 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 42 * written by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp> 43 * 44 * Technical manual available at 45 * http://www.amd.com/products/npd/techdocs/techdocs.html 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: pcscp.c,v 1.21 2002/11/15 22:13:12 tsutsui Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 #include <machine/endian.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsi_all.h> 64 #include <dev/scsipi/scsiconf.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/ic/ncr53c9xreg.h> 71 #include <dev/ic/ncr53c9xvar.h> 72 73 #include <dev/pci/pcscpreg.h> 74 75 #define IO_MAP_REG 0x10 76 #define MEM_MAP_REG 0x14 77 78 struct pcscp_softc { 79 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 80 81 bus_space_tag_t sc_st; /* bus space tag */ 82 bus_space_handle_t sc_sh; /* bus space handle */ 83 void *sc_ih; /* interrupt cookie */ 84 85 bus_dma_tag_t sc_dmat; /* DMA tag */ 86 87 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 88 89 u_int32_t *sc_mdladdr; /* MDL array */ 90 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 91 92 int sc_active; /* DMA state */ 93 int sc_datain; /* DMA Data Direction */ 94 size_t sc_dmasize; /* DMA size */ 95 char **sc_dmaaddr; /* DMA address */ 96 size_t *sc_dmalen; /* DMA length */ 97 }; 98 99 #define READ_DMAREG(sc, reg) \ 100 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 101 #define WRITE_DMAREG(sc, reg, var) \ 102 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 103 104 /* don't have to use MI defines in MD code... */ 105 #undef NCR_READ_REG 106 #define NCR_READ_REG(sc, reg) pcscp_read_reg((sc), (reg)) 107 #undef NCR_WRITE_REG 108 #define NCR_WRITE_REG(sc, reg, val) pcscp_write_reg((sc), (reg), (val)) 109 110 int pcscp_match __P((struct device *, struct cfdata *, void *)); 111 void pcscp_attach __P((struct device *, struct device *, void *)); 112 113 CFATTACH_DECL(pcscp, sizeof(struct pcscp_softc), 114 pcscp_match, pcscp_attach, NULL, NULL); 115 116 /* 117 * Functions and the switch for the MI code. 118 */ 119 120 u_char pcscp_read_reg __P((struct ncr53c9x_softc *, int)); 121 void pcscp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 122 int pcscp_dma_isintr __P((struct ncr53c9x_softc *)); 123 void pcscp_dma_reset __P((struct ncr53c9x_softc *)); 124 int pcscp_dma_intr __P((struct ncr53c9x_softc *)); 125 int pcscp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 126 size_t *, int, size_t *)); 127 void pcscp_dma_go __P((struct ncr53c9x_softc *)); 128 void pcscp_dma_stop __P((struct ncr53c9x_softc *)); 129 int pcscp_dma_isactive __P((struct ncr53c9x_softc *)); 130 131 struct ncr53c9x_glue pcscp_glue = { 132 pcscp_read_reg, 133 pcscp_write_reg, 134 pcscp_dma_isintr, 135 pcscp_dma_reset, 136 pcscp_dma_intr, 137 pcscp_dma_setup, 138 pcscp_dma_go, 139 pcscp_dma_stop, 140 pcscp_dma_isactive, 141 NULL, /* gl_clear_latched_intr */ 142 }; 143 144 int 145 pcscp_match(parent, match, aux) 146 struct device *parent; 147 struct cfdata *match; 148 void *aux; 149 { 150 struct pci_attach_args *pa = aux; 151 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 152 return 0; 153 154 switch (PCI_PRODUCT(pa->pa_id)) { 155 case PCI_PRODUCT_AMD_PCSCSI_PCI: 156 return 1; 157 } 158 return 0; 159 } 160 161 /* 162 * Attach this instance, and then all the sub-devices 163 */ 164 void 165 pcscp_attach(parent, self, aux) 166 struct device *parent, *self; 167 void *aux; 168 { 169 struct pci_attach_args *pa = aux; 170 struct pcscp_softc *esc = (void *)self; 171 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 172 bus_space_tag_t st, iot, memt; 173 bus_space_handle_t sh, ioh, memh; 174 int ioh_valid, memh_valid; 175 pci_intr_handle_t ih; 176 const char *intrstr; 177 pcireg_t csr; 178 bus_dma_segment_t seg; 179 int error, rseg; 180 181 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 182 PCI_MAPREG_TYPE_IO, 0, 183 &iot, &ioh, NULL, NULL) == 0); 184 #if 0 /* XXX cannot use memory map? */ 185 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 186 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 187 &memt, &memh, NULL, NULL) == 0); 188 #else 189 memh_valid = 0; 190 #endif 191 192 if (memh_valid) { 193 st = memt; 194 sh = memh; 195 } else if (ioh_valid) { 196 st = iot; 197 sh = ioh; 198 } else { 199 printf(": unable to map registers\n"); 200 return; 201 } 202 printf("\n"); 203 204 sc->sc_glue = &pcscp_glue; 205 206 esc->sc_st = st; 207 esc->sc_sh = sh; 208 esc->sc_dmat = pa->pa_dmat; 209 210 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 211 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 212 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 213 214 /* 215 * XXX More of this should be in ncr53c9x_attach(), but 216 * XXX should we really poke around the chip that much in 217 * XXX the MI code? Think about this more... 218 */ 219 220 /* 221 * Set up static configuration info. 222 */ 223 224 /* 225 * XXX should read configuration from EEPROM? 226 * 227 * MI ncr53c9x driver does not support configuration 228 * per each target device, though... 229 */ 230 sc->sc_id = 7; 231 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 232 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 233 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 234 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 235 sc->sc_rev = NCR_VARIANT_AM53C974; 236 sc->sc_features = NCR_F_FASTSCSI; 237 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 238 sc->sc_freq = 40; /* MHz */ 239 240 /* 241 * XXX minsync and maxxfer _should_ be set up in MI code, 242 * XXX but it appears to have some dependency on what sort 243 * XXX of DMA we're hooked up to, etc. 244 */ 245 246 /* 247 * This is the value used to start sync negotiations 248 * Note that the NCR register "SYNCTP" is programmed 249 * in "clocks per byte", and has a minimum value of 4. 250 * The SCSI period used in negotiation is one-fourth 251 * of the time (in nanoseconds) needed to transfer one byte. 252 * Since the chip's clock is given in MHz, we have the following 253 * formula: 4 * period = (1000 / freq) * 4 254 */ 255 256 sc->sc_minsync = 1000 / sc->sc_freq; 257 258 /* Really no limit, but since we want to fit into the TCR... */ 259 sc->sc_maxxfer = 16 * 1024 * 1024; 260 261 /* map and establish interrupt */ 262 if (pci_intr_map(pa, &ih)) { 263 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 264 return; 265 } 266 267 intrstr = pci_intr_string(pa->pa_pc, ih); 268 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 269 ncr53c9x_intr, esc); 270 if (esc->sc_ih == NULL) { 271 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 272 if (intrstr != NULL) 273 printf(" at %s", intrstr); 274 printf("\n"); 275 return; 276 } 277 if (intrstr != NULL) 278 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 279 intrstr); 280 281 /* 282 * Create the DMA maps for the data transfers. 283 */ 284 285 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 286 #define MDL_SEG_OFFSET 0x0FFF 287 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 288 289 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MAXPHYS, 0, 290 BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 291 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname); 292 return; 293 } 294 295 /* 296 * Allocate and map memory for the MDL. 297 */ 298 299 if ((error = bus_dmamem_alloc(esc->sc_dmat, 300 sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 301 BUS_DMA_NOWAIT)) != 0) { 302 printf("%s: unable to allocate memory for the MDL, " 303 "error = %d\n", sc->sc_dev.dv_xname, error); 304 return; 305 } 306 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 307 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 308 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 309 printf("%s: unable to map the MDL memory, error = %d\n", 310 sc->sc_dev.dv_xname, error); 311 return; 312 } 313 if ((error = bus_dmamap_create(esc->sc_dmat, 314 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 315 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 316 printf("%s: unable to map_create for the MDL, error = %d\n", 317 sc->sc_dev.dv_xname, error); 318 return; 319 } 320 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 321 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 322 NULL, BUS_DMA_NOWAIT)) != 0) { 323 printf("%s: unable to load for the MDL, error = %d\n", 324 sc->sc_dev.dv_xname, error); 325 return; 326 } 327 328 /* Do the common parts of attachment. */ 329 printf("%s", sc->sc_dev.dv_xname); 330 331 sc->sc_adapter.adapt_minphys = minphys; 332 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 333 ncr53c9x_attach(sc); 334 335 /* Turn on target selection using the `dma' method */ 336 sc->sc_features |= NCR_F_DMASELECT; 337 } 338 339 /* 340 * Glue functions. 341 */ 342 343 u_char 344 pcscp_read_reg(sc, reg) 345 struct ncr53c9x_softc *sc; 346 int reg; 347 { 348 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 349 350 return bus_space_read_1(esc->sc_st, esc->sc_sh, reg << 2); 351 } 352 353 void 354 pcscp_write_reg(sc, reg, v) 355 struct ncr53c9x_softc *sc; 356 int reg; 357 u_char v; 358 { 359 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 360 361 bus_space_write_1(esc->sc_st, esc->sc_sh, reg << 2, v); 362 } 363 364 int 365 pcscp_dma_isintr(sc) 366 struct ncr53c9x_softc *sc; 367 { 368 369 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 370 } 371 372 void 373 pcscp_dma_reset(sc) 374 struct ncr53c9x_softc *sc; 375 { 376 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 377 378 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 379 380 esc->sc_active = 0; 381 } 382 383 int 384 pcscp_dma_intr(sc) 385 struct ncr53c9x_softc *sc; 386 { 387 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 388 int trans, resid, i; 389 bus_dmamap_t dmap = esc->sc_xfermap; 390 int datain = esc->sc_datain; 391 u_int32_t dmastat; 392 char *p = NULL; 393 394 dmastat = READ_DMAREG(esc, DMA_STAT); 395 396 if (dmastat & DMASTAT_ERR) { 397 /* XXX not tested... */ 398 WRITE_DMAREG(esc, DMA_CMD, 399 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 400 401 printf("%s: error: DMA error detected; Aborting.\n", 402 sc->sc_dev.dv_xname); 403 bus_dmamap_unload(esc->sc_dmat, dmap); 404 return -1; 405 } 406 407 if (dmastat & DMASTAT_ABT) { 408 /* XXX What should be done? */ 409 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 410 WRITE_DMAREG(esc, DMA_CMD, 411 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 412 esc->sc_active = 0; 413 return 0; 414 } 415 416 /* This is an "assertion" :) */ 417 if (esc->sc_active == 0) 418 panic("pcscp dmaintr: DMA wasn't active"); 419 420 /* DMA has stopped */ 421 422 esc->sc_active = 0; 423 424 if (esc->sc_dmasize == 0) { 425 /* A "Transfer Pad" operation completed */ 426 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 427 NCR_READ_REG(sc, NCR_TCL) | 428 (NCR_READ_REG(sc, NCR_TCM) << 8), 429 NCR_READ_REG(sc, NCR_TCL), 430 NCR_READ_REG(sc, NCR_TCM))); 431 return 0; 432 } 433 434 resid = 0; 435 /* 436 * If a transfer onto the SCSI bus gets interrupted by the device 437 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 438 * as residual since the ESP counter registers get decremented as 439 * bytes are clocked into the FIFO. 440 */ 441 if (!datain && 442 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 443 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 444 } 445 446 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 447 /* 448 * `Terminal count' is off, so read the residue 449 * out of the ESP counter registers. 450 */ 451 if (datain) { 452 resid = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 453 while (resid > 1) 454 resid = 455 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 456 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 457 (datain ? DMACMD_DIR : 0)); 458 459 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 460 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 461 break; 462 463 /* See the below comments... */ 464 if (resid) 465 p = *esc->sc_dmaaddr; 466 } 467 468 resid += (NCR_READ_REG(sc, NCR_TCL) | 469 (NCR_READ_REG(sc, NCR_TCM) << 8) | 470 ((sc->sc_cfg2 & NCRCFG2_FE) 471 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 472 473 if (resid == 0 && esc->sc_dmasize == 65536 && 474 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 475 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 476 resid = 65536; 477 } else { 478 while((dmastat & DMASTAT_DONE) == 0) 479 dmastat = READ_DMAREG(esc, DMA_STAT); 480 } 481 482 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 483 484 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 485 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 486 bus_dmamap_unload(esc->sc_dmat, dmap); 487 488 trans = esc->sc_dmasize - resid; 489 490 /* 491 * From the technical manual notes: 492 * 493 * `In some odd byte conditions, one residual byte will be left 494 * in the SCSI FIFO, and the FIFO flags will never count to 0. 495 * When this happens, the residual byte should be retrieved 496 * via PIO following completion of the BLAST operation.' 497 */ 498 499 if (p) { 500 p += trans; 501 *p = NCR_READ_REG(sc, NCR_FIFO); 502 trans++; 503 } 504 505 if (trans < 0) { /* transferred < 0 ? */ 506 #if 0 507 /* 508 * This situation can happen in perfectly normal operation 509 * if the ESP is reselected while using DMA to select 510 * another target. As such, don't print the warning. 511 */ 512 printf("%s: xfer (%d) > req (%d)\n", 513 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 514 #endif 515 trans = esc->sc_dmasize; 516 } 517 518 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 519 NCR_READ_REG(sc, NCR_TCL), 520 NCR_READ_REG(sc, NCR_TCM), 521 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 522 trans, resid)); 523 524 *esc->sc_dmalen -= trans; 525 *esc->sc_dmaaddr += trans; 526 527 return 0; 528 } 529 530 int 531 pcscp_dma_setup(sc, addr, len, datain, dmasize) 532 struct ncr53c9x_softc *sc; 533 caddr_t *addr; 534 size_t *len; 535 int datain; 536 size_t *dmasize; 537 { 538 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 539 bus_dmamap_t dmap = esc->sc_xfermap; 540 u_int32_t *mdl; 541 int error, nseg, seg; 542 bus_addr_t s_offset, s_addr; 543 long rest, count; 544 545 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 546 547 esc->sc_dmaaddr = addr; 548 esc->sc_dmalen = len; 549 esc->sc_dmasize = *dmasize; 550 esc->sc_datain = datain; 551 552 #ifdef DIAGNOSTIC 553 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 554 panic("pcscp: transfer size too large"); 555 #endif 556 557 /* 558 * No need to set up DMA in `Transfer Pad' operation. 559 * (case of *dmasize == 0) 560 */ 561 if (*dmasize == 0) 562 return 0; 563 564 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 565 *esc->sc_dmalen, NULL, 566 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 567 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 568 ((sc->sc_nexus->xs->xs_control & XS_CTL_DATA_IN) ? 569 BUS_DMA_READ : BUS_DMA_WRITE)); 570 if (error) { 571 printf("%s: unable to load dmamap, error = %d\n", 572 sc->sc_dev.dv_xname, error); 573 return error; 574 } 575 576 /* set transfer length */ 577 WRITE_DMAREG(esc, DMA_STC, *dmasize); 578 579 /* set up MDL */ 580 mdl = esc->sc_mdladdr; 581 nseg = dmap->dm_nsegs; 582 583 /* the first segment is possibly not aligned with 4k MDL boundary */ 584 count = dmap->dm_segs[0].ds_len; 585 s_addr = dmap->dm_segs[0].ds_addr; 586 s_offset = s_addr & MDL_SEG_OFFSET; 587 s_addr -= s_offset; 588 rest = MDL_SEG_SIZE - s_offset; 589 590 /* set the first MDL and offset */ 591 WRITE_DMAREG(esc, DMA_SPA, s_offset); 592 *mdl++ = htole32(s_addr); 593 count -= rest; 594 595 /* rests of the first dmamap segment */ 596 while (count > 0) { 597 s_addr += MDL_SEG_SIZE; 598 *mdl++ = htole32(s_addr); 599 count -= MDL_SEG_SIZE; 600 } 601 602 /* the rest dmamap segments are aligned with 4k boundary */ 603 for (seg = 1; seg < nseg; seg++) { 604 count = dmap->dm_segs[seg].ds_len; 605 s_addr = dmap->dm_segs[seg].ds_addr; 606 607 /* first 4kbyte of each dmamap segment */ 608 *mdl++ = htole32(s_addr); 609 count -= MDL_SEG_SIZE; 610 611 /* trailing contiguous 4k frames of each dmamap segments */ 612 while (count > 0) { 613 s_addr += MDL_SEG_SIZE; 614 *mdl++ = htole32(s_addr); 615 count -= MDL_SEG_SIZE; 616 } 617 } 618 619 return 0; 620 } 621 622 void 623 pcscp_dma_go(sc) 624 struct ncr53c9x_softc *sc; 625 { 626 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 627 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 628 int datain = esc->sc_datain; 629 630 /* No DMA transfer in Transfer Pad operation */ 631 if (esc->sc_dmasize == 0) 632 return; 633 634 /* sync transfer buffer */ 635 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 636 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 637 638 /* sync MDL */ 639 bus_dmamap_sync(esc->sc_dmat, mdldmap, 0, mdldmap->dm_mapsize, 640 BUS_DMASYNC_PREWRITE); 641 642 /* set Starting MDL Address */ 643 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 644 645 /* set DMA command register bits */ 646 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 647 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 648 /* DMACMD_INTE | */ 649 (datain ? DMACMD_DIR : 0)); 650 651 /* issue DMA start command */ 652 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 653 /* DMACMD_INTE | */ 654 (datain ? DMACMD_DIR : 0)); 655 656 esc->sc_active = 1; 657 } 658 659 void 660 pcscp_dma_stop(sc) 661 struct ncr53c9x_softc *sc; 662 { 663 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 664 665 /* dma stop */ 666 /* XXX What should we do here ? */ 667 WRITE_DMAREG(esc, DMA_CMD, 668 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 669 670 esc->sc_active = 0; 671 } 672 673 int 674 pcscp_dma_isactive(sc) 675 struct ncr53c9x_softc *sc; 676 { 677 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 678 679 /* XXX should check esc->sc_active? */ 680 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 681 return 1; 682 return 0; 683 } 684
Indexes created Sun Oct 12 05:10:08 GMT 2025