pcscp.c revision 1.5
1 /* $NetBSD: pcscp.c,v 1.5 1999/09/30 23:04:42 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 42 * written by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp> 43 * 44 * Technical manual available at 45 * http://www.amd.com/products/npd/techdocs/techdocs.html 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 #if BYTE_ORDER == BIG_ENDIAN 56 #include <machine/bswap.h> 57 #endif 58 59 #include <dev/scsipi/scsi_all.h> 60 #include <dev/scsipi/scsipi_all.h> 61 #include <dev/scsipi/scsiconf.h> 62 #include <dev/scsipi/scsi_message.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcidevs.h> 67 68 #include <dev/ic/ncr53c9xreg.h> 69 #include <dev/ic/ncr53c9xvar.h> 70 71 #include <dev/pci/pcscpreg.h> 72 73 #define IO_MAP_REG 0x10 74 #define MEM_MAP_REG 0x14 75 76 struct pcscp_softc { 77 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 78 79 bus_space_tag_t sc_st; /* bus space tag */ 80 bus_space_handle_t sc_sh; /* bus space handle */ 81 void *sc_ih; /* interrupt cookie */ 82 83 bus_dma_tag_t sc_dmat; /* DMA tag */ 84 85 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 86 87 u_int32_t *sc_mdladdr; /* MDL array */ 88 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 89 90 int sc_active; /* DMA state */ 91 int sc_datain; /* DMA Data Direction */ 92 size_t sc_dmasize; /* DMA size */ 93 char **sc_dmaaddr; /* DMA address */ 94 size_t *sc_dmalen; /* DMA length */ 95 }; 96 97 #define READ_DMAREG(sc, reg) \ 98 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 99 #define WRITE_DMAREG(sc, reg, var) \ 100 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 101 102 /* don't have to use MI defines in MD code... */ 103 #undef NCR_READ_REG 104 #define NCR_READ_REG(sc, reg) pcscp_read_reg((sc), (reg)) 105 #undef NCR_WRITE_REG 106 #define NCR_WRITE_REG(sc, reg, val) pcscp_write_reg((sc), (reg), (val)) 107 108 int pcscp_match __P((struct device *, struct cfdata *, void *)); 109 void pcscp_attach __P((struct device *, struct device *, void *)); 110 111 struct cfattach pcscp_ca = { 112 sizeof(struct pcscp_softc), pcscp_match, pcscp_attach 113 }; 114 115 struct scsipi_device pcscp_dev = { 116 NULL, /* Use default error handler */ 117 NULL, /* have a queue, served by this */ 118 NULL, /* have no async handler */ 119 NULL, /* Use default 'done' routine */ 120 }; 121 122 /* 123 * Functions and the switch for the MI code. 124 */ 125 126 u_char pcscp_read_reg __P((struct ncr53c9x_softc *, int)); 127 void pcscp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 128 int pcscp_dma_isintr __P((struct ncr53c9x_softc *)); 129 void pcscp_dma_reset __P((struct ncr53c9x_softc *)); 130 int pcscp_dma_intr __P((struct ncr53c9x_softc *)); 131 int pcscp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 132 size_t *, int, size_t *)); 133 void pcscp_dma_go __P((struct ncr53c9x_softc *)); 134 void pcscp_dma_stop __P((struct ncr53c9x_softc *)); 135 int pcscp_dma_isactive __P((struct ncr53c9x_softc *)); 136 137 struct ncr53c9x_glue pcscp_glue = { 138 pcscp_read_reg, 139 pcscp_write_reg, 140 pcscp_dma_isintr, 141 pcscp_dma_reset, 142 pcscp_dma_intr, 143 pcscp_dma_setup, 144 pcscp_dma_go, 145 pcscp_dma_stop, 146 pcscp_dma_isactive, 147 NULL, /* gl_clear_latched_intr */ 148 }; 149 150 int 151 pcscp_match(parent, match, aux) 152 struct device *parent; 153 struct cfdata *match; 154 void *aux; 155 { 156 struct pci_attach_args *pa = aux; 157 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 158 return 0; 159 160 switch (PCI_PRODUCT(pa->pa_id)) { 161 case PCI_PRODUCT_AMD_PCSCSI_PCI: 162 #if 0 163 case PCI_PRODUCT_AMD_PCNETS_PCI: 164 #endif 165 return 1; 166 } 167 return 0; 168 } 169 170 /* 171 * Attach this instance, and then all the sub-devices 172 */ 173 void 174 pcscp_attach(parent, self, aux) 175 struct device *parent, *self; 176 void *aux; 177 { 178 struct pci_attach_args *pa = aux; 179 struct pcscp_softc *esc = (void *)self; 180 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 181 bus_space_tag_t st, iot, memt; 182 bus_space_handle_t sh, ioh, memh; 183 int ioh_valid, memh_valid; 184 pci_intr_handle_t ih; 185 const char *intrstr; 186 pcireg_t csr; 187 bus_dma_segment_t seg; 188 int error, rseg; 189 190 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 191 PCI_MAPREG_TYPE_IO, 0, 192 &iot, &ioh, NULL, NULL) == 0); 193 #if 0 /* XXX cannot use memory map? */ 194 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 195 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 196 &memt, &memh, NULL, NULL) == 0); 197 #else 198 memh_valid = 0; 199 #endif 200 201 if (memh_valid) { 202 st = memt; 203 sh = memh; 204 } else if (ioh_valid) { 205 st = iot; 206 sh = ioh; 207 } else { 208 printf(": unable to map registers\n"); 209 return; 210 } 211 printf("\n"); 212 213 sc->sc_glue = &pcscp_glue; 214 215 esc->sc_st = st; 216 esc->sc_sh = sh; 217 esc->sc_dmat = pa->pa_dmat; 218 219 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 220 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 221 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 222 223 /* 224 * XXX More of this should be in ncr53c9x_attach(), but 225 * XXX should we really poke around the chip that much in 226 * XXX the MI code? Think about this more... 227 */ 228 229 /* 230 * Set up static configuration info. 231 */ 232 233 /* 234 * XXX should read configuration from EEPROM? 235 * 236 * MI ncr53c9x driver does not support configuration 237 * per each target device, though... 238 */ 239 sc->sc_id = 7; 240 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 241 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 242 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 243 sc->sc_rev = NCR_VARIANT_AM53C974; 244 sc->sc_features = NCR_F_FASTSCSI; 245 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 246 sc->sc_freq = 40; /* MHz */ 247 248 /* 249 * XXX minsync and maxxfer _should_ be set up in MI code, 250 * XXX but it appears to have some dependency on what sort 251 * XXX of DMA we're hooked up to, etc. 252 */ 253 254 /* 255 * This is the value used to start sync negotiations 256 * Note that the NCR register "SYNCTP" is programmed 257 * in "clocks per byte", and has a minimum value of 4. 258 * The SCSI period used in negotiation is one-fourth 259 * of the time (in nanoseconds) needed to transfer one byte. 260 * Since the chip's clock is given in MHz, we have the following 261 * formula: 4 * period = (1000 / freq) * 4 262 */ 263 264 sc->sc_minsync = 1000 / sc->sc_freq; 265 266 /* Really no limit, but since we want to fit into the TCR... */ 267 sc->sc_maxxfer = 16 * 1024 * 1024; 268 269 /* map and establish interrupt */ 270 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 271 pa->pa_intrline, &ih)) { 272 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 273 return; 274 } 275 276 intrstr = pci_intr_string(pa->pa_pc, ih); 277 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 278 (int (*)(void *))ncr53c9x_intr, esc); 279 if (esc->sc_ih == NULL) { 280 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 281 if (intrstr != NULL) 282 printf(" at %s", intrstr); 283 printf("\n"); 284 return; 285 } 286 if (intrstr != NULL) 287 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 288 intrstr); 289 290 /* 291 * Create the DMA maps for the data transfers. 292 */ 293 294 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 295 #define MDL_SEG_OFFSET 0x0FFF 296 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 297 298 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MAXPHYS, 0, 299 BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 300 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname); 301 return; 302 } 303 304 /* 305 * Allocate and map memory for the MDL. 306 */ 307 308 if ((error = bus_dmamem_alloc(esc->sc_dmat, 309 sizeof(u_int32_t) * MDL_SIZE, NBPG, 0, &seg, 1, &rseg, 310 BUS_DMA_NOWAIT)) != 0) { 311 printf("%s: unable to allocate memory for the MDL, " 312 "error = %d\n", sc->sc_dev.dv_xname, error); 313 return; 314 } 315 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 316 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 317 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 318 printf("%s: unable to map the MDL memory, error = %d\n", 319 sc->sc_dev.dv_xname, error); 320 return; 321 } 322 if ((error = bus_dmamap_create(esc->sc_dmat, 323 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 324 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 325 printf("%s: unable to map_create for the MDL, error = %d\n", 326 sc->sc_dev.dv_xname, error); 327 return; 328 } 329 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 330 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 331 NULL, BUS_DMA_NOWAIT)) != 0) { 332 printf("%s: unable to load for the MDL, error = %d\n", 333 sc->sc_dev.dv_xname, error); 334 return; 335 } 336 337 /* Do the common parts of attachment. */ 338 printf("%s", sc->sc_dev.dv_xname); 339 340 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 341 sc->sc_adapter.scsipi_minphys = minphys; 342 343 ncr53c9x_attach(sc, &pcscp_dev); 344 345 /* Turn on target selection using the `dma' method */ 346 ncr53c9x_dmaselect = 1; 347 } 348 349 /* 350 * Glue functions. 351 */ 352 353 u_char 354 pcscp_read_reg(sc, reg) 355 struct ncr53c9x_softc *sc; 356 int reg; 357 { 358 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 359 360 return bus_space_read_1(esc->sc_st, esc->sc_sh, reg << 2); 361 } 362 363 void 364 pcscp_write_reg(sc, reg, v) 365 struct ncr53c9x_softc *sc; 366 int reg; 367 u_char v; 368 { 369 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 370 371 bus_space_write_1(esc->sc_st, esc->sc_sh, reg << 2, v); 372 } 373 374 int 375 pcscp_dma_isintr(sc) 376 struct ncr53c9x_softc *sc; 377 { 378 379 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 380 } 381 382 void 383 pcscp_dma_reset(sc) 384 struct ncr53c9x_softc *sc; 385 { 386 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 387 388 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 389 390 esc->sc_active = 0; 391 } 392 393 int 394 pcscp_dma_intr(sc) 395 struct ncr53c9x_softc *sc; 396 { 397 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 398 int trans, resid, i; 399 bus_dmamap_t dmap = esc->sc_xfermap; 400 int datain = esc->sc_datain; 401 u_int32_t dmastat; 402 char *p = NULL; 403 404 dmastat = READ_DMAREG(esc, DMA_STAT); 405 406 if (dmastat & DMASTAT_ERR) { 407 /* XXX not tested... */ 408 WRITE_DMAREG(esc, DMA_CMD, DMACMD_ABORT | 409 (datain ? DMACMD_DIR : 0)); 410 411 printf("%s: error: DMA error detected; Aborting.\n", 412 sc->sc_dev.dv_xname); 413 bus_dmamap_unload(esc->sc_dmat, dmap); 414 return -1; 415 } 416 417 if (dmastat & DMASTAT_ABT) { 418 /* XXX What should be done? */ 419 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 420 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | 421 (datain ? DMACMD_DIR : 0)); 422 esc->sc_active = 0; 423 return 0; 424 } 425 426 /* This is an "assertion" :) */ 427 if (esc->sc_active == 0) 428 panic("pcscp dmaintr: DMA wasn't active"); 429 430 /* DMA has stopped */ 431 432 esc->sc_active = 0; 433 434 if (esc->sc_dmasize == 0) { 435 /* A "Transfer Pad" operation completed */ 436 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 437 NCR_READ_REG(sc, NCR_TCL) | 438 (NCR_READ_REG(sc, NCR_TCM) << 8), 439 NCR_READ_REG(sc, NCR_TCL), 440 NCR_READ_REG(sc, NCR_TCM))); 441 return 0; 442 } 443 444 resid = 0; 445 /* 446 * If a transfer onto the SCSI bus gets interrupted by the device 447 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 448 * as residual since the ESP counter registers get decremented as 449 * bytes are clocked into the FIFO. 450 */ 451 if (!datain && 452 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 453 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 454 } 455 456 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 457 /* 458 * `Terminal count' is off, so read the residue 459 * out of the ESP counter registers. 460 */ 461 if (datain) { 462 resid = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 463 while (resid > 1) 464 resid = NCR_READ_REG(sc, NCR_FFLAG) & 465 NCRFIFO_FF; 466 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 467 (datain ? DMACMD_DIR : 0)); 468 469 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 470 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 471 break; 472 473 /* See the below comments... */ 474 if (resid) 475 p = *esc->sc_dmaaddr; 476 } 477 478 resid += (NCR_READ_REG(sc, NCR_TCL) | 479 (NCR_READ_REG(sc, NCR_TCM) << 8) | 480 ((sc->sc_cfg2 & NCRCFG2_FE) 481 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 482 483 if (resid == 0 && esc->sc_dmasize == 65536 && 484 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 485 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 486 resid = 65536; 487 } else { 488 while((dmastat & DMASTAT_DONE) == 0) 489 dmastat = READ_DMAREG(esc, DMA_STAT); 490 } 491 492 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 493 494 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 495 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 496 bus_dmamap_unload(esc->sc_dmat, dmap); 497 498 trans = esc->sc_dmasize - resid; 499 500 /* 501 * From the technical manual notes: 502 * 503 * `In some odd byte conditions, one residual byte will be left 504 * in the SCSI FIFO, and the FIFO flags will never count to 0. 505 * When this happens, the residual byte should be retrieved 506 * via PIO following completion of the BLAST operation.' 507 */ 508 509 if (p) { 510 p += trans; 511 *p = NCR_READ_REG(sc, NCR_FIFO); 512 trans++; 513 } 514 515 if (trans < 0) { /* transferred < 0 ? */ 516 #if 0 517 /* 518 * This situation can happen in perfectly normal operation 519 * if the ESP is reselected while using DMA to select 520 * another target. As such, don't print the warning. 521 */ 522 printf("%s: xfer (%d) > req (%d)\n", 523 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 524 #endif 525 trans = esc->sc_dmasize; 526 } 527 528 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 529 NCR_READ_REG(sc, NCR_TCL), 530 NCR_READ_REG(sc, NCR_TCM), 531 (sc->sc_cfg2 & NCRCFG2_FE) 532 ? NCR_READ_REG(sc, NCR_TCH) : 0, 533 trans, resid)); 534 535 *esc->sc_dmalen -= trans; 536 *esc->sc_dmaaddr += trans; 537 538 return 0; 539 } 540 541 int 542 pcscp_dma_setup(sc, addr, len, datain, dmasize) 543 struct ncr53c9x_softc *sc; 544 caddr_t *addr; 545 size_t *len; 546 int datain; 547 size_t *dmasize; 548 { 549 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 550 bus_dmamap_t dmap = esc->sc_xfermap; 551 u_int32_t *mdl; 552 int error, nseg, seg; 553 bus_addr_t s_offset, s_addr; 554 long rest, count; 555 556 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 557 558 esc->sc_dmaaddr = addr; 559 esc->sc_dmalen = len; 560 esc->sc_dmasize = *dmasize; 561 esc->sc_datain = datain; 562 563 #ifdef DIAGNOSTIC 564 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 565 panic("pcscp: transfer size too large"); 566 #endif 567 568 /* 569 * No need to set up DMA in `Transfer Pad' operation. 570 * (case of *dmasize == 0) 571 */ 572 if (*dmasize == 0) 573 return 0; 574 575 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 576 *esc->sc_dmalen, NULL, 577 sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP ? 578 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 579 if (error) { 580 printf("%s: unable to load dmamap, error = %d\n", 581 sc->sc_dev.dv_xname, error); 582 return error; 583 } 584 585 /* set transfer length */ 586 WRITE_DMAREG(esc, DMA_STC, *dmasize); 587 588 /* set up MDL */ 589 mdl = esc->sc_mdladdr; 590 nseg = dmap->dm_nsegs; 591 seg = 0; 592 593 /* the first segment is possibly not aligned with 4k MDL boundary */ 594 count = dmap->dm_segs[seg].ds_len; 595 s_offset = dmap->dm_segs[seg].ds_addr & MDL_SEG_OFFSET; 596 s_addr = dmap->dm_segs[seg].ds_addr - s_offset; 597 rest = MDL_SEG_SIZE - s_offset; 598 599 #if BYTE_ORDER == BIG_ENDIAN 600 #define htopci(addr) bswap32(addr) 601 #else 602 #define htopci(addr) (addr) 603 #endif 604 605 /* set the first MDL and offset */ 606 WRITE_DMAREG(esc, DMA_SPA, s_offset); 607 *mdl++ = htopci(s_addr); 608 count -= rest; 609 610 /* rests of the first dmamap segment */ 611 while (count > 0) { 612 s_addr += MDL_SEG_SIZE; 613 *mdl++ = htopci(s_addr); 614 count -= MDL_SEG_SIZE; 615 } 616 617 /* the rest dmamap segments are aligned with 4k boundary */ 618 for (seg = 1; seg < nseg; seg++) { 619 count = dmap->dm_segs[seg].ds_len; 620 s_addr = dmap->dm_segs[seg].ds_addr; 621 622 /* first 4kbyte of each dmamap segment */ 623 *mdl++ = htopci(s_addr); 624 count -= MDL_SEG_SIZE; 625 626 /* trailing contiguous 4k frames of each dmamap segments */ 627 while (count > 0) { 628 s_addr += MDL_SEG_SIZE; 629 *mdl++ = htopci(s_addr); 630 count -= MDL_SEG_SIZE; 631 } 632 } 633 634 #undef htopci 635 636 return 0; 637 } 638 639 void 640 pcscp_dma_go(sc) 641 struct ncr53c9x_softc *sc; 642 { 643 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 644 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 645 int datain = esc->sc_datain; 646 647 /* No DMA transfer in Transfer Pad operation */ 648 if (esc->sc_dmasize == 0) 649 return; 650 651 /* sync transfer buffer */ 652 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 653 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 654 655 /* sync MDL */ 656 bus_dmamap_sync(esc->sc_dmat, mdldmap, 0, mdldmap->dm_mapsize, 657 BUS_DMASYNC_PREWRITE); 658 659 /* set Starting MDL Address */ 660 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 661 662 /* set DMA command register bits */ 663 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 664 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 665 /* DMACMD_INTE | */ 666 (datain ? DMACMD_DIR : 0)); 667 668 /* issue DMA start command */ 669 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 670 /* DMACMD_INTE | */ 671 (datain ? DMACMD_DIR : 0)); 672 673 esc->sc_active = 1; 674 } 675 676 void 677 pcscp_dma_stop(sc) 678 struct ncr53c9x_softc *sc; 679 { 680 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 681 682 /* dma stop */ 683 /* XXX What should we do here ? */ 684 WRITE_DMAREG(esc, DMA_CMD, DMACMD_ABORT | 685 ( esc->sc_datain ? DMACMD_DIR : 0)); 686 687 esc->sc_active = 0; 688 } 689 690 int 691 pcscp_dma_isactive(sc) 692 struct ncr53c9x_softc *sc; 693 { 694 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 695 696 /* XXX should check esc->sc_active? */ 697 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 698 return 1; 699 return 0; 700 } 701
Indexes created Tue Sep 23 07:09:52 GMT 2025