pcscp.c revision 1.6 1 /* $NetBSD: pcscp.c,v 1.6 1999/12/12 02:50:40 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center; Izumi Tsutsui.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI)
42 * written by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp>
43 *
44 * Technical manual available at
45 * http://www.amd.com/products/npd/techdocs/techdocs.html
46 */
47
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/device.h>
51 #include <sys/buf.h>
52
53 #include <machine/bus.h>
54 #include <machine/intr.h>
55 #include <machine/endian.h>
56
57 #include <dev/scsipi/scsi_all.h>
58 #include <dev/scsipi/scsipi_all.h>
59 #include <dev/scsipi/scsiconf.h>
60 #include <dev/scsipi/scsi_message.h>
61
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcivar.h>
64 #include <dev/pci/pcidevs.h>
65
66 #include <dev/ic/ncr53c9xreg.h>
67 #include <dev/ic/ncr53c9xvar.h>
68
69 #include <dev/pci/pcscpreg.h>
70
71 #define IO_MAP_REG 0x10
72 #define MEM_MAP_REG 0x14
73
74 struct pcscp_softc {
75 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
76
77 bus_space_tag_t sc_st; /* bus space tag */
78 bus_space_handle_t sc_sh; /* bus space handle */
79 void *sc_ih; /* interrupt cookie */
80
81 bus_dma_tag_t sc_dmat; /* DMA tag */
82
83 bus_dmamap_t sc_xfermap; /* DMA map for transfers */
84
85 u_int32_t *sc_mdladdr; /* MDL array */
86 bus_dmamap_t sc_mdldmap; /* MDL DMA map */
87
88 int sc_active; /* DMA state */
89 int sc_datain; /* DMA Data Direction */
90 size_t sc_dmasize; /* DMA size */
91 char **sc_dmaaddr; /* DMA address */
92 size_t *sc_dmalen; /* DMA length */
93 };
94
95 #define READ_DMAREG(sc, reg) \
96 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
97 #define WRITE_DMAREG(sc, reg, var) \
98 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var))
99
100 /* don't have to use MI defines in MD code... */
101 #undef NCR_READ_REG
102 #define NCR_READ_REG(sc, reg) pcscp_read_reg((sc), (reg))
103 #undef NCR_WRITE_REG
104 #define NCR_WRITE_REG(sc, reg, val) pcscp_write_reg((sc), (reg), (val))
105
106 int pcscp_match __P((struct device *, struct cfdata *, void *));
107 void pcscp_attach __P((struct device *, struct device *, void *));
108
109 struct cfattach pcscp_ca = {
110 sizeof(struct pcscp_softc), pcscp_match, pcscp_attach
111 };
112
113 struct scsipi_device pcscp_dev = {
114 NULL, /* Use default error handler */
115 NULL, /* have a queue, served by this */
116 NULL, /* have no async handler */
117 NULL, /* Use default 'done' routine */
118 };
119
120 /*
121 * Functions and the switch for the MI code.
122 */
123
124 u_char pcscp_read_reg __P((struct ncr53c9x_softc *, int));
125 void pcscp_write_reg __P((struct ncr53c9x_softc *, int, u_char));
126 int pcscp_dma_isintr __P((struct ncr53c9x_softc *));
127 void pcscp_dma_reset __P((struct ncr53c9x_softc *));
128 int pcscp_dma_intr __P((struct ncr53c9x_softc *));
129 int pcscp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
130 size_t *, int, size_t *));
131 void pcscp_dma_go __P((struct ncr53c9x_softc *));
132 void pcscp_dma_stop __P((struct ncr53c9x_softc *));
133 int pcscp_dma_isactive __P((struct ncr53c9x_softc *));
134
135 struct ncr53c9x_glue pcscp_glue = {
136 pcscp_read_reg,
137 pcscp_write_reg,
138 pcscp_dma_isintr,
139 pcscp_dma_reset,
140 pcscp_dma_intr,
141 pcscp_dma_setup,
142 pcscp_dma_go,
143 pcscp_dma_stop,
144 pcscp_dma_isactive,
145 NULL, /* gl_clear_latched_intr */
146 };
147
148 int
149 pcscp_match(parent, match, aux)
150 struct device *parent;
151 struct cfdata *match;
152 void *aux;
153 {
154 struct pci_attach_args *pa = aux;
155 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD)
156 return 0;
157
158 switch (PCI_PRODUCT(pa->pa_id)) {
159 case PCI_PRODUCT_AMD_PCSCSI_PCI:
160 #if 0
161 case PCI_PRODUCT_AMD_PCNETS_PCI:
162 #endif
163 return 1;
164 }
165 return 0;
166 }
167
168 /*
169 * Attach this instance, and then all the sub-devices
170 */
171 void
172 pcscp_attach(parent, self, aux)
173 struct device *parent, *self;
174 void *aux;
175 {
176 struct pci_attach_args *pa = aux;
177 struct pcscp_softc *esc = (void *)self;
178 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
179 bus_space_tag_t st, iot, memt;
180 bus_space_handle_t sh, ioh, memh;
181 int ioh_valid, memh_valid;
182 pci_intr_handle_t ih;
183 const char *intrstr;
184 pcireg_t csr;
185 bus_dma_segment_t seg;
186 int error, rseg;
187
188 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG,
189 PCI_MAPREG_TYPE_IO, 0,
190 &iot, &ioh, NULL, NULL) == 0);
191 #if 0 /* XXX cannot use memory map? */
192 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG,
193 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
194 &memt, &memh, NULL, NULL) == 0);
195 #else
196 memh_valid = 0;
197 #endif
198
199 if (memh_valid) {
200 st = memt;
201 sh = memh;
202 } else if (ioh_valid) {
203 st = iot;
204 sh = ioh;
205 } else {
206 printf(": unable to map registers\n");
207 return;
208 }
209 printf("\n");
210
211 sc->sc_glue = &pcscp_glue;
212
213 esc->sc_st = st;
214 esc->sc_sh = sh;
215 esc->sc_dmat = pa->pa_dmat;
216
217 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
218 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
219 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
220
221 /*
222 * XXX More of this should be in ncr53c9x_attach(), but
223 * XXX should we really poke around the chip that much in
224 * XXX the MI code? Think about this more...
225 */
226
227 /*
228 * Set up static configuration info.
229 */
230
231 /*
232 * XXX should read configuration from EEPROM?
233 *
234 * MI ncr53c9x driver does not support configuration
235 * per each target device, though...
236 */
237 sc->sc_id = 7;
238 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
239 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
240 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK;
241 sc->sc_rev = NCR_VARIANT_AM53C974;
242 sc->sc_features = NCR_F_FASTSCSI;
243 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI;
244 sc->sc_freq = 40; /* MHz */
245
246 /*
247 * XXX minsync and maxxfer _should_ be set up in MI code,
248 * XXX but it appears to have some dependency on what sort
249 * XXX of DMA we're hooked up to, etc.
250 */
251
252 /*
253 * This is the value used to start sync negotiations
254 * Note that the NCR register "SYNCTP" is programmed
255 * in "clocks per byte", and has a minimum value of 4.
256 * The SCSI period used in negotiation is one-fourth
257 * of the time (in nanoseconds) needed to transfer one byte.
258 * Since the chip's clock is given in MHz, we have the following
259 * formula: 4 * period = (1000 / freq) * 4
260 */
261
262 sc->sc_minsync = 1000 / sc->sc_freq;
263
264 /* Really no limit, but since we want to fit into the TCR... */
265 sc->sc_maxxfer = 16 * 1024 * 1024;
266
267 /* map and establish interrupt */
268 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
269 pa->pa_intrline, &ih)) {
270 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
271 return;
272 }
273
274 intrstr = pci_intr_string(pa->pa_pc, ih);
275 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
276 (int (*)(void *))ncr53c9x_intr, esc);
277 if (esc->sc_ih == NULL) {
278 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname);
279 if (intrstr != NULL)
280 printf(" at %s", intrstr);
281 printf("\n");
282 return;
283 }
284 if (intrstr != NULL)
285 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname,
286 intrstr);
287
288 /*
289 * Create the DMA maps for the data transfers.
290 */
291
292 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */
293 #define MDL_SEG_OFFSET 0x0FFF
294 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */
295
296 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MAXPHYS, 0,
297 BUS_DMA_NOWAIT, &esc->sc_xfermap)) {
298 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname);
299 return;
300 }
301
302 /*
303 * Allocate and map memory for the MDL.
304 */
305
306 if ((error = bus_dmamem_alloc(esc->sc_dmat,
307 sizeof(u_int32_t) * MDL_SIZE, NBPG, 0, &seg, 1, &rseg,
308 BUS_DMA_NOWAIT)) != 0) {
309 printf("%s: unable to allocate memory for the MDL, "
310 "error = %d\n", sc->sc_dev.dv_xname, error);
311 return;
312 }
313 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg,
314 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr,
315 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
316 printf("%s: unable to map the MDL memory, error = %d\n",
317 sc->sc_dev.dv_xname, error);
318 return;
319 }
320 if ((error = bus_dmamap_create(esc->sc_dmat,
321 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE,
322 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) {
323 printf("%s: unable to map_create for the MDL, error = %d\n",
324 sc->sc_dev.dv_xname, error);
325 return;
326 }
327 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap,
328 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE,
329 NULL, BUS_DMA_NOWAIT)) != 0) {
330 printf("%s: unable to load for the MDL, error = %d\n",
331 sc->sc_dev.dv_xname, error);
332 return;
333 }
334
335 /* Do the common parts of attachment. */
336 printf("%s", sc->sc_dev.dv_xname);
337
338 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd;
339 sc->sc_adapter.scsipi_minphys = minphys;
340
341 ncr53c9x_attach(sc, &pcscp_dev);
342
343 /* Turn on target selection using the `dma' method */
344 ncr53c9x_dmaselect = 1;
345 }
346
347 /*
348 * Glue functions.
349 */
350
351 u_char
352 pcscp_read_reg(sc, reg)
353 struct ncr53c9x_softc *sc;
354 int reg;
355 {
356 struct pcscp_softc *esc = (struct pcscp_softc *)sc;
357
358 return bus_space_read_1(esc->sc_st, esc->sc_sh, reg << 2);
359 }
360
361 void
362 pcscp_write_reg(sc, reg, v)
363 struct ncr53c9x_softc *sc;
364 int reg;
365 u_char v;
366 {
367 struct pcscp_softc *esc = (struct pcscp_softc *)sc;
368
369 bus_space_write_1(esc->sc_st, esc->sc_sh, reg << 2, v);
370 }
371
372 int
373 pcscp_dma_isintr(sc)
374 struct ncr53c9x_softc *sc;
375 {
376
377 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT;
378 }
379
380 void
381 pcscp_dma_reset(sc)
382 struct ncr53c9x_softc *sc;
383 {
384 struct pcscp_softc *esc = (struct pcscp_softc *)sc;
385
386 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE);
387
388 esc->sc_active = 0;
389 }
390
391 int
392 pcscp_dma_intr(sc)
393 struct ncr53c9x_softc *sc;
394 {
395 struct pcscp_softc *esc = (struct pcscp_softc *)sc;
396 int trans, resid, i;
397 bus_dmamap_t dmap = esc->sc_xfermap;
398 int datain = esc->sc_datain;
399 u_int32_t dmastat;
400 char *p = NULL;
401
402 dmastat = READ_DMAREG(esc, DMA_STAT);
403
404 if (dmastat & DMASTAT_ERR) {
405 /* XXX not tested... */
406 WRITE_DMAREG(esc, DMA_CMD, DMACMD_ABORT |
407 (datain ? DMACMD_DIR : 0));
408
409 printf("%s: error: DMA error detected; Aborting.\n",
410 sc->sc_dev.dv_xname);
411 bus_dmamap_unload(esc->sc_dmat, dmap);
412 return -1;
413 }
414
415 if (dmastat & DMASTAT_ABT) {
416 /* XXX What should be done? */
417 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname);
418 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE |
419 (datain ? DMACMD_DIR : 0));
420 esc->sc_active = 0;
421 return 0;
422 }
423
424 /* This is an "assertion" :) */
425 if (esc->sc_active == 0)
426 panic("pcscp dmaintr: DMA wasn't active");
427
428 /* DMA has stopped */
429
430 esc->sc_active = 0;
431
432 if (esc->sc_dmasize == 0) {
433 /* A "Transfer Pad" operation completed */
434 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
435 NCR_READ_REG(sc, NCR_TCL) |
436 (NCR_READ_REG(sc, NCR_TCM) << 8),
437 NCR_READ_REG(sc, NCR_TCL),
438 NCR_READ_REG(sc, NCR_TCM)));
439 return 0;
440 }
441
442 resid = 0;
443 /*
444 * If a transfer onto the SCSI bus gets interrupted by the device
445 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts
446 * as residual since the ESP counter registers get decremented as
447 * bytes are clocked into the FIFO.
448 */
449 if (!datain &&
450 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
451 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid));
452 }
453
454 if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
455 /*
456 * `Terminal count' is off, so read the residue
457 * out of the ESP counter registers.
458 */
459 if (datain) {
460 resid = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF;
461 while (resid > 1)
462 resid = NCR_READ_REG(sc, NCR_FFLAG) &
463 NCRFIFO_FF;
464 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL |
465 (datain ? DMACMD_DIR : 0));
466
467 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */
468 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP)
469 break;
470
471 /* See the below comments... */
472 if (resid)
473 p = *esc->sc_dmaaddr;
474 }
475
476 resid += (NCR_READ_REG(sc, NCR_TCL) |
477 (NCR_READ_REG(sc, NCR_TCM) << 8) |
478 ((sc->sc_cfg2 & NCRCFG2_FE)
479 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0));
480
481 if (resid == 0 && esc->sc_dmasize == 65536 &&
482 (sc->sc_cfg2 & NCRCFG2_FE) == 0)
483 /* A transfer of 64K is encoded as `TCL=TCM=0' */
484 resid = 65536;
485 } else {
486 while((dmastat & DMASTAT_DONE) == 0)
487 dmastat = READ_DMAREG(esc, DMA_STAT);
488 }
489
490 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0));
491
492 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize,
493 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
494 bus_dmamap_unload(esc->sc_dmat, dmap);
495
496 trans = esc->sc_dmasize - resid;
497
498 /*
499 * From the technical manual notes:
500 *
501 * `In some odd byte conditions, one residual byte will be left
502 * in the SCSI FIFO, and the FIFO flags will never count to 0.
503 * When this happens, the residual byte should be retrieved
504 * via PIO following completion of the BLAST operation.'
505 */
506
507 if (p) {
508 p += trans;
509 *p = NCR_READ_REG(sc, NCR_FIFO);
510 trans++;
511 }
512
513 if (trans < 0) { /* transferred < 0 ? */
514 #if 0
515 /*
516 * This situation can happen in perfectly normal operation
517 * if the ESP is reselected while using DMA to select
518 * another target. As such, don't print the warning.
519 */
520 printf("%s: xfer (%d) > req (%d)\n",
521 sc->sc_dev.dv_xname, trans, esc->sc_dmasize);
522 #endif
523 trans = esc->sc_dmasize;
524 }
525
526 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
527 NCR_READ_REG(sc, NCR_TCL),
528 NCR_READ_REG(sc, NCR_TCM),
529 (sc->sc_cfg2 & NCRCFG2_FE)
530 ? NCR_READ_REG(sc, NCR_TCH) : 0,
531 trans, resid));
532
533 *esc->sc_dmalen -= trans;
534 *esc->sc_dmaaddr += trans;
535
536 return 0;
537 }
538
539 int
540 pcscp_dma_setup(sc, addr, len, datain, dmasize)
541 struct ncr53c9x_softc *sc;
542 caddr_t *addr;
543 size_t *len;
544 int datain;
545 size_t *dmasize;
546 {
547 struct pcscp_softc *esc = (struct pcscp_softc *)sc;
548 bus_dmamap_t dmap = esc->sc_xfermap;
549 u_int32_t *mdl;
550 int error, nseg, seg;
551 bus_addr_t s_offset, s_addr;
552 long rest, count;
553
554 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0));
555
556 esc->sc_dmaaddr = addr;
557 esc->sc_dmalen = len;
558 esc->sc_dmasize = *dmasize;
559 esc->sc_datain = datain;
560
561 #ifdef DIAGNOSTIC
562 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE)
563 panic("pcscp: transfer size too large");
564 #endif
565
566 /*
567 * No need to set up DMA in `Transfer Pad' operation.
568 * (case of *dmasize == 0)
569 */
570 if (*dmasize == 0)
571 return 0;
572
573 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr,
574 *esc->sc_dmalen, NULL,
575 sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP ?
576 BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
577 if (error) {
578 printf("%s: unable to load dmamap, error = %d\n",
579 sc->sc_dev.dv_xname, error);
580 return error;
581 }
582
583 /* set transfer length */
584 WRITE_DMAREG(esc, DMA_STC, *dmasize);
585
586 /* set up MDL */
587 mdl = esc->sc_mdladdr;
588 nseg = dmap->dm_nsegs;
589 seg = 0;
590
591 /* the first segment is possibly not aligned with 4k MDL boundary */
592 count = dmap->dm_segs[seg].ds_len;
593 s_offset = dmap->dm_segs[seg].ds_addr & MDL_SEG_OFFSET;
594 s_addr = dmap->dm_segs[seg].ds_addr - s_offset;
595 rest = MDL_SEG_SIZE - s_offset;
596
597 /* set the first MDL and offset */
598 WRITE_DMAREG(esc, DMA_SPA, s_offset);
599 *mdl++ = htole32(s_addr);
600 count -= rest;
601
602 /* rests of the first dmamap segment */
603 while (count > 0) {
604 s_addr += MDL_SEG_SIZE;
605 *mdl++ = htole32(s_addr);
606 count -= MDL_SEG_SIZE;
607 }
608
609 /* the rest dmamap segments are aligned with 4k boundary */
610 for (seg = 1; seg < nseg; seg++) {
611 count = dmap->dm_segs[seg].ds_len;
612 s_addr = dmap->dm_segs[seg].ds_addr;
613
614 /* first 4kbyte of each dmamap segment */
615 *mdl++ = htole32(s_addr);
616 count -= MDL_SEG_SIZE;
617
618 /* trailing contiguous 4k frames of each dmamap segments */
619 while (count > 0) {
620 s_addr += MDL_SEG_SIZE;
621 *mdl++ = htole32(s_addr);
622 count -= MDL_SEG_SIZE;
623 }
624 }
625
626 return 0;
627 }
628
629 void
630 pcscp_dma_go(sc)
631 struct ncr53c9x_softc *sc;
632 {
633 struct pcscp_softc *esc = (struct pcscp_softc *)sc;
634 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap;
635 int datain = esc->sc_datain;
636
637 /* No DMA transfer in Transfer Pad operation */
638 if (esc->sc_dmasize == 0)
639 return;
640
641 /* sync transfer buffer */
642 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize,
643 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
644
645 /* sync MDL */
646 bus_dmamap_sync(esc->sc_dmat, mdldmap, 0, mdldmap->dm_mapsize,
647 BUS_DMASYNC_PREWRITE);
648
649 /* set Starting MDL Address */
650 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr);
651
652 /* set DMA command register bits */
653 /* XXX DMA Transfer Interrupt Enable bit is broken? */
654 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL |
655 /* DMACMD_INTE | */
656 (datain ? DMACMD_DIR : 0));
657
658 /* issue DMA start command */
659 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL |
660 /* DMACMD_INTE | */
661 (datain ? DMACMD_DIR : 0));
662
663 esc->sc_active = 1;
664 }
665
666 void
667 pcscp_dma_stop(sc)
668 struct ncr53c9x_softc *sc;
669 {
670 struct pcscp_softc *esc = (struct pcscp_softc *)sc;
671
672 /* dma stop */
673 /* XXX What should we do here ? */
674 WRITE_DMAREG(esc, DMA_CMD, DMACMD_ABORT |
675 ( esc->sc_datain ? DMACMD_DIR : 0));
676
677 esc->sc_active = 0;
678 }
679
680 int
681 pcscp_dma_isactive(sc)
682 struct ncr53c9x_softc *sc;
683 {
684 struct pcscp_softc *esc = (struct pcscp_softc *)sc;
685
686 /* XXX should check esc->sc_active? */
687 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE)
688 return 1;
689 return 0;
690 }
691