pdcide.c revision 1.1
1 /* $NetBSD: pdcide.c,v 1.1 2003/10/08 11:51:59 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_pdc202xx_reg.h> 43 44 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 45 void pdc202xx_setup_channel __P((struct channel_softc*)); 46 void pdc20268_setup_channel __P((struct channel_softc*)); 47 int pdc202xx_pci_intr __P((void *)); 48 int pdc20265_pci_intr __P((void *)); 49 static void pdc20262_dma_start __P((void*, int, int)); 50 static int pdc20262_dma_finish __P((void*, int, int, int)); 51 52 int pdcide_match __P((struct device *, struct cfdata *, void *)); 53 void pdcide_attach __P((struct device *, struct device *, void *)); 54 55 CFATTACH_DECL(pdcide, sizeof(struct pciide_softc), 56 pdcide_match, pdcide_attach, NULL, NULL); 57 58 const struct pciide_product_desc pciide_promise_products[] = { 59 { PCI_PRODUCT_PROMISE_ULTRA33, 60 IDE_PCI_CLASS_OVERRIDE, 61 "Promise Ultra33/ATA Bus Master IDE Accelerator", 62 pdc202xx_chip_map, 63 }, 64 { PCI_PRODUCT_PROMISE_ULTRA66, 65 IDE_PCI_CLASS_OVERRIDE, 66 "Promise Ultra66/ATA Bus Master IDE Accelerator", 67 pdc202xx_chip_map, 68 }, 69 { PCI_PRODUCT_PROMISE_ULTRA100, 70 IDE_PCI_CLASS_OVERRIDE, 71 "Promise Ultra100/ATA Bus Master IDE Accelerator", 72 pdc202xx_chip_map, 73 }, 74 { PCI_PRODUCT_PROMISE_ULTRA100X, 75 IDE_PCI_CLASS_OVERRIDE, 76 "Promise Ultra100/ATA Bus Master IDE Accelerator", 77 pdc202xx_chip_map, 78 }, 79 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 80 IDE_PCI_CLASS_OVERRIDE, 81 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 82 pdc202xx_chip_map, 83 }, 84 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 85 IDE_PCI_CLASS_OVERRIDE, 86 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 87 pdc202xx_chip_map, 88 }, 89 { PCI_PRODUCT_PROMISE_ULTRA133, 90 IDE_PCI_CLASS_OVERRIDE, 91 "Promise Ultra133/ATA Bus Master IDE Accelerator", 92 pdc202xx_chip_map, 93 }, 94 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 95 IDE_PCI_CLASS_OVERRIDE, 96 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 97 pdc202xx_chip_map, 98 }, 99 { PCI_PRODUCT_PROMISE_MBULTRA133, 100 IDE_PCI_CLASS_OVERRIDE, 101 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 102 pdc202xx_chip_map, 103 }, 104 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 105 IDE_PCI_CLASS_OVERRIDE, 106 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 107 pdc202xx_chip_map, 108 }, 109 { PCI_PRODUCT_PROMISE_FASTTRAK133LITE, 110 IDE_PCI_CLASS_OVERRIDE, 111 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 112 pdc202xx_chip_map, 113 }, 114 { PCI_PRODUCT_PROMISE_SATA150TX2PLUS, 115 IDE_PCI_CLASS_OVERRIDE, 116 "Promise Serial ATA/150 TX2plus Bus Master IDE Accelerator", 117 pdc202xx_chip_map, 118 }, 119 { 0, 120 0, 121 NULL, 122 NULL 123 } 124 }; 125 126 int 127 pdcide_match(parent, match, aux) 128 struct device *parent; 129 struct cfdata *match; 130 void *aux; 131 { 132 struct pci_attach_args *pa = aux; 133 134 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 135 if (pciide_lookup_product(pa->pa_id, pciide_promise_products)) 136 return (2); 137 } 138 return (0); 139 } 140 141 void 142 pdcide_attach(parent, self, aux) 143 struct device *parent, *self; 144 void *aux; 145 { 146 struct pci_attach_args *pa = aux; 147 struct pciide_softc *sc = (struct pciide_softc *)self; 148 149 pciide_common_attach(sc, pa, 150 pciide_lookup_product(pa->pa_id, pciide_promise_products)); 151 152 } 153 154 /* Macros to test product */ 155 #define PDC_IS_262(sc) \ 156 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 157 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 158 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 159 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 160 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 161 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 162 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 163 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 164 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 165 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 166 #define PDC_IS_265(sc) \ 167 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 168 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 169 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 170 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 171 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 172 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 173 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 174 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 175 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 176 #define PDC_IS_268(sc) \ 177 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 178 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 179 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 180 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 181 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 182 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 183 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 184 #define PDC_IS_276(sc) \ 185 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 186 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 187 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 188 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 189 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 190 191 void 192 pdc202xx_chip_map(sc, pa) 193 struct pciide_softc *sc; 194 struct pci_attach_args *pa; 195 { 196 struct pciide_channel *cp; 197 int channel; 198 pcireg_t interface, st, mode; 199 bus_size_t cmdsize, ctlsize; 200 201 if (!PDC_IS_268(sc)) { 202 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 203 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 204 st), DEBUG_PROBE); 205 } 206 if (pciide_chipen(sc, pa) == 0) 207 return; 208 209 /* turn off RAID mode */ 210 if (!PDC_IS_268(sc)) 211 st &= ~PDC2xx_STATE_IDERAID; 212 213 /* 214 * can't rely on the PCI_CLASS_REG content if the chip was in raid 215 * mode. We have to fake interface 216 */ 217 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 218 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 219 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 220 221 aprint_normal("%s: bus-master DMA support present", 222 sc->sc_wdcdev.sc_dev.dv_xname); 223 pciide_mapreg_dma(sc, pa); 224 aprint_normal("\n"); 225 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 226 WDC_CAPABILITY_MODE; 227 if (sc->sc_dma_ok) { 228 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 229 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 230 sc->sc_wdcdev.irqack = pciide_irqack; 231 } 232 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 233 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 234 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 235 sc->sc_wdcdev.PIO_cap = 4; 236 sc->sc_wdcdev.DMA_cap = 2; 237 if (PDC_IS_276(sc)) 238 sc->sc_wdcdev.UDMA_cap = 6; 239 else if (PDC_IS_265(sc)) 240 sc->sc_wdcdev.UDMA_cap = 5; 241 else if (PDC_IS_262(sc)) 242 sc->sc_wdcdev.UDMA_cap = 4; 243 else 244 sc->sc_wdcdev.UDMA_cap = 2; 245 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 246 pdc20268_setup_channel : pdc202xx_setup_channel; 247 sc->sc_wdcdev.channels = sc->wdc_chanarray; 248 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 249 250 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || 251 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || 252 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) { 253 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 254 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 255 } 256 257 if (!PDC_IS_268(sc)) { 258 /* setup failsafe defaults */ 259 mode = 0; 260 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 261 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 262 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 263 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 264 for (channel = 0; 265 channel < sc->sc_wdcdev.nchannels; 266 channel++) { 267 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 268 "drive 0 initial timings 0x%x, now 0x%x\n", 269 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 270 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 271 DEBUG_PROBE); 272 pci_conf_write(sc->sc_pc, sc->sc_tag, 273 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 274 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 275 "drive 1 initial timings 0x%x, now 0x%x\n", 276 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 277 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 278 pci_conf_write(sc->sc_pc, sc->sc_tag, 279 PDC2xx_TIM(channel, 1), mode); 280 } 281 282 mode = PDC2xx_SCR_DMA; 283 if (PDC_IS_265(sc)) { 284 mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT); 285 } else if (PDC_IS_262(sc)) { 286 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 287 } else { 288 /* the BIOS set it up this way */ 289 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 290 } 291 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 292 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 293 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 294 "now 0x%x\n", 295 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 296 PDC2xx_SCR), 297 mode), DEBUG_PROBE); 298 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 299 PDC2xx_SCR, mode); 300 301 /* controller initial state register is OK even without BIOS */ 302 /* Set DMA mode to IDE DMA compatibility */ 303 mode = 304 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 305 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 306 DEBUG_PROBE); 307 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 308 mode | 0x1); 309 mode = 310 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 311 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 312 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 313 mode | 0x1); 314 } 315 316 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 317 cp = &sc->pciide_channels[channel]; 318 if (pciide_chansetup(sc, channel, interface) == 0) 319 continue; 320 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 321 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 322 aprint_normal("%s: %s channel ignored (disabled)\n", 323 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 324 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 325 continue; 326 } 327 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 328 PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr); 329 } 330 if (!PDC_IS_268(sc)) { 331 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 332 "0x%x\n", st), DEBUG_PROBE); 333 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 334 } 335 return; 336 } 337 338 void 339 pdc202xx_setup_channel(chp) 340 struct channel_softc *chp; 341 { 342 struct ata_drive_datas *drvp; 343 int drive; 344 pcireg_t mode, st; 345 u_int32_t idedma_ctl, scr, atapi; 346 struct pciide_channel *cp = (struct pciide_channel*)chp; 347 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 348 int channel = chp->channel; 349 350 /* setup DMA if needed */ 351 pciide_channel_dma_setup(cp); 352 353 idedma_ctl = 0; 354 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 355 sc->sc_wdcdev.sc_dev.dv_xname, 356 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 357 DEBUG_PROBE); 358 359 /* Per channel settings */ 360 if (PDC_IS_262(sc)) { 361 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 362 PDC262_U66); 363 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 364 /* Trim UDMA mode */ 365 if ((st & PDC262_STATE_80P(channel)) != 0 || 366 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 367 chp->ch_drive[0].UDMA_mode <= 2) || 368 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 369 chp->ch_drive[1].UDMA_mode <= 2)) { 370 if (chp->ch_drive[0].UDMA_mode > 2) 371 chp->ch_drive[0].UDMA_mode = 2; 372 if (chp->ch_drive[1].UDMA_mode > 2) 373 chp->ch_drive[1].UDMA_mode = 2; 374 } 375 /* Set U66 if needed */ 376 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 377 chp->ch_drive[0].UDMA_mode > 2) || 378 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 379 chp->ch_drive[1].UDMA_mode > 2)) 380 scr |= PDC262_U66_EN(channel); 381 else 382 scr &= ~PDC262_U66_EN(channel); 383 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 384 PDC262_U66, scr); 385 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 386 sc->sc_wdcdev.sc_dev.dv_xname, channel, 387 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 388 PDC262_ATAPI(channel))), DEBUG_PROBE); 389 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 390 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 391 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 392 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 393 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 394 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 395 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 396 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 397 atapi = 0; 398 else 399 atapi = PDC262_ATAPI_UDMA; 400 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 401 PDC262_ATAPI(channel), atapi); 402 } 403 } 404 for (drive = 0; drive < 2; drive++) { 405 drvp = &chp->ch_drive[drive]; 406 /* If no drive, skip */ 407 if ((drvp->drive_flags & DRIVE) == 0) 408 continue; 409 mode = 0; 410 if (drvp->drive_flags & DRIVE_UDMA) { 411 /* use Ultra/DMA */ 412 drvp->drive_flags &= ~DRIVE_DMA; 413 mode = PDC2xx_TIM_SET_MB(mode, 414 pdc2xx_udma_mb[drvp->UDMA_mode]); 415 mode = PDC2xx_TIM_SET_MC(mode, 416 pdc2xx_udma_mc[drvp->UDMA_mode]); 417 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 418 } else if (drvp->drive_flags & DRIVE_DMA) { 419 mode = PDC2xx_TIM_SET_MB(mode, 420 pdc2xx_dma_mb[drvp->DMA_mode]); 421 mode = PDC2xx_TIM_SET_MC(mode, 422 pdc2xx_dma_mc[drvp->DMA_mode]); 423 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 424 } else { 425 mode = PDC2xx_TIM_SET_MB(mode, 426 pdc2xx_dma_mb[0]); 427 mode = PDC2xx_TIM_SET_MC(mode, 428 pdc2xx_dma_mc[0]); 429 } 430 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 431 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 432 if (drvp->drive_flags & DRIVE_ATA) 433 mode |= PDC2xx_TIM_PRE; 434 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 435 if (drvp->PIO_mode >= 3) { 436 mode |= PDC2xx_TIM_IORDY; 437 if (drive == 0) 438 mode |= PDC2xx_TIM_IORDYp; 439 } 440 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 441 "timings 0x%x\n", 442 sc->sc_wdcdev.sc_dev.dv_xname, 443 chp->channel, drive, mode), DEBUG_PROBE); 444 pci_conf_write(sc->sc_pc, sc->sc_tag, 445 PDC2xx_TIM(chp->channel, drive), mode); 446 } 447 if (idedma_ctl != 0) { 448 /* Add software bits in status register */ 449 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 450 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 451 idedma_ctl); 452 } 453 } 454 455 void 456 pdc20268_setup_channel(chp) 457 struct channel_softc *chp; 458 { 459 struct ata_drive_datas *drvp; 460 int drive; 461 u_int32_t idedma_ctl; 462 struct pciide_channel *cp = (struct pciide_channel*)chp; 463 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 464 int u100; 465 466 /* setup DMA if needed */ 467 pciide_channel_dma_setup(cp); 468 469 idedma_ctl = 0; 470 471 /* I don't know what this is for, FreeBSD does it ... */ 472 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 473 IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * chp->channel, 0x0b); 474 475 /* 476 * cable type detect, from FreeBSD 477 */ 478 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 479 IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * chp->channel) & 0x04) ? 480 0 : 1; 481 482 for (drive = 0; drive < 2; drive++) { 483 drvp = &chp->ch_drive[drive]; 484 /* If no drive, skip */ 485 if ((drvp->drive_flags & DRIVE) == 0) 486 continue; 487 if (drvp->drive_flags & DRIVE_UDMA) { 488 /* use Ultra/DMA */ 489 drvp->drive_flags &= ~DRIVE_DMA; 490 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 491 if (drvp->UDMA_mode > 2 && u100 == 0) 492 drvp->UDMA_mode = 2; 493 } else if (drvp->drive_flags & DRIVE_DMA) { 494 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 495 } 496 } 497 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 498 if (idedma_ctl != 0) { 499 /* Add software bits in status register */ 500 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 501 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 502 idedma_ctl); 503 } 504 } 505 506 int 507 pdc202xx_pci_intr(arg) 508 void *arg; 509 { 510 struct pciide_softc *sc = arg; 511 struct pciide_channel *cp; 512 struct channel_softc *wdc_cp; 513 int i, rv, crv; 514 u_int32_t scr; 515 516 rv = 0; 517 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 518 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 519 cp = &sc->pciide_channels[i]; 520 wdc_cp = &cp->wdc_channel; 521 /* If a compat channel skip. */ 522 if (cp->compat) 523 continue; 524 if (scr & PDC2xx_SCR_INT(i)) { 525 crv = wdcintr(wdc_cp); 526 if (crv == 0) 527 printf("%s:%d: bogus intr (reg 0x%x)\n", 528 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 529 else 530 rv = 1; 531 } 532 } 533 return rv; 534 } 535 536 int 537 pdc20265_pci_intr(arg) 538 void *arg; 539 { 540 struct pciide_softc *sc = arg; 541 struct pciide_channel *cp; 542 struct channel_softc *wdc_cp; 543 int i, rv, crv; 544 u_int32_t dmastat; 545 546 rv = 0; 547 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 548 cp = &sc->pciide_channels[i]; 549 wdc_cp = &cp->wdc_channel; 550 /* If a compat channel skip. */ 551 if (cp->compat) 552 continue; 553 #if 0 554 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * i, 0x0b); 555 if ((bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * i) & 0x20) == 0) 556 continue; 557 #endif 558 /* 559 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 560 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 561 * So use it instead (requires 2 reg reads instead of 1, 562 * but we can't do it another way). 563 */ 564 dmastat = bus_space_read_1(sc->sc_dma_iot, 565 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 566 if((dmastat & IDEDMA_CTL_INTR) == 0) 567 continue; 568 crv = wdcintr(wdc_cp); 569 if (crv == 0) 570 printf("%s:%d: bogus intr\n", 571 sc->sc_wdcdev.sc_dev.dv_xname, i); 572 else 573 rv = 1; 574 } 575 return rv; 576 } 577 578 static void 579 pdc20262_dma_start(v, channel, drive) 580 void *v; 581 int channel, drive; 582 { 583 struct pciide_softc *sc = v; 584 struct pciide_dma_maps *dma_maps = 585 &sc->pciide_channels[channel].dma_maps[drive]; 586 int atapi; 587 588 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 589 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ? 590 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 591 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1; 592 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 593 PDC262_ATAPI(channel), atapi); 594 } 595 596 pciide_dma_start(v, channel, drive); 597 } 598 599 int 600 pdc20262_dma_finish(v, channel, drive, force) 601 void *v; 602 int channel, drive; 603 int force; 604 { 605 struct pciide_softc *sc = v; 606 struct pciide_dma_maps *dma_maps = 607 &sc->pciide_channels[channel].dma_maps[drive]; 608 struct channel_softc *chp; 609 int atapi, error; 610 611 error = pciide_dma_finish(v, channel, drive, force); 612 613 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 614 chp = sc->wdc_chanarray[channel]; 615 atapi = 0; 616 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 617 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 618 if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 619 (chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 620 !(chp->ch_drive[1].drive_flags & DRIVE_DMA)) && 621 (!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 622 (chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 623 !(chp->ch_drive[0].drive_flags & DRIVE_DMA))) 624 atapi = PDC262_ATAPI_UDMA; 625 } 626 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 627 PDC262_ATAPI(channel), atapi); 628 } 629 630 return error; 631 } 632
Indexes created Fri Oct 03 02:09:57 GMT 2025