pdcide.c revision 1.2
1 /* $NetBSD: pdcide.c,v 1.2 2003/10/11 17:40:15 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_pdc202xx_reg.h> 40 41 static void pdc202xx_chip_map(struct pciide_softc *, struct pci_attach_args *); 42 static void pdc202xx_setup_channel(struct channel_softc *); 43 static void pdc20268_setup_channel(struct channel_softc *); 44 static int pdc202xx_pci_intr(void *); 45 static int pdc20265_pci_intr(void *); 46 static void pdc20262_dma_start(void *, int, int); 47 static int pdc20262_dma_finish(void *, int, int, int); 48 49 static int pdcide_match(struct device *, struct cfdata *, void *); 50 static void pdcide_attach(struct device *, struct device *, void *); 51 52 CFATTACH_DECL(pdcide, sizeof(struct pciide_softc), 53 pdcide_match, pdcide_attach, NULL, NULL); 54 55 static const struct pciide_product_desc pciide_promise_products[] = { 56 { PCI_PRODUCT_PROMISE_ULTRA33, 57 IDE_PCI_CLASS_OVERRIDE, 58 "Promise Ultra33/ATA Bus Master IDE Accelerator", 59 pdc202xx_chip_map, 60 }, 61 { PCI_PRODUCT_PROMISE_ULTRA66, 62 IDE_PCI_CLASS_OVERRIDE, 63 "Promise Ultra66/ATA Bus Master IDE Accelerator", 64 pdc202xx_chip_map, 65 }, 66 { PCI_PRODUCT_PROMISE_ULTRA100, 67 IDE_PCI_CLASS_OVERRIDE, 68 "Promise Ultra100/ATA Bus Master IDE Accelerator", 69 pdc202xx_chip_map, 70 }, 71 { PCI_PRODUCT_PROMISE_ULTRA100X, 72 IDE_PCI_CLASS_OVERRIDE, 73 "Promise Ultra100/ATA Bus Master IDE Accelerator", 74 pdc202xx_chip_map, 75 }, 76 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 77 IDE_PCI_CLASS_OVERRIDE, 78 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 79 pdc202xx_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 82 IDE_PCI_CLASS_OVERRIDE, 83 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 84 pdc202xx_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_ULTRA133, 87 IDE_PCI_CLASS_OVERRIDE, 88 "Promise Ultra133/ATA Bus Master IDE Accelerator", 89 pdc202xx_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 92 IDE_PCI_CLASS_OVERRIDE, 93 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 94 pdc202xx_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_MBULTRA133, 97 IDE_PCI_CLASS_OVERRIDE, 98 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 99 pdc202xx_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 102 IDE_PCI_CLASS_OVERRIDE, 103 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 104 pdc202xx_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_FASTTRAK133LITE, 107 IDE_PCI_CLASS_OVERRIDE, 108 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 109 pdc202xx_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_SATA150TX2PLUS, 112 IDE_PCI_CLASS_OVERRIDE, 113 "Promise Serial ATA/150 TX2plus Bus Master IDE Accelerator", 114 pdc202xx_chip_map, 115 }, 116 { 0, 117 0, 118 NULL, 119 NULL 120 } 121 }; 122 123 static int 124 pdcide_match(struct device *parent, struct cfdata *match, void *aux) 125 { 126 struct pci_attach_args *pa = aux; 127 128 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 129 if (pciide_lookup_product(pa->pa_id, pciide_promise_products)) 130 return (2); 131 } 132 return (0); 133 } 134 135 static void 136 pdcide_attach(struct device *parent, struct device *self, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 struct pciide_softc *sc = (struct pciide_softc *)self; 140 141 pciide_common_attach(sc, pa, 142 pciide_lookup_product(pa->pa_id, pciide_promise_products)); 143 144 } 145 146 /* Macros to test product */ 147 #define PDC_IS_262(sc) \ 148 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 149 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 150 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 151 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 152 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 153 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 154 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 155 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 156 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 157 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 158 #define PDC_IS_265(sc) \ 159 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 160 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 161 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 162 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 163 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 164 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 165 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 166 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 167 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 168 #define PDC_IS_268(sc) \ 169 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 170 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 171 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 172 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 173 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 174 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 175 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 176 #define PDC_IS_276(sc) \ 177 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 178 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 179 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 180 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 181 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 182 183 static void 184 pdc202xx_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 185 { 186 struct pciide_channel *cp; 187 int channel; 188 pcireg_t interface, st, mode; 189 bus_size_t cmdsize, ctlsize; 190 191 if (!PDC_IS_268(sc)) { 192 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 193 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 194 st), DEBUG_PROBE); 195 } 196 if (pciide_chipen(sc, pa) == 0) 197 return; 198 199 /* turn off RAID mode */ 200 if (!PDC_IS_268(sc)) 201 st &= ~PDC2xx_STATE_IDERAID; 202 203 /* 204 * can't rely on the PCI_CLASS_REG content if the chip was in raid 205 * mode. We have to fake interface 206 */ 207 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 208 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 209 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 210 211 aprint_normal("%s: bus-master DMA support present", 212 sc->sc_wdcdev.sc_dev.dv_xname); 213 pciide_mapreg_dma(sc, pa); 214 aprint_normal("\n"); 215 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 216 WDC_CAPABILITY_MODE; 217 if (sc->sc_dma_ok) { 218 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 219 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 220 sc->sc_wdcdev.irqack = pciide_irqack; 221 } 222 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 223 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 224 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 225 sc->sc_wdcdev.PIO_cap = 4; 226 sc->sc_wdcdev.DMA_cap = 2; 227 if (PDC_IS_276(sc)) 228 sc->sc_wdcdev.UDMA_cap = 6; 229 else if (PDC_IS_265(sc)) 230 sc->sc_wdcdev.UDMA_cap = 5; 231 else if (PDC_IS_262(sc)) 232 sc->sc_wdcdev.UDMA_cap = 4; 233 else 234 sc->sc_wdcdev.UDMA_cap = 2; 235 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 236 pdc20268_setup_channel : pdc202xx_setup_channel; 237 sc->sc_wdcdev.channels = sc->wdc_chanarray; 238 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 239 240 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || 241 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || 242 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) { 243 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 244 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 245 } 246 247 if (!PDC_IS_268(sc)) { 248 /* setup failsafe defaults */ 249 mode = 0; 250 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 251 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 252 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 253 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 254 for (channel = 0; 255 channel < sc->sc_wdcdev.nchannels; 256 channel++) { 257 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 258 "drive 0 initial timings 0x%x, now 0x%x\n", 259 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 260 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 261 DEBUG_PROBE); 262 pci_conf_write(sc->sc_pc, sc->sc_tag, 263 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 264 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 265 "drive 1 initial timings 0x%x, now 0x%x\n", 266 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 267 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 268 pci_conf_write(sc->sc_pc, sc->sc_tag, 269 PDC2xx_TIM(channel, 1), mode); 270 } 271 272 mode = PDC2xx_SCR_DMA; 273 if (PDC_IS_265(sc)) { 274 mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT); 275 } else if (PDC_IS_262(sc)) { 276 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 277 } else { 278 /* the BIOS set it up this way */ 279 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 280 } 281 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 282 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 283 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 284 "now 0x%x\n", 285 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 286 PDC2xx_SCR), 287 mode), DEBUG_PROBE); 288 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 289 PDC2xx_SCR, mode); 290 291 /* controller initial state register is OK even without BIOS */ 292 /* Set DMA mode to IDE DMA compatibility */ 293 mode = 294 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 295 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 296 DEBUG_PROBE); 297 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 298 mode | 0x1); 299 mode = 300 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 301 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 302 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 303 mode | 0x1); 304 } 305 306 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 307 cp = &sc->pciide_channels[channel]; 308 if (pciide_chansetup(sc, channel, interface) == 0) 309 continue; 310 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 311 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 312 aprint_normal("%s: %s channel ignored (disabled)\n", 313 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 314 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 315 continue; 316 } 317 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 318 PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr); 319 } 320 if (!PDC_IS_268(sc)) { 321 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 322 "0x%x\n", st), DEBUG_PROBE); 323 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 324 } 325 return; 326 } 327 328 static void 329 pdc202xx_setup_channel(struct channel_softc *chp) 330 { 331 struct ata_drive_datas *drvp; 332 int drive; 333 pcireg_t mode, st; 334 u_int32_t idedma_ctl, scr, atapi; 335 struct pciide_channel *cp = (struct pciide_channel*)chp; 336 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 337 int channel = chp->channel; 338 339 /* setup DMA if needed */ 340 pciide_channel_dma_setup(cp); 341 342 idedma_ctl = 0; 343 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 344 sc->sc_wdcdev.sc_dev.dv_xname, 345 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 346 DEBUG_PROBE); 347 348 /* Per channel settings */ 349 if (PDC_IS_262(sc)) { 350 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 351 PDC262_U66); 352 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 353 /* Trim UDMA mode */ 354 if ((st & PDC262_STATE_80P(channel)) != 0 || 355 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 356 chp->ch_drive[0].UDMA_mode <= 2) || 357 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 358 chp->ch_drive[1].UDMA_mode <= 2)) { 359 if (chp->ch_drive[0].UDMA_mode > 2) 360 chp->ch_drive[0].UDMA_mode = 2; 361 if (chp->ch_drive[1].UDMA_mode > 2) 362 chp->ch_drive[1].UDMA_mode = 2; 363 } 364 /* Set U66 if needed */ 365 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 366 chp->ch_drive[0].UDMA_mode > 2) || 367 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 368 chp->ch_drive[1].UDMA_mode > 2)) 369 scr |= PDC262_U66_EN(channel); 370 else 371 scr &= ~PDC262_U66_EN(channel); 372 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 373 PDC262_U66, scr); 374 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 375 sc->sc_wdcdev.sc_dev.dv_xname, channel, 376 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 377 PDC262_ATAPI(channel))), DEBUG_PROBE); 378 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 379 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 380 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 381 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 382 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 383 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 384 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 385 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 386 atapi = 0; 387 else 388 atapi = PDC262_ATAPI_UDMA; 389 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 390 PDC262_ATAPI(channel), atapi); 391 } 392 } 393 for (drive = 0; drive < 2; drive++) { 394 drvp = &chp->ch_drive[drive]; 395 /* If no drive, skip */ 396 if ((drvp->drive_flags & DRIVE) == 0) 397 continue; 398 mode = 0; 399 if (drvp->drive_flags & DRIVE_UDMA) { 400 /* use Ultra/DMA */ 401 drvp->drive_flags &= ~DRIVE_DMA; 402 mode = PDC2xx_TIM_SET_MB(mode, 403 pdc2xx_udma_mb[drvp->UDMA_mode]); 404 mode = PDC2xx_TIM_SET_MC(mode, 405 pdc2xx_udma_mc[drvp->UDMA_mode]); 406 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 407 } else if (drvp->drive_flags & DRIVE_DMA) { 408 mode = PDC2xx_TIM_SET_MB(mode, 409 pdc2xx_dma_mb[drvp->DMA_mode]); 410 mode = PDC2xx_TIM_SET_MC(mode, 411 pdc2xx_dma_mc[drvp->DMA_mode]); 412 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 413 } else { 414 mode = PDC2xx_TIM_SET_MB(mode, 415 pdc2xx_dma_mb[0]); 416 mode = PDC2xx_TIM_SET_MC(mode, 417 pdc2xx_dma_mc[0]); 418 } 419 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 420 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 421 if (drvp->drive_flags & DRIVE_ATA) 422 mode |= PDC2xx_TIM_PRE; 423 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 424 if (drvp->PIO_mode >= 3) { 425 mode |= PDC2xx_TIM_IORDY; 426 if (drive == 0) 427 mode |= PDC2xx_TIM_IORDYp; 428 } 429 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 430 "timings 0x%x\n", 431 sc->sc_wdcdev.sc_dev.dv_xname, 432 chp->channel, drive, mode), DEBUG_PROBE); 433 pci_conf_write(sc->sc_pc, sc->sc_tag, 434 PDC2xx_TIM(chp->channel, drive), mode); 435 } 436 if (idedma_ctl != 0) { 437 /* Add software bits in status register */ 438 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 439 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 440 idedma_ctl); 441 } 442 } 443 444 static void 445 pdc20268_setup_channel(struct channel_softc *chp) 446 { 447 struct ata_drive_datas *drvp; 448 int drive; 449 u_int32_t idedma_ctl; 450 struct pciide_channel *cp = (struct pciide_channel*)chp; 451 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 452 int u100; 453 454 /* setup DMA if needed */ 455 pciide_channel_dma_setup(cp); 456 457 idedma_ctl = 0; 458 459 /* I don't know what this is for, FreeBSD does it ... */ 460 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 461 IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * chp->channel, 0x0b); 462 463 /* 464 * cable type detect, from FreeBSD 465 */ 466 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 467 IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * chp->channel) & 0x04) ? 468 0 : 1; 469 470 for (drive = 0; drive < 2; drive++) { 471 drvp = &chp->ch_drive[drive]; 472 /* If no drive, skip */ 473 if ((drvp->drive_flags & DRIVE) == 0) 474 continue; 475 if (drvp->drive_flags & DRIVE_UDMA) { 476 /* use Ultra/DMA */ 477 drvp->drive_flags &= ~DRIVE_DMA; 478 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 479 if (drvp->UDMA_mode > 2 && u100 == 0) 480 drvp->UDMA_mode = 2; 481 } else if (drvp->drive_flags & DRIVE_DMA) { 482 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 483 } 484 } 485 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 486 if (idedma_ctl != 0) { 487 /* Add software bits in status register */ 488 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 489 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 490 idedma_ctl); 491 } 492 } 493 494 static int 495 pdc202xx_pci_intr(void *arg) 496 { 497 struct pciide_softc *sc = arg; 498 struct pciide_channel *cp; 499 struct channel_softc *wdc_cp; 500 int i, rv, crv; 501 u_int32_t scr; 502 503 rv = 0; 504 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 505 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 506 cp = &sc->pciide_channels[i]; 507 wdc_cp = &cp->wdc_channel; 508 /* If a compat channel skip. */ 509 if (cp->compat) 510 continue; 511 if (scr & PDC2xx_SCR_INT(i)) { 512 crv = wdcintr(wdc_cp); 513 if (crv == 0) 514 printf("%s:%d: bogus intr (reg 0x%x)\n", 515 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 516 else 517 rv = 1; 518 } 519 } 520 return rv; 521 } 522 523 static int 524 pdc20265_pci_intr(void *arg) 525 { 526 struct pciide_softc *sc = arg; 527 struct pciide_channel *cp; 528 struct channel_softc *wdc_cp; 529 int i, rv, crv; 530 u_int32_t dmastat; 531 532 rv = 0; 533 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 534 cp = &sc->pciide_channels[i]; 535 wdc_cp = &cp->wdc_channel; 536 /* If a compat channel skip. */ 537 if (cp->compat) 538 continue; 539 #if 0 540 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * i, 0x0b); 541 if ((bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * i) & 0x20) == 0) 542 continue; 543 #endif 544 /* 545 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 546 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 547 * So use it instead (requires 2 reg reads instead of 1, 548 * but we can't do it another way). 549 */ 550 dmastat = bus_space_read_1(sc->sc_dma_iot, 551 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 552 if((dmastat & IDEDMA_CTL_INTR) == 0) 553 continue; 554 crv = wdcintr(wdc_cp); 555 if (crv == 0) 556 printf("%s:%d: bogus intr\n", 557 sc->sc_wdcdev.sc_dev.dv_xname, i); 558 else 559 rv = 1; 560 } 561 return rv; 562 } 563 564 static void 565 pdc20262_dma_start(void *v, int channel, int drive) 566 { 567 struct pciide_softc *sc = v; 568 struct pciide_dma_maps *dma_maps = 569 &sc->pciide_channels[channel].dma_maps[drive]; 570 int atapi; 571 572 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 573 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ? 574 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 575 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1; 576 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 577 PDC262_ATAPI(channel), atapi); 578 } 579 580 pciide_dma_start(v, channel, drive); 581 } 582 583 static int 584 pdc20262_dma_finish(void *v, int channel, int drive, int force) 585 { 586 struct pciide_softc *sc = v; 587 struct pciide_dma_maps *dma_maps = 588 &sc->pciide_channels[channel].dma_maps[drive]; 589 struct channel_softc *chp; 590 int atapi, error; 591 592 error = pciide_dma_finish(v, channel, drive, force); 593 594 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 595 chp = sc->wdc_chanarray[channel]; 596 atapi = 0; 597 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 598 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 599 if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 600 (chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 601 !(chp->ch_drive[1].drive_flags & DRIVE_DMA)) && 602 (!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 603 (chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 604 !(chp->ch_drive[0].drive_flags & DRIVE_DMA))) 605 atapi = PDC262_ATAPI_UDMA; 606 } 607 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 608 PDC262_ATAPI(channel), atapi); 609 } 610 611 return error; 612 } 613
Indexes created Fri Oct 03 02:09:57 GMT 2025