pdcide.c revision 1.25
1 /* $NetBSD: pdcide.c,v 1.25 2007/02/09 21:55:27 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pdcide.c,v 1.25 2007/02/09 21:55:27 ad Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_pdc202xx_reg.h> 43 44 static void pdc202xx_chip_map(struct pciide_softc *, struct pci_attach_args *); 45 static void pdc202xx_setup_channel(struct ata_channel *); 46 static void pdc20268_setup_channel(struct ata_channel *); 47 static int pdc202xx_pci_intr(void *); 48 static int pdc20265_pci_intr(void *); 49 static void pdc20262_dma_start(void *, int, int); 50 static int pdc20262_dma_finish(void *, int, int, int); 51 52 static int pdcide_match(struct device *, struct cfdata *, void *); 53 static void pdcide_attach(struct device *, struct device *, void *); 54 55 CFATTACH_DECL(pdcide, sizeof(struct pciide_softc), 56 pdcide_match, pdcide_attach, NULL, NULL); 57 58 static const struct pciide_product_desc pciide_promise_products[] = { 59 { PCI_PRODUCT_PROMISE_PDC20246, 60 0, 61 "Promise Ultra33/ATA Bus Master IDE Accelerator", 62 pdc202xx_chip_map, 63 }, 64 { PCI_PRODUCT_PROMISE_PDC20262, 65 0, 66 "Promise Ultra66/ATA Bus Master IDE Accelerator", 67 pdc202xx_chip_map, 68 }, 69 { PCI_PRODUCT_PROMISE_PDC20267, 70 0, 71 "Promise Ultra100/ATA Bus Master IDE Accelerator", 72 pdc202xx_chip_map, 73 }, 74 { PCI_PRODUCT_PROMISE_PDC20265, 75 0, 76 "Promise Ultra100/ATA Bus Master IDE Accelerator", 77 pdc202xx_chip_map, 78 }, 79 { PCI_PRODUCT_PROMISE_PDC20268, 80 0, 81 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 82 pdc202xx_chip_map, 83 }, 84 { PCI_PRODUCT_PROMISE_PDC20270, 85 0, 86 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 87 pdc202xx_chip_map, 88 }, 89 { PCI_PRODUCT_PROMISE_PDC20269, 90 0, 91 "Promise Ultra133/ATA Bus Master IDE Accelerator", 92 pdc202xx_chip_map, 93 }, 94 { PCI_PRODUCT_PROMISE_PDC20276, 95 0, 96 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 97 pdc202xx_chip_map, 98 }, 99 { PCI_PRODUCT_PROMISE_PDC20275, 100 0, 101 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 102 pdc202xx_chip_map, 103 }, 104 { PCI_PRODUCT_PROMISE_PDC20271, 105 0, 106 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 107 pdc202xx_chip_map, 108 }, 109 { PCI_PRODUCT_PROMISE_PDC20277, 110 0, 111 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 112 pdc202xx_chip_map, 113 }, 114 { 0, 115 0, 116 NULL, 117 NULL 118 } 119 }; 120 121 static int 122 pdcide_match(struct device *parent, struct cfdata *match, 123 void *aux) 124 { 125 struct pci_attach_args *pa = aux; 126 127 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 128 if (pciide_lookup_product(pa->pa_id, pciide_promise_products)) 129 return (2); 130 } 131 return (0); 132 } 133 134 static void 135 pdcide_attach(struct device *parent, struct device *self, void *aux) 136 { 137 struct pci_attach_args *pa = aux; 138 struct pciide_softc *sc = (struct pciide_softc *)self; 139 140 pciide_common_attach(sc, pa, 141 pciide_lookup_product(pa->pa_id, pciide_promise_products)); 142 143 } 144 145 /* Macros to test product */ 146 #define PDC_IS_262(sc) \ 147 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || \ 148 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \ 149 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 150 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 151 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 152 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 153 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 154 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 155 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 156 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 157 #define PDC_IS_265(sc) \ 158 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \ 159 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 160 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 161 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 162 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 163 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 164 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 165 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 166 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 167 #define PDC_IS_268(sc) \ 168 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 169 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 170 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 171 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 172 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 173 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 174 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 175 #define PDC_IS_276(sc) \ 176 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 177 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 178 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 179 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 180 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 181 182 static void 183 pdc202xx_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 184 { 185 struct pciide_channel *cp; 186 int channel; 187 pcireg_t interface, st, mode; 188 bus_size_t cmdsize, ctlsize; 189 190 if (!PDC_IS_268(sc)) { 191 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 192 ATADEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 193 st), DEBUG_PROBE); 194 /* turn off RAID mode */ 195 if (st & PDC2xx_STATE_IDERAID) { 196 ATADEBUG_PRINT(("pdc202xx_setup_chip: turning off RAID mode\n"), DEBUG_PROBE); 197 st &= ~PDC2xx_STATE_IDERAID; 198 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 199 } 200 } else 201 st = PDC2xx_STATE_NATIVE | PDC262_STATE_EN(0) | PDC262_STATE_EN(1); 202 203 if (pciide_chipen(sc, pa) == 0) 204 return; 205 206 /* 207 * can't rely on the PCI_CLASS_REG content if the chip was in raid 208 * mode. We have to fake interface 209 */ 210 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 211 if (st & PDC2xx_STATE_NATIVE) 212 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 213 214 aprint_verbose("%s: bus-master DMA support present", 215 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 216 pciide_mapreg_dma(sc, pa); 217 aprint_verbose("\n"); 218 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 219 if (sc->sc_dma_ok) { 220 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 221 sc->sc_wdcdev.irqack = pciide_irqack; 222 } 223 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 224 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 225 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 226 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 227 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 228 if (PDC_IS_276(sc)) 229 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 230 else if (PDC_IS_265(sc)) 231 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 232 else if (PDC_IS_262(sc)) 233 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 234 else 235 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 236 sc->sc_wdcdev.sc_atac.atac_set_modes = PDC_IS_268(sc) ? 237 pdc20268_setup_channel : pdc202xx_setup_channel; 238 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 239 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 240 241 wdc_allocate_regs(&sc->sc_wdcdev); 242 243 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || 244 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || 245 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265) { 246 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 247 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 248 } 249 250 if (!PDC_IS_268(sc)) { 251 /* setup failsafe defaults */ 252 mode = 0; 253 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 254 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 255 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 256 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 257 for (channel = 0; 258 channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 259 channel++) { 260 ATADEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 261 "drive 0 initial timings 0x%x, now 0x%x\n", 262 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 263 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 264 DEBUG_PROBE); 265 pci_conf_write(sc->sc_pc, sc->sc_tag, 266 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 267 ATADEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 268 "drive 1 initial timings 0x%x, now 0x%x\n", 269 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 270 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 271 pci_conf_write(sc->sc_pc, sc->sc_tag, 272 PDC2xx_TIM(channel, 1), mode); 273 } 274 275 mode = PDC2xx_SCR_DMA; 276 if (PDC_IS_265(sc)) { 277 mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT); 278 } else if (PDC_IS_262(sc)) { 279 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 280 } else { 281 /* the BIOS set it up this way */ 282 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 283 } 284 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 285 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 286 ATADEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 287 "now 0x%x\n", 288 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 289 PDC2xx_SCR), 290 mode), DEBUG_PROBE); 291 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 292 PDC2xx_SCR, mode); 293 294 /* controller initial state register is OK even without BIOS */ 295 /* Set DMA mode to IDE DMA compatibility */ 296 mode = 297 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 298 ATADEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 299 DEBUG_PROBE); 300 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 301 mode | 0x1); 302 mode = 303 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 304 ATADEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 305 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 306 mode | 0x1); 307 } 308 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 309 channel++) { 310 cp = &sc->pciide_channels[channel]; 311 if (pciide_chansetup(sc, channel, interface) == 0) 312 continue; 313 if ((st & (PDC_IS_262(sc) ? 314 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 315 aprint_normal("%s: %s channel ignored (disabled)\n", 316 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 317 cp->ata_channel.ch_flags |= ATACH_DISABLED; 318 continue; 319 } 320 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 321 PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr); 322 /* clear interrupt, in case there is one pending */ 323 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 324 IDEDMA_CTL_INTR); 325 } 326 return; 327 } 328 329 static void 330 pdc202xx_setup_channel(struct ata_channel *chp) 331 { 332 struct ata_drive_datas *drvp; 333 int drive, s; 334 pcireg_t mode, st; 335 u_int32_t idedma_ctl, scr, atapi; 336 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 337 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 338 int channel = chp->ch_channel; 339 340 /* setup DMA if needed */ 341 pciide_channel_dma_setup(cp); 342 343 idedma_ctl = 0; 344 ATADEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 345 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 346 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 347 DEBUG_PROBE); 348 349 /* Per channel settings */ 350 if (PDC_IS_262(sc)) { 351 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 352 PDC262_U66); 353 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 354 /* Trim UDMA mode */ 355 if ((st & PDC262_STATE_80P(channel)) != 0 || 356 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 357 chp->ch_drive[0].UDMA_mode <= 2) || 358 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 359 chp->ch_drive[1].UDMA_mode <= 2)) { 360 if (chp->ch_drive[0].UDMA_mode > 2) 361 chp->ch_drive[0].UDMA_mode = 2; 362 if (chp->ch_drive[1].UDMA_mode > 2) 363 chp->ch_drive[1].UDMA_mode = 2; 364 } 365 /* Set U66 if needed */ 366 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 367 chp->ch_drive[0].UDMA_mode > 2) || 368 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 369 chp->ch_drive[1].UDMA_mode > 2)) 370 scr |= PDC262_U66_EN(channel); 371 else 372 scr &= ~PDC262_U66_EN(channel); 373 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 374 PDC262_U66, scr); 375 ATADEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 376 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel, 377 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 378 PDC262_ATAPI(channel))), DEBUG_PROBE); 379 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 380 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 381 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 382 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 383 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 384 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 385 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 386 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 387 atapi = 0; 388 else 389 atapi = PDC262_ATAPI_UDMA; 390 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 391 PDC262_ATAPI(channel), atapi); 392 } 393 } 394 for (drive = 0; drive < 2; drive++) { 395 drvp = &chp->ch_drive[drive]; 396 /* If no drive, skip */ 397 if ((drvp->drive_flags & DRIVE) == 0) 398 continue; 399 mode = 0; 400 if (drvp->drive_flags & DRIVE_UDMA) { 401 /* use Ultra/DMA */ 402 s = splbio(); 403 drvp->drive_flags &= ~DRIVE_DMA; 404 splx(s); 405 mode = PDC2xx_TIM_SET_MB(mode, 406 pdc2xx_udma_mb[drvp->UDMA_mode]); 407 mode = PDC2xx_TIM_SET_MC(mode, 408 pdc2xx_udma_mc[drvp->UDMA_mode]); 409 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 410 } else if (drvp->drive_flags & DRIVE_DMA) { 411 mode = PDC2xx_TIM_SET_MB(mode, 412 pdc2xx_dma_mb[drvp->DMA_mode]); 413 mode = PDC2xx_TIM_SET_MC(mode, 414 pdc2xx_dma_mc[drvp->DMA_mode]); 415 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 416 } else { 417 mode = PDC2xx_TIM_SET_MB(mode, 418 pdc2xx_dma_mb[0]); 419 mode = PDC2xx_TIM_SET_MC(mode, 420 pdc2xx_dma_mc[0]); 421 } 422 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 423 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 424 if (drvp->drive_flags & DRIVE_ATA) 425 mode |= PDC2xx_TIM_PRE; 426 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 427 if (drvp->PIO_mode >= 3) { 428 mode |= PDC2xx_TIM_IORDY; 429 if (drive == 0) 430 mode |= PDC2xx_TIM_IORDYp; 431 } 432 ATADEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 433 "timings 0x%x\n", 434 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 435 chp->ch_channel, drive, mode), DEBUG_PROBE); 436 pci_conf_write(sc->sc_pc, sc->sc_tag, 437 PDC2xx_TIM(chp->ch_channel, drive), mode); 438 } 439 if (idedma_ctl != 0) { 440 /* Add software bits in status register */ 441 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 442 0, idedma_ctl); 443 } 444 } 445 446 static void 447 pdc20268_setup_channel(struct ata_channel *chp) 448 { 449 struct ata_drive_datas *drvp; 450 int drive, s; 451 u_int32_t idedma_ctl; 452 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 453 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 454 int u100; 455 456 /* setup DMA if needed */ 457 pciide_channel_dma_setup(cp); 458 459 idedma_ctl = 0; 460 461 /* I don't know what this is for, FreeBSD does it ... */ 462 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 463 IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * chp->ch_channel, 0x0b); 464 465 /* 466 * cable type detect, from FreeBSD 467 */ 468 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 469 IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * chp->ch_channel) & 0x04) ? 470 0 : 1; 471 472 for (drive = 0; drive < 2; drive++) { 473 drvp = &chp->ch_drive[drive]; 474 /* If no drive, skip */ 475 if ((drvp->drive_flags & DRIVE) == 0) 476 continue; 477 if (drvp->drive_flags & DRIVE_UDMA) { 478 /* use Ultra/DMA */ 479 s = splbio(); 480 drvp->drive_flags &= ~DRIVE_DMA; 481 splx(s); 482 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 483 if (drvp->UDMA_mode > 2 && u100 == 0) 484 drvp->UDMA_mode = 2; 485 } else if (drvp->drive_flags & DRIVE_DMA) { 486 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 487 } 488 } 489 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 490 if (idedma_ctl != 0) { 491 /* Add software bits in status register */ 492 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 493 0, idedma_ctl); 494 } 495 } 496 497 static int 498 pdc202xx_pci_intr(void *arg) 499 { 500 struct pciide_softc *sc = arg; 501 struct pciide_channel *cp; 502 struct ata_channel *wdc_cp; 503 int i, rv, crv; 504 u_int32_t scr; 505 506 rv = 0; 507 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 508 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 509 cp = &sc->pciide_channels[i]; 510 wdc_cp = &cp->ata_channel; 511 /* If a compat channel skip. */ 512 if (cp->compat) 513 continue; 514 if (scr & PDC2xx_SCR_INT(i)) { 515 crv = wdcintr(wdc_cp); 516 if (crv == 0) 517 printf("%s:%d: bogus intr (reg 0x%x)\n", 518 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 519 i, scr); 520 else 521 rv = 1; 522 } 523 } 524 return rv; 525 } 526 527 static int 528 pdc20265_pci_intr(void *arg) 529 { 530 struct pciide_softc *sc = arg; 531 struct pciide_channel *cp; 532 struct ata_channel *wdc_cp; 533 int i, rv, crv; 534 u_int32_t dmastat; 535 536 rv = 0; 537 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 538 cp = &sc->pciide_channels[i]; 539 wdc_cp = &cp->ata_channel; 540 /* If a compat channel skip. */ 541 if (cp->compat) 542 continue; 543 #if 0 544 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * i, 0x0b); 545 if ((bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * i) & 0x20) == 0) 546 continue; 547 #endif 548 /* 549 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 550 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 551 * So use it instead (requires 2 reg reads instead of 1, 552 * but we can't do it another way). 553 */ 554 dmastat = bus_space_read_1(sc->sc_dma_iot, 555 cp->dma_iohs[IDEDMA_CTL], 0); 556 if((dmastat & IDEDMA_CTL_INTR) == 0) 557 continue; 558 crv = wdcintr(wdc_cp); 559 if (crv == 0) 560 printf("%s:%d: bogus intr\n", 561 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 562 else 563 rv = 1; 564 } 565 return rv; 566 } 567 568 static void 569 pdc20262_dma_start(void *v, int channel, int drive) 570 { 571 struct pciide_softc *sc = v; 572 struct pciide_dma_maps *dma_maps = 573 &sc->pciide_channels[channel].dma_maps[drive]; 574 int atapi; 575 576 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 577 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ? 578 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 579 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1; 580 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 581 PDC262_ATAPI(channel), atapi); 582 } 583 584 pciide_dma_start(v, channel, drive); 585 } 586 587 static int 588 pdc20262_dma_finish(void *v, int channel, int drive, int force) 589 { 590 struct pciide_softc *sc = v; 591 struct pciide_dma_maps *dma_maps = 592 &sc->pciide_channels[channel].dma_maps[drive]; 593 struct ata_channel *chp; 594 int atapi, error; 595 596 error = pciide_dma_finish(v, channel, drive, force); 597 598 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 599 chp = sc->wdc_chanarray[channel]; 600 atapi = 0; 601 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 602 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 603 if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 604 (chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 605 !(chp->ch_drive[1].drive_flags & DRIVE_DMA)) && 606 (!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 607 (chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 608 !(chp->ch_drive[0].drive_flags & DRIVE_DMA))) 609 atapi = PDC262_ATAPI_UDMA; 610 } 611 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 612 PDC262_ATAPI(channel), atapi); 613 } 614 615 return error; 616 } 617
Indexes created Thu Oct 02 14:10:14 GMT 2025