pdcide.c revision 1.25.40.1
1 /* $NetBSD: pdcide.c,v 1.25.40.1 2008/04/03 12:42:53 mjf Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pdcide.c,v 1.25.40.1 2008/04/03 12:42:53 mjf Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_pdc202xx_reg.h> 43 44 static void pdc202xx_chip_map(struct pciide_softc *, struct pci_attach_args *); 45 static void pdc202xx_setup_channel(struct ata_channel *); 46 static void pdc20268_setup_channel(struct ata_channel *); 47 static int pdc202xx_pci_intr(void *); 48 static int pdc20265_pci_intr(void *); 49 static void pdc20262_dma_start(void *, int, int); 50 static int pdc20262_dma_finish(void *, int, int, int); 51 52 static int pdcide_match(device_t, cfdata_t, void *); 53 static void pdcide_attach(device_t, device_t, void *); 54 55 CFATTACH_DECL_NEW(pdcide, sizeof(struct pciide_softc), 56 pdcide_match, pdcide_attach, NULL, NULL); 57 58 static const struct pciide_product_desc pciide_promise_products[] = { 59 { PCI_PRODUCT_PROMISE_PDC20246, 60 0, 61 "Promise Ultra33/ATA Bus Master IDE Accelerator", 62 pdc202xx_chip_map, 63 }, 64 { PCI_PRODUCT_PROMISE_PDC20262, 65 0, 66 "Promise Ultra66/ATA Bus Master IDE Accelerator", 67 pdc202xx_chip_map, 68 }, 69 { PCI_PRODUCT_PROMISE_PDC20267, 70 0, 71 "Promise Ultra100/ATA Bus Master IDE Accelerator", 72 pdc202xx_chip_map, 73 }, 74 { PCI_PRODUCT_PROMISE_PDC20265, 75 0, 76 "Promise Ultra100/ATA Bus Master IDE Accelerator", 77 pdc202xx_chip_map, 78 }, 79 { PCI_PRODUCT_PROMISE_PDC20268, 80 0, 81 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 82 pdc202xx_chip_map, 83 }, 84 { PCI_PRODUCT_PROMISE_PDC20270, 85 0, 86 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 87 pdc202xx_chip_map, 88 }, 89 { PCI_PRODUCT_PROMISE_PDC20269, 90 0, 91 "Promise Ultra133/ATA Bus Master IDE Accelerator", 92 pdc202xx_chip_map, 93 }, 94 { PCI_PRODUCT_PROMISE_PDC20276, 95 0, 96 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 97 pdc202xx_chip_map, 98 }, 99 { PCI_PRODUCT_PROMISE_PDC20275, 100 0, 101 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 102 pdc202xx_chip_map, 103 }, 104 { PCI_PRODUCT_PROMISE_PDC20271, 105 0, 106 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 107 pdc202xx_chip_map, 108 }, 109 { PCI_PRODUCT_PROMISE_PDC20277, 110 0, 111 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 112 pdc202xx_chip_map, 113 }, 114 { 0, 115 0, 116 NULL, 117 NULL 118 } 119 }; 120 121 static int 122 pdcide_match(device_t parent, cfdata_t match, void *aux) 123 { 124 struct pci_attach_args *pa = aux; 125 126 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 127 if (pciide_lookup_product(pa->pa_id, pciide_promise_products)) 128 return (2); 129 } 130 return (0); 131 } 132 133 static void 134 pdcide_attach(device_t parent, device_t self, void *aux) 135 { 136 struct pci_attach_args *pa = aux; 137 struct pciide_softc *sc = device_private(self); 138 139 sc->sc_wdcdev.sc_atac.atac_dev = self; 140 141 pciide_common_attach(sc, pa, 142 pciide_lookup_product(pa->pa_id, pciide_promise_products)); 143 144 } 145 146 /* Macros to test product */ 147 #define PDC_IS_262(sc) \ 148 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || \ 149 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \ 150 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 151 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 152 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 153 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 154 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 155 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 156 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 157 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 158 #define PDC_IS_265(sc) \ 159 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \ 160 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 161 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 162 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 163 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 164 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 165 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 166 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 167 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 168 #define PDC_IS_268(sc) \ 169 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 170 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 171 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 172 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 173 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 174 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 175 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 176 #define PDC_IS_276(sc) \ 177 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 178 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 179 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 180 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 181 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 182 183 static void 184 pdc202xx_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 185 { 186 struct pciide_channel *cp; 187 int channel; 188 pcireg_t interface, st, mode; 189 bus_size_t cmdsize, ctlsize; 190 191 if (!PDC_IS_268(sc)) { 192 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 193 ATADEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 194 st), DEBUG_PROBE); 195 /* turn off RAID mode */ 196 if (st & PDC2xx_STATE_IDERAID) { 197 ATADEBUG_PRINT(("pdc202xx_setup_chip: turning off RAID mode\n"), DEBUG_PROBE); 198 st &= ~PDC2xx_STATE_IDERAID; 199 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 200 } 201 } else 202 st = PDC2xx_STATE_NATIVE | PDC262_STATE_EN(0) | PDC262_STATE_EN(1); 203 204 if (pciide_chipen(sc, pa) == 0) 205 return; 206 207 /* 208 * can't rely on the PCI_CLASS_REG content if the chip was in raid 209 * mode. We have to fake interface 210 */ 211 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 212 if (st & PDC2xx_STATE_NATIVE) 213 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 214 215 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 216 "bus-master DMA support present"); 217 pciide_mapreg_dma(sc, pa); 218 aprint_verbose("\n"); 219 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 220 if (sc->sc_dma_ok) { 221 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 222 sc->sc_wdcdev.irqack = pciide_irqack; 223 } 224 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 225 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 226 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 227 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 228 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 229 if (PDC_IS_276(sc)) 230 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 231 else if (PDC_IS_265(sc)) 232 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 233 else if (PDC_IS_262(sc)) 234 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 235 else 236 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 237 sc->sc_wdcdev.sc_atac.atac_set_modes = PDC_IS_268(sc) ? 238 pdc20268_setup_channel : pdc202xx_setup_channel; 239 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 240 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 241 242 wdc_allocate_regs(&sc->sc_wdcdev); 243 244 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || 245 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || 246 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265) { 247 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 248 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 249 } 250 251 if (!PDC_IS_268(sc)) { 252 /* setup failsafe defaults */ 253 mode = 0; 254 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 255 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 256 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 257 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 258 for (channel = 0; 259 channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 260 channel++) { 261 ATADEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 262 "drive 0 initial timings 0x%x, now 0x%x\n", 263 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 264 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 265 DEBUG_PROBE); 266 pci_conf_write(sc->sc_pc, sc->sc_tag, 267 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 268 ATADEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 269 "drive 1 initial timings 0x%x, now 0x%x\n", 270 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 271 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 272 pci_conf_write(sc->sc_pc, sc->sc_tag, 273 PDC2xx_TIM(channel, 1), mode); 274 } 275 276 mode = PDC2xx_SCR_DMA; 277 if (PDC_IS_265(sc)) { 278 mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT); 279 } else if (PDC_IS_262(sc)) { 280 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 281 } else { 282 /* the BIOS set it up this way */ 283 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 284 } 285 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 286 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 287 ATADEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 288 "now 0x%x\n", 289 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 290 PDC2xx_SCR), 291 mode), DEBUG_PROBE); 292 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 293 PDC2xx_SCR, mode); 294 295 /* controller initial state register is OK even without BIOS */ 296 /* Set DMA mode to IDE DMA compatibility */ 297 mode = 298 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 299 ATADEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 300 DEBUG_PROBE); 301 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 302 mode | 0x1); 303 mode = 304 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 305 ATADEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 306 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 307 mode | 0x1); 308 } 309 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 310 channel++) { 311 cp = &sc->pciide_channels[channel]; 312 if (pciide_chansetup(sc, channel, interface) == 0) 313 continue; 314 if ((st & (PDC_IS_262(sc) ? 315 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 316 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 317 "%s channel ignored (disabled)\n", cp->name); 318 cp->ata_channel.ch_flags |= ATACH_DISABLED; 319 continue; 320 } 321 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 322 PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr); 323 /* clear interrupt, in case there is one pending */ 324 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 325 IDEDMA_CTL_INTR); 326 } 327 return; 328 } 329 330 static void 331 pdc202xx_setup_channel(struct ata_channel *chp) 332 { 333 struct ata_drive_datas *drvp; 334 int drive, s; 335 pcireg_t mode, st; 336 u_int32_t idedma_ctl, scr, atapi; 337 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 338 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 339 int channel = chp->ch_channel; 340 341 /* setup DMA if needed */ 342 pciide_channel_dma_setup(cp); 343 344 idedma_ctl = 0; 345 ATADEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 346 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 347 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 348 DEBUG_PROBE); 349 350 /* Per channel settings */ 351 if (PDC_IS_262(sc)) { 352 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 353 PDC262_U66); 354 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 355 /* Trim UDMA mode */ 356 if ((st & PDC262_STATE_80P(channel)) != 0 || 357 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 358 chp->ch_drive[0].UDMA_mode <= 2) || 359 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 360 chp->ch_drive[1].UDMA_mode <= 2)) { 361 if (chp->ch_drive[0].UDMA_mode > 2) 362 chp->ch_drive[0].UDMA_mode = 2; 363 if (chp->ch_drive[1].UDMA_mode > 2) 364 chp->ch_drive[1].UDMA_mode = 2; 365 } 366 /* Set U66 if needed */ 367 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 368 chp->ch_drive[0].UDMA_mode > 2) || 369 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 370 chp->ch_drive[1].UDMA_mode > 2)) 371 scr |= PDC262_U66_EN(channel); 372 else 373 scr &= ~PDC262_U66_EN(channel); 374 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 375 PDC262_U66, scr); 376 ATADEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 377 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 378 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 379 PDC262_ATAPI(channel))), DEBUG_PROBE); 380 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 381 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 382 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 383 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 384 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 385 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 386 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 387 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 388 atapi = 0; 389 else 390 atapi = PDC262_ATAPI_UDMA; 391 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 392 PDC262_ATAPI(channel), atapi); 393 } 394 } 395 for (drive = 0; drive < 2; drive++) { 396 drvp = &chp->ch_drive[drive]; 397 /* If no drive, skip */ 398 if ((drvp->drive_flags & DRIVE) == 0) 399 continue; 400 mode = 0; 401 if (drvp->drive_flags & DRIVE_UDMA) { 402 /* use Ultra/DMA */ 403 s = splbio(); 404 drvp->drive_flags &= ~DRIVE_DMA; 405 splx(s); 406 mode = PDC2xx_TIM_SET_MB(mode, 407 pdc2xx_udma_mb[drvp->UDMA_mode]); 408 mode = PDC2xx_TIM_SET_MC(mode, 409 pdc2xx_udma_mc[drvp->UDMA_mode]); 410 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 411 } else if (drvp->drive_flags & DRIVE_DMA) { 412 mode = PDC2xx_TIM_SET_MB(mode, 413 pdc2xx_dma_mb[drvp->DMA_mode]); 414 mode = PDC2xx_TIM_SET_MC(mode, 415 pdc2xx_dma_mc[drvp->DMA_mode]); 416 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 417 } else { 418 mode = PDC2xx_TIM_SET_MB(mode, 419 pdc2xx_dma_mb[0]); 420 mode = PDC2xx_TIM_SET_MC(mode, 421 pdc2xx_dma_mc[0]); 422 } 423 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 424 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 425 if (drvp->drive_flags & DRIVE_ATA) 426 mode |= PDC2xx_TIM_PRE; 427 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 428 if (drvp->PIO_mode >= 3) { 429 mode |= PDC2xx_TIM_IORDY; 430 if (drive == 0) 431 mode |= PDC2xx_TIM_IORDYp; 432 } 433 ATADEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 434 "timings 0x%x\n", 435 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 436 chp->ch_channel, drive, mode), DEBUG_PROBE); 437 pci_conf_write(sc->sc_pc, sc->sc_tag, 438 PDC2xx_TIM(chp->ch_channel, drive), mode); 439 } 440 if (idedma_ctl != 0) { 441 /* Add software bits in status register */ 442 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 443 0, idedma_ctl); 444 } 445 } 446 447 static void 448 pdc20268_setup_channel(struct ata_channel *chp) 449 { 450 struct ata_drive_datas *drvp; 451 int drive, s; 452 u_int32_t idedma_ctl; 453 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 454 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 455 int u100; 456 457 /* setup DMA if needed */ 458 pciide_channel_dma_setup(cp); 459 460 idedma_ctl = 0; 461 462 /* I don't know what this is for, FreeBSD does it ... */ 463 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 464 IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * chp->ch_channel, 0x0b); 465 466 /* 467 * cable type detect, from FreeBSD 468 */ 469 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 470 IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * chp->ch_channel) & 0x04) ? 471 0 : 1; 472 473 for (drive = 0; drive < 2; drive++) { 474 drvp = &chp->ch_drive[drive]; 475 /* If no drive, skip */ 476 if ((drvp->drive_flags & DRIVE) == 0) 477 continue; 478 if (drvp->drive_flags & DRIVE_UDMA) { 479 /* use Ultra/DMA */ 480 s = splbio(); 481 drvp->drive_flags &= ~DRIVE_DMA; 482 splx(s); 483 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 484 if (drvp->UDMA_mode > 2 && u100 == 0) 485 drvp->UDMA_mode = 2; 486 } else if (drvp->drive_flags & DRIVE_DMA) { 487 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 488 } 489 } 490 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 491 if (idedma_ctl != 0) { 492 /* Add software bits in status register */ 493 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 494 0, idedma_ctl); 495 } 496 } 497 498 static int 499 pdc202xx_pci_intr(void *arg) 500 { 501 struct pciide_softc *sc = arg; 502 struct pciide_channel *cp; 503 struct ata_channel *wdc_cp; 504 int i, rv, crv; 505 u_int32_t scr; 506 507 rv = 0; 508 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 509 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 510 cp = &sc->pciide_channels[i]; 511 wdc_cp = &cp->ata_channel; 512 /* If a compat channel skip. */ 513 if (cp->compat) 514 continue; 515 if (scr & PDC2xx_SCR_INT(i)) { 516 crv = wdcintr(wdc_cp); 517 if (crv == 0) 518 aprint_error("%s:%d: bogus intr (reg 0x%x)\n", 519 device_xname( 520 sc->sc_wdcdev.sc_atac.atac_dev), i, scr); 521 else 522 rv = 1; 523 } 524 } 525 return rv; 526 } 527 528 static int 529 pdc20265_pci_intr(void *arg) 530 { 531 struct pciide_softc *sc = arg; 532 struct pciide_channel *cp; 533 struct ata_channel *wdc_cp; 534 int i, rv, crv; 535 u_int32_t dmastat; 536 537 rv = 0; 538 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 539 cp = &sc->pciide_channels[i]; 540 wdc_cp = &cp->ata_channel; 541 /* If a compat channel skip. */ 542 if (cp->compat) 543 continue; 544 #if 0 545 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * i, 0x0b); 546 if ((bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * i) & 0x20) == 0) 547 continue; 548 #endif 549 /* 550 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 551 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 552 * So use it instead (requires 2 reg reads instead of 1, 553 * but we can't do it another way). 554 */ 555 dmastat = bus_space_read_1(sc->sc_dma_iot, 556 cp->dma_iohs[IDEDMA_CTL], 0); 557 if((dmastat & IDEDMA_CTL_INTR) == 0) 558 continue; 559 crv = wdcintr(wdc_cp); 560 if (crv == 0) 561 aprint_error("%s:%d: bogus intr\n", 562 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), i); 563 else 564 rv = 1; 565 } 566 return rv; 567 } 568 569 static void 570 pdc20262_dma_start(void *v, int channel, int drive) 571 { 572 struct pciide_softc *sc = v; 573 struct pciide_dma_maps *dma_maps = 574 &sc->pciide_channels[channel].dma_maps[drive]; 575 int atapi; 576 577 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 578 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ? 579 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 580 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1; 581 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 582 PDC262_ATAPI(channel), atapi); 583 } 584 585 pciide_dma_start(v, channel, drive); 586 } 587 588 static int 589 pdc20262_dma_finish(void *v, int channel, int drive, int force) 590 { 591 struct pciide_softc *sc = v; 592 struct pciide_dma_maps *dma_maps = 593 &sc->pciide_channels[channel].dma_maps[drive]; 594 struct ata_channel *chp; 595 int atapi, error; 596 597 error = pciide_dma_finish(v, channel, drive, force); 598 599 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 600 chp = sc->wdc_chanarray[channel]; 601 atapi = 0; 602 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 603 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 604 if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 605 (chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 606 !(chp->ch_drive[1].drive_flags & DRIVE_DMA)) && 607 (!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 608 (chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 609 !(chp->ch_drive[0].drive_flags & DRIVE_DMA))) 610 atapi = PDC262_ATAPI_UDMA; 611 } 612 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 613 PDC262_ATAPI(channel), atapi); 614 } 615 616 return error; 617 } 618
Indexes created Thu Oct 02 14:10:14 GMT 2025