pdcide.c revision 1.27.4.1
1 /* $NetBSD: pdcide.c,v 1.27.4.1 2011/03/05 20:53:56 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: pdcide.c,v 1.27.4.1 2011/03/05 20:53:56 rmind Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_pdc202xx_reg.h> 38 39 static void pdc202xx_chip_map(struct pciide_softc *, struct pci_attach_args *); 40 static void pdc202xx_setup_channel(struct ata_channel *); 41 static void pdc20268_setup_channel(struct ata_channel *); 42 static int pdc202xx_pci_intr(void *); 43 static int pdc20265_pci_intr(void *); 44 static void pdc20262_dma_start(void *, int, int); 45 static int pdc20262_dma_finish(void *, int, int, int); 46 47 static int pdcide_match(device_t, cfdata_t, void *); 48 static void pdcide_attach(device_t, device_t, void *); 49 50 CFATTACH_DECL_NEW(pdcide, sizeof(struct pciide_softc), 51 pdcide_match, pdcide_attach, NULL, NULL); 52 53 static const struct pciide_product_desc pciide_promise_products[] = { 54 { PCI_PRODUCT_PROMISE_PDC20246, 55 0, 56 "Promise Ultra33/ATA Bus Master IDE Accelerator", 57 pdc202xx_chip_map, 58 }, 59 { PCI_PRODUCT_PROMISE_PDC20262, 60 0, 61 "Promise Ultra66/ATA Bus Master IDE Accelerator", 62 pdc202xx_chip_map, 63 }, 64 { PCI_PRODUCT_PROMISE_PDC20267, 65 0, 66 "Promise Ultra100/ATA Bus Master IDE Accelerator", 67 pdc202xx_chip_map, 68 }, 69 { PCI_PRODUCT_PROMISE_PDC20265, 70 0, 71 "Promise Ultra100/ATA Bus Master IDE Accelerator", 72 pdc202xx_chip_map, 73 }, 74 { PCI_PRODUCT_PROMISE_PDC20268, 75 0, 76 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 77 pdc202xx_chip_map, 78 }, 79 { PCI_PRODUCT_PROMISE_PDC20270, 80 0, 81 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 82 pdc202xx_chip_map, 83 }, 84 { PCI_PRODUCT_PROMISE_PDC20269, 85 0, 86 "Promise Ultra133/ATA Bus Master IDE Accelerator", 87 pdc202xx_chip_map, 88 }, 89 { PCI_PRODUCT_PROMISE_PDC20276, 90 0, 91 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 92 pdc202xx_chip_map, 93 }, 94 { PCI_PRODUCT_PROMISE_PDC20275, 95 0, 96 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 97 pdc202xx_chip_map, 98 }, 99 { PCI_PRODUCT_PROMISE_PDC20271, 100 0, 101 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 102 pdc202xx_chip_map, 103 }, 104 { PCI_PRODUCT_PROMISE_PDC20277, 105 0, 106 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 107 pdc202xx_chip_map, 108 }, 109 { 0, 110 0, 111 NULL, 112 NULL 113 } 114 }; 115 116 static int 117 pdcide_match(device_t parent, cfdata_t match, void *aux) 118 { 119 struct pci_attach_args *pa = aux; 120 121 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 122 if (pciide_lookup_product(pa->pa_id, pciide_promise_products)) 123 return (2); 124 } 125 return (0); 126 } 127 128 static void 129 pdcide_attach(device_t parent, device_t self, void *aux) 130 { 131 struct pci_attach_args *pa = aux; 132 struct pciide_softc *sc = device_private(self); 133 134 sc->sc_wdcdev.sc_atac.atac_dev = self; 135 136 pciide_common_attach(sc, pa, 137 pciide_lookup_product(pa->pa_id, pciide_promise_products)); 138 139 } 140 141 /* Macros to test product */ 142 #define PDC_IS_262(sc) \ 143 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || \ 144 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \ 145 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 146 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 147 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 148 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 149 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 150 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 151 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 152 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 153 #define PDC_IS_265(sc) \ 154 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \ 155 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 156 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 157 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 158 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 159 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 160 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 161 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 162 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 163 #define PDC_IS_268(sc) \ 164 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 165 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 166 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 167 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 168 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 169 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 170 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 171 #define PDC_IS_276(sc) \ 172 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 173 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 174 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 175 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 176 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 177 178 static void 179 pdc202xx_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 180 { 181 struct pciide_channel *cp; 182 int channel; 183 pcireg_t interface, st, mode; 184 185 if (!PDC_IS_268(sc)) { 186 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 187 ATADEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 188 st), DEBUG_PROBE); 189 /* turn off RAID mode */ 190 if (st & PDC2xx_STATE_IDERAID) { 191 ATADEBUG_PRINT(("pdc202xx_setup_chip: turning off RAID mode\n"), DEBUG_PROBE); 192 st &= ~PDC2xx_STATE_IDERAID; 193 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 194 } 195 } else 196 st = PDC2xx_STATE_NATIVE | PDC262_STATE_EN(0) | PDC262_STATE_EN(1); 197 198 if (pciide_chipen(sc, pa) == 0) 199 return; 200 201 /* 202 * can't rely on the PCI_CLASS_REG content if the chip was in raid 203 * mode. We have to fake interface 204 */ 205 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 206 if (st & PDC2xx_STATE_NATIVE) 207 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 208 209 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 210 "bus-master DMA support present"); 211 pciide_mapreg_dma(sc, pa); 212 aprint_verbose("\n"); 213 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 214 if (sc->sc_dma_ok) { 215 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 216 sc->sc_wdcdev.irqack = pciide_irqack; 217 } 218 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 219 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 220 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 221 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 222 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 223 if (PDC_IS_276(sc)) 224 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 225 else if (PDC_IS_265(sc)) 226 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 227 else if (PDC_IS_262(sc)) 228 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 229 else 230 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 231 sc->sc_wdcdev.sc_atac.atac_set_modes = PDC_IS_268(sc) ? 232 pdc20268_setup_channel : pdc202xx_setup_channel; 233 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 234 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 235 236 wdc_allocate_regs(&sc->sc_wdcdev); 237 238 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || 239 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || 240 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265) { 241 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 242 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 243 } 244 245 if (!PDC_IS_268(sc)) { 246 /* setup failsafe defaults */ 247 mode = 0; 248 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 249 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 250 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 251 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 252 for (channel = 0; 253 channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 254 channel++) { 255 ATADEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 256 "drive 0 initial timings 0x%x, now 0x%x\n", 257 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 258 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 259 DEBUG_PROBE); 260 pci_conf_write(sc->sc_pc, sc->sc_tag, 261 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 262 ATADEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 263 "drive 1 initial timings 0x%x, now 0x%x\n", 264 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 265 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 266 pci_conf_write(sc->sc_pc, sc->sc_tag, 267 PDC2xx_TIM(channel, 1), mode); 268 } 269 270 mode = PDC2xx_SCR_DMA; 271 if (PDC_IS_265(sc)) { 272 mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT); 273 } else if (PDC_IS_262(sc)) { 274 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 275 } else { 276 /* the BIOS set it up this way */ 277 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 278 } 279 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 280 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 281 ATADEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 282 "now 0x%x\n", 283 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 284 PDC2xx_SCR), 285 mode), DEBUG_PROBE); 286 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 287 PDC2xx_SCR, mode); 288 289 /* controller initial state register is OK even without BIOS */ 290 /* Set DMA mode to IDE DMA compatibility */ 291 mode = 292 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 293 ATADEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 294 DEBUG_PROBE); 295 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 296 mode | 0x1); 297 mode = 298 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 299 ATADEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 300 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 301 mode | 0x1); 302 } 303 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 304 channel++) { 305 cp = &sc->pciide_channels[channel]; 306 if (pciide_chansetup(sc, channel, interface) == 0) 307 continue; 308 if ((st & (PDC_IS_262(sc) ? 309 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 310 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 311 "%s channel ignored (disabled)\n", cp->name); 312 cp->ata_channel.ch_flags |= ATACH_DISABLED; 313 continue; 314 } 315 pciide_mapchan(pa, cp, interface, 316 PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr); 317 /* clear interrupt, in case there is one pending */ 318 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 319 IDEDMA_CTL_INTR); 320 } 321 return; 322 } 323 324 static void 325 pdc202xx_setup_channel(struct ata_channel *chp) 326 { 327 struct ata_drive_datas *drvp; 328 int drive, s; 329 pcireg_t mode, st; 330 u_int32_t idedma_ctl, scr, atapi; 331 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 332 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 333 int channel = chp->ch_channel; 334 335 /* setup DMA if needed */ 336 pciide_channel_dma_setup(cp); 337 338 idedma_ctl = 0; 339 ATADEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 340 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 341 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 342 DEBUG_PROBE); 343 344 /* Per channel settings */ 345 if (PDC_IS_262(sc)) { 346 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 347 PDC262_U66); 348 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 349 /* Trim UDMA mode */ 350 if ((st & PDC262_STATE_80P(channel)) != 0 || 351 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 352 chp->ch_drive[0].UDMA_mode <= 2) || 353 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 354 chp->ch_drive[1].UDMA_mode <= 2)) { 355 if (chp->ch_drive[0].UDMA_mode > 2) 356 chp->ch_drive[0].UDMA_mode = 2; 357 if (chp->ch_drive[1].UDMA_mode > 2) 358 chp->ch_drive[1].UDMA_mode = 2; 359 } 360 /* Set U66 if needed */ 361 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 362 chp->ch_drive[0].UDMA_mode > 2) || 363 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 364 chp->ch_drive[1].UDMA_mode > 2)) 365 scr |= PDC262_U66_EN(channel); 366 else 367 scr &= ~PDC262_U66_EN(channel); 368 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 369 PDC262_U66, scr); 370 ATADEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 371 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 372 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 373 PDC262_ATAPI(channel))), DEBUG_PROBE); 374 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 375 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 376 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 377 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 378 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 379 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 380 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 381 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 382 atapi = 0; 383 else 384 atapi = PDC262_ATAPI_UDMA; 385 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 386 PDC262_ATAPI(channel), atapi); 387 } 388 } 389 for (drive = 0; drive < 2; drive++) { 390 drvp = &chp->ch_drive[drive]; 391 /* If no drive, skip */ 392 if ((drvp->drive_flags & DRIVE) == 0) 393 continue; 394 mode = 0; 395 if (drvp->drive_flags & DRIVE_UDMA) { 396 /* use Ultra/DMA */ 397 s = splbio(); 398 drvp->drive_flags &= ~DRIVE_DMA; 399 splx(s); 400 mode = PDC2xx_TIM_SET_MB(mode, 401 pdc2xx_udma_mb[drvp->UDMA_mode]); 402 mode = PDC2xx_TIM_SET_MC(mode, 403 pdc2xx_udma_mc[drvp->UDMA_mode]); 404 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 405 } else if (drvp->drive_flags & DRIVE_DMA) { 406 mode = PDC2xx_TIM_SET_MB(mode, 407 pdc2xx_dma_mb[drvp->DMA_mode]); 408 mode = PDC2xx_TIM_SET_MC(mode, 409 pdc2xx_dma_mc[drvp->DMA_mode]); 410 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 411 } else { 412 mode = PDC2xx_TIM_SET_MB(mode, 413 pdc2xx_dma_mb[0]); 414 mode = PDC2xx_TIM_SET_MC(mode, 415 pdc2xx_dma_mc[0]); 416 } 417 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 418 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 419 if (drvp->drive_flags & DRIVE_ATA) 420 mode |= PDC2xx_TIM_PRE; 421 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 422 if (drvp->PIO_mode >= 3) { 423 mode |= PDC2xx_TIM_IORDY; 424 if (drive == 0) 425 mode |= PDC2xx_TIM_IORDYp; 426 } 427 ATADEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 428 "timings 0x%x\n", 429 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 430 chp->ch_channel, drive, mode), DEBUG_PROBE); 431 pci_conf_write(sc->sc_pc, sc->sc_tag, 432 PDC2xx_TIM(chp->ch_channel, drive), mode); 433 } 434 if (idedma_ctl != 0) { 435 /* Add software bits in status register */ 436 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 437 0, idedma_ctl); 438 } 439 } 440 441 static void 442 pdc20268_setup_channel(struct ata_channel *chp) 443 { 444 struct ata_drive_datas *drvp; 445 int drive, s; 446 u_int32_t idedma_ctl; 447 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 448 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 449 int u100; 450 451 /* setup DMA if needed */ 452 pciide_channel_dma_setup(cp); 453 454 idedma_ctl = 0; 455 456 /* I don't know what this is for, FreeBSD does it ... */ 457 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 458 IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * chp->ch_channel, 0x0b); 459 460 /* 461 * cable type detect, from FreeBSD 462 */ 463 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 464 IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * chp->ch_channel) & 0x04) ? 465 0 : 1; 466 467 for (drive = 0; drive < 2; drive++) { 468 drvp = &chp->ch_drive[drive]; 469 /* If no drive, skip */ 470 if ((drvp->drive_flags & DRIVE) == 0) 471 continue; 472 if (drvp->drive_flags & DRIVE_UDMA) { 473 /* use Ultra/DMA */ 474 s = splbio(); 475 drvp->drive_flags &= ~DRIVE_DMA; 476 splx(s); 477 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 478 if (drvp->UDMA_mode > 2 && u100 == 0) 479 drvp->UDMA_mode = 2; 480 } else if (drvp->drive_flags & DRIVE_DMA) { 481 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 482 } 483 } 484 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 485 if (idedma_ctl != 0) { 486 /* Add software bits in status register */ 487 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 488 0, idedma_ctl); 489 } 490 } 491 492 static int 493 pdc202xx_pci_intr(void *arg) 494 { 495 struct pciide_softc *sc = arg; 496 struct pciide_channel *cp; 497 struct ata_channel *wdc_cp; 498 int i, rv, crv; 499 u_int32_t scr; 500 501 rv = 0; 502 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 503 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 504 cp = &sc->pciide_channels[i]; 505 wdc_cp = &cp->ata_channel; 506 /* If a compat channel skip. */ 507 if (cp->compat) 508 continue; 509 if (scr & PDC2xx_SCR_INT(i)) { 510 crv = wdcintr(wdc_cp); 511 if (crv == 0) 512 aprint_error("%s:%d: bogus intr (reg 0x%x)\n", 513 device_xname( 514 sc->sc_wdcdev.sc_atac.atac_dev), i, scr); 515 else 516 rv = 1; 517 } 518 } 519 return rv; 520 } 521 522 static int 523 pdc20265_pci_intr(void *arg) 524 { 525 struct pciide_softc *sc = arg; 526 struct pciide_channel *cp; 527 struct ata_channel *wdc_cp; 528 int i, rv, crv; 529 u_int32_t dmastat; 530 531 rv = 0; 532 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 533 cp = &sc->pciide_channels[i]; 534 wdc_cp = &cp->ata_channel; 535 /* If a compat channel skip. */ 536 if (cp->compat) 537 continue; 538 #if 0 539 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * i, 0x0b); 540 if ((bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * i) & 0x20) == 0) 541 continue; 542 #endif 543 /* 544 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 545 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 546 * So use it instead (requires 2 reg reads instead of 1, 547 * but we can't do it another way). 548 */ 549 dmastat = bus_space_read_1(sc->sc_dma_iot, 550 cp->dma_iohs[IDEDMA_CTL], 0); 551 if((dmastat & IDEDMA_CTL_INTR) == 0) 552 continue; 553 crv = wdcintr(wdc_cp); 554 if (crv == 0) 555 aprint_error("%s:%d: bogus intr\n", 556 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), i); 557 else 558 rv = 1; 559 } 560 return rv; 561 } 562 563 static void 564 pdc20262_dma_start(void *v, int channel, int drive) 565 { 566 struct pciide_softc *sc = v; 567 struct pciide_dma_maps *dma_maps = 568 &sc->pciide_channels[channel].dma_maps[drive]; 569 int atapi; 570 571 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 572 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ? 573 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 574 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1; 575 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 576 PDC262_ATAPI(channel), atapi); 577 } 578 579 pciide_dma_start(v, channel, drive); 580 } 581 582 static int 583 pdc20262_dma_finish(void *v, int channel, int drive, int force) 584 { 585 struct pciide_softc *sc = v; 586 struct pciide_dma_maps *dma_maps = 587 &sc->pciide_channels[channel].dma_maps[drive]; 588 struct ata_channel *chp; 589 int atapi, error; 590 591 error = pciide_dma_finish(v, channel, drive, force); 592 593 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 594 chp = sc->wdc_chanarray[channel]; 595 atapi = 0; 596 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 597 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 598 if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 599 (chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 600 !(chp->ch_drive[1].drive_flags & DRIVE_DMA)) && 601 (!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 602 (chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 603 !(chp->ch_drive[0].drive_flags & DRIVE_DMA))) 604 atapi = PDC262_ATAPI_UDMA; 605 } 606 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 607 PDC262_ATAPI(channel), atapi); 608 } 609 610 return error; 611 } 612
Indexes created Fri Oct 03 02:09:57 GMT 2025