pdcide.c revision 1.34.2.2
1 /* $NetBSD: pdcide.c,v 1.34.2.2 2014/08/20 00:03:48 tls Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: pdcide.c,v 1.34.2.2 2014/08/20 00:03:48 tls Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_pdc202xx_reg.h> 38 39 static void pdc202xx_chip_map(struct pciide_softc *, 40 const struct pci_attach_args *); 41 static void pdc202xx_setup_channel(struct ata_channel *); 42 static void pdc20268_setup_channel(struct ata_channel *); 43 static int pdc202xx_pci_intr(void *); 44 static int pdc20265_pci_intr(void *); 45 static void pdc20262_dma_start(void *, int, int); 46 static int pdc20262_dma_finish(void *, int, int, int); 47 48 static int pdcide_match(device_t, cfdata_t, void *); 49 static void pdcide_attach(device_t, device_t, void *); 50 51 CFATTACH_DECL_NEW(pdcide, sizeof(struct pciide_softc), 52 pdcide_match, pdcide_attach, pciide_detach, NULL); 53 54 static const struct pciide_product_desc pciide_promise_products[] = { 55 { PCI_PRODUCT_PROMISE_PDC20246, 56 0, 57 "Promise Ultra33/ATA Bus Master IDE Accelerator", 58 pdc202xx_chip_map, 59 }, 60 { PCI_PRODUCT_PROMISE_PDC20262, 61 0, 62 "Promise Ultra66/ATA Bus Master IDE Accelerator", 63 pdc202xx_chip_map, 64 }, 65 { PCI_PRODUCT_PROMISE_PDC20267, 66 0, 67 "Promise Ultra100/ATA Bus Master IDE Accelerator", 68 pdc202xx_chip_map, 69 }, 70 { PCI_PRODUCT_PROMISE_PDC20265, 71 0, 72 "Promise Ultra100/ATA Bus Master IDE Accelerator", 73 pdc202xx_chip_map, 74 }, 75 { PCI_PRODUCT_PROMISE_PDC20268, 76 0, 77 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 78 pdc202xx_chip_map, 79 }, 80 { PCI_PRODUCT_PROMISE_PDC20270, 81 0, 82 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 83 pdc202xx_chip_map, 84 }, 85 { PCI_PRODUCT_PROMISE_PDC20269, 86 0, 87 "Promise Ultra133/ATA Bus Master IDE Accelerator", 88 pdc202xx_chip_map, 89 }, 90 { PCI_PRODUCT_PROMISE_PDC20276, 91 0, 92 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 93 pdc202xx_chip_map, 94 }, 95 { PCI_PRODUCT_PROMISE_PDC20275, 96 0, 97 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 98 pdc202xx_chip_map, 99 }, 100 { PCI_PRODUCT_PROMISE_PDC20271, 101 0, 102 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 103 pdc202xx_chip_map, 104 }, 105 { PCI_PRODUCT_PROMISE_PDC20277, 106 0, 107 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 108 pdc202xx_chip_map, 109 }, 110 { 0, 111 0, 112 NULL, 113 NULL 114 } 115 }; 116 117 static int 118 pdcide_match(device_t parent, cfdata_t match, void *aux) 119 { 120 struct pci_attach_args *pa = aux; 121 122 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 123 if (pciide_lookup_product(pa->pa_id, pciide_promise_products)) 124 return (2); 125 } 126 return (0); 127 } 128 129 static void 130 pdcide_attach(device_t parent, device_t self, void *aux) 131 { 132 struct pci_attach_args *pa = aux; 133 struct pciide_softc *sc = device_private(self); 134 135 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 136 137 sc->sc_wdcdev.sc_atac.atac_dev = self; 138 139 pciide_common_attach(sc, pa, 140 pciide_lookup_product(pa->pa_id, pciide_promise_products)); 141 142 } 143 144 /* Macros to test product */ 145 #define PDC_IS_262(sc) \ 146 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || \ 147 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \ 148 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 149 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 150 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 151 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 152 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 153 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 154 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 155 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 156 #define PDC_IS_265(sc) \ 157 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \ 158 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 159 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 160 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 161 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 162 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 163 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 164 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 165 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 166 #define PDC_IS_268(sc) \ 167 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 168 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \ 169 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 170 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 171 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 172 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 173 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 174 #define PDC_IS_276(sc) \ 175 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 176 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 177 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 178 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 179 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 180 181 static void 182 pdc202xx_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 183 { 184 struct pciide_channel *cp; 185 int channel; 186 pcireg_t interface, st, mode; 187 188 if (!PDC_IS_268(sc)) { 189 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 190 ATADEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 191 st), DEBUG_PROBE); 192 /* turn off RAID mode */ 193 if (st & PDC2xx_STATE_IDERAID) { 194 ATADEBUG_PRINT(("pdc202xx_setup_chip: turning off RAID mode\n"), DEBUG_PROBE); 195 st &= ~PDC2xx_STATE_IDERAID; 196 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 197 } 198 } else 199 st = PDC2xx_STATE_NATIVE | PDC262_STATE_EN(0) | PDC262_STATE_EN(1); 200 201 if (pciide_chipen(sc, pa) == 0) 202 return; 203 204 /* 205 * can't rely on the PCI_CLASS_REG content if the chip was in raid 206 * mode. We have to fake interface 207 */ 208 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 209 if (st & PDC2xx_STATE_NATIVE) 210 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 211 212 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 213 "bus-master DMA support present"); 214 pciide_mapreg_dma(sc, pa); 215 aprint_verbose("\n"); 216 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 217 if (sc->sc_dma_ok) { 218 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 219 sc->sc_wdcdev.irqack = pciide_irqack; 220 } 221 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 222 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 223 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 224 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 225 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 226 if (PDC_IS_276(sc)) 227 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 228 else if (PDC_IS_265(sc)) 229 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 230 else if (PDC_IS_262(sc)) 231 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 232 else 233 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 234 sc->sc_wdcdev.sc_atac.atac_set_modes = PDC_IS_268(sc) ? 235 pdc20268_setup_channel : pdc202xx_setup_channel; 236 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 237 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 238 sc->sc_wdcdev.wdc_maxdrives = 2; 239 240 wdc_allocate_regs(&sc->sc_wdcdev); 241 242 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || 243 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || 244 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265) { 245 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 246 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 247 } 248 249 if (!PDC_IS_268(sc)) { 250 /* setup failsafe defaults */ 251 mode = 0; 252 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 253 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 254 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 255 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 256 for (channel = 0; 257 channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 258 channel++) { 259 ATADEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 260 "drive 0 initial timings 0x%x, now 0x%x\n", 261 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 262 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 263 DEBUG_PROBE); 264 pci_conf_write(sc->sc_pc, sc->sc_tag, 265 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 266 ATADEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 267 "drive 1 initial timings 0x%x, now 0x%x\n", 268 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 269 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 270 pci_conf_write(sc->sc_pc, sc->sc_tag, 271 PDC2xx_TIM(channel, 1), mode); 272 } 273 274 mode = PDC2xx_SCR_DMA; 275 if (PDC_IS_265(sc)) { 276 mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT); 277 } else if (PDC_IS_262(sc)) { 278 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 279 } else { 280 /* the BIOS set it up this way */ 281 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 282 } 283 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 284 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 285 ATADEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 286 "now 0x%x\n", 287 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 288 PDC2xx_SCR), 289 mode), DEBUG_PROBE); 290 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 291 PDC2xx_SCR, mode); 292 293 /* controller initial state register is OK even without BIOS */ 294 /* Set DMA mode to IDE DMA compatibility */ 295 mode = 296 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 297 ATADEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 298 DEBUG_PROBE); 299 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 300 mode | 0x1); 301 mode = 302 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 303 ATADEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 304 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 305 mode | 0x1); 306 } 307 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 308 channel++) { 309 cp = &sc->pciide_channels[channel]; 310 if (pciide_chansetup(sc, channel, interface) == 0) 311 continue; 312 if ((st & (PDC_IS_262(sc) ? 313 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 314 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 315 "%s channel ignored (disabled)\n", cp->name); 316 cp->ata_channel.ch_flags |= ATACH_DISABLED; 317 continue; 318 } 319 pciide_mapchan(pa, cp, interface, 320 PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr); 321 /* clear interrupt, in case there is one pending */ 322 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 323 IDEDMA_CTL_INTR); 324 } 325 return; 326 } 327 328 static void 329 pdc202xx_setup_channel(struct ata_channel *chp) 330 { 331 struct ata_drive_datas *drvp; 332 int drive, s; 333 pcireg_t mode, st; 334 u_int32_t idedma_ctl, scr, atapi; 335 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 336 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 337 int channel = chp->ch_channel; 338 339 /* setup DMA if needed */ 340 pciide_channel_dma_setup(cp); 341 342 idedma_ctl = 0; 343 ATADEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 344 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 345 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 346 DEBUG_PROBE); 347 348 /* Per channel settings */ 349 if (PDC_IS_262(sc)) { 350 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 351 PDC262_U66); 352 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 353 /* Trim UDMA mode */ 354 if ((st & PDC262_STATE_80P(channel)) != 0 || 355 (chp->ch_drive[0].drive_flags & ATA_DRIVE_UDMA && 356 chp->ch_drive[0].UDMA_mode <= 2) || 357 (chp->ch_drive[1].drive_flags & ATA_DRIVE_UDMA && 358 chp->ch_drive[1].UDMA_mode <= 2)) { 359 if (chp->ch_drive[0].UDMA_mode > 2) 360 chp->ch_drive[0].UDMA_mode = 2; 361 if (chp->ch_drive[1].UDMA_mode > 2) 362 chp->ch_drive[1].UDMA_mode = 2; 363 } 364 /* Set U66 if needed */ 365 if ((chp->ch_drive[0].drive_flags & ATA_DRIVE_UDMA && 366 chp->ch_drive[0].UDMA_mode > 2) || 367 (chp->ch_drive[1].drive_flags & ATA_DRIVE_UDMA && 368 chp->ch_drive[1].UDMA_mode > 2)) 369 scr |= PDC262_U66_EN(channel); 370 else 371 scr &= ~PDC262_U66_EN(channel); 372 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 373 PDC262_U66, scr); 374 ATADEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 375 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 376 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 377 PDC262_ATAPI(channel))), DEBUG_PROBE); 378 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATAPI || 379 chp->ch_drive[1].drive_type == ATA_DRIVET_ATAPI) { 380 if (((chp->ch_drive[0].drive_flags & ATA_DRIVE_UDMA) && 381 !(chp->ch_drive[1].drive_flags & ATA_DRIVE_UDMA) && 382 (chp->ch_drive[1].drive_flags & ATA_DRIVE_DMA)) || 383 ((chp->ch_drive[1].drive_flags & ATA_DRIVE_UDMA) && 384 !(chp->ch_drive[0].drive_flags & ATA_DRIVE_UDMA) && 385 (chp->ch_drive[0].drive_flags & ATA_DRIVE_DMA))) 386 atapi = 0; 387 else 388 atapi = PDC262_ATAPI_UDMA; 389 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 390 PDC262_ATAPI(channel), atapi); 391 } 392 } 393 for (drive = 0; drive < 2; drive++) { 394 drvp = &chp->ch_drive[drive]; 395 /* If no drive, skip */ 396 if (drvp->drive_type == ATA_DRIVET_NONE) 397 continue; 398 mode = 0; 399 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 400 /* use Ultra/DMA */ 401 s = splbio(); 402 drvp->drive_flags &= ~ATA_DRIVE_DMA; 403 splx(s); 404 mode = PDC2xx_TIM_SET_MB(mode, 405 pdc2xx_udma_mb[drvp->UDMA_mode]); 406 mode = PDC2xx_TIM_SET_MC(mode, 407 pdc2xx_udma_mc[drvp->UDMA_mode]); 408 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 409 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 410 mode = PDC2xx_TIM_SET_MB(mode, 411 pdc2xx_dma_mb[drvp->DMA_mode]); 412 mode = PDC2xx_TIM_SET_MC(mode, 413 pdc2xx_dma_mc[drvp->DMA_mode]); 414 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 415 } else { 416 mode = PDC2xx_TIM_SET_MB(mode, 417 pdc2xx_dma_mb[0]); 418 mode = PDC2xx_TIM_SET_MC(mode, 419 pdc2xx_dma_mc[0]); 420 } 421 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 422 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 423 if (drvp->drive_type == ATA_DRIVET_ATA) 424 mode |= PDC2xx_TIM_PRE; 425 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 426 if (drvp->PIO_mode >= 3) { 427 mode |= PDC2xx_TIM_IORDY; 428 if (drive == 0) 429 mode |= PDC2xx_TIM_IORDYp; 430 } 431 ATADEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 432 "timings 0x%x\n", 433 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 434 chp->ch_channel, drive, mode), DEBUG_PROBE); 435 pci_conf_write(sc->sc_pc, sc->sc_tag, 436 PDC2xx_TIM(chp->ch_channel, drive), mode); 437 } 438 if (idedma_ctl != 0) { 439 /* Add software bits in status register */ 440 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 441 0, idedma_ctl); 442 } 443 } 444 445 static void 446 pdc20268_setup_channel(struct ata_channel *chp) 447 { 448 struct ata_drive_datas *drvp; 449 int drive, s; 450 u_int32_t idedma_ctl; 451 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 452 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 453 int u100; 454 455 /* setup DMA if needed */ 456 pciide_channel_dma_setup(cp); 457 458 idedma_ctl = 0; 459 460 /* I don't know what this is for, FreeBSD does it ... */ 461 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 462 IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * chp->ch_channel, 0x0b); 463 464 /* 465 * cable type detect, from FreeBSD 466 */ 467 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 468 IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * chp->ch_channel) & 0x04) ? 469 0 : 1; 470 471 for (drive = 0; drive < 2; drive++) { 472 drvp = &chp->ch_drive[drive]; 473 /* If no drive, skip */ 474 if (drvp->drive_type == ATA_DRIVET_NONE) 475 continue; 476 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 477 /* use Ultra/DMA */ 478 s = splbio(); 479 drvp->drive_flags &= ~ATA_DRIVE_DMA; 480 splx(s); 481 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 482 if (drvp->UDMA_mode > 2 && u100 == 0) 483 drvp->UDMA_mode = 2; 484 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 485 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 486 } 487 } 488 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 489 if (idedma_ctl != 0) { 490 /* Add software bits in status register */ 491 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 492 0, idedma_ctl); 493 } 494 } 495 496 static int 497 pdc202xx_pci_intr(void *arg) 498 { 499 struct pciide_softc *sc = arg; 500 struct pciide_channel *cp; 501 struct ata_channel *wdc_cp; 502 int i, rv, crv; 503 u_int32_t scr; 504 505 rv = 0; 506 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 507 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 508 cp = &sc->pciide_channels[i]; 509 wdc_cp = &cp->ata_channel; 510 /* If a compat channel skip. */ 511 if (cp->compat) 512 continue; 513 if (scr & PDC2xx_SCR_INT(i)) { 514 crv = wdcintr(wdc_cp); 515 if (crv == 0) 516 aprint_error("%s:%d: bogus intr (reg 0x%x)\n", 517 device_xname( 518 sc->sc_wdcdev.sc_atac.atac_dev), i, scr); 519 else 520 rv = 1; 521 } 522 } 523 return rv; 524 } 525 526 static int 527 pdc20265_pci_intr(void *arg) 528 { 529 struct pciide_softc *sc = arg; 530 struct pciide_channel *cp; 531 struct ata_channel *wdc_cp; 532 int i, rv, crv; 533 u_int32_t dmastat; 534 535 rv = 0; 536 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 537 cp = &sc->pciide_channels[i]; 538 wdc_cp = &cp->ata_channel; 539 /* If a compat channel skip. */ 540 if (cp->compat) 541 continue; 542 #if 0 543 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * i, 0x0b); 544 if ((bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * i) & 0x20) == 0) 545 continue; 546 #endif 547 /* 548 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 549 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 550 * So use it instead (requires 2 reg reads instead of 1, 551 * but we can't do it another way). 552 */ 553 dmastat = bus_space_read_1(sc->sc_dma_iot, 554 cp->dma_iohs[IDEDMA_CTL], 0); 555 if((dmastat & IDEDMA_CTL_INTR) == 0) 556 continue; 557 crv = wdcintr(wdc_cp); 558 if (crv == 0) 559 aprint_error("%s:%d: bogus intr\n", 560 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), i); 561 else 562 rv = 1; 563 } 564 return rv; 565 } 566 567 static void 568 pdc20262_dma_start(void *v, int channel, int drive) 569 { 570 struct pciide_softc *sc = v; 571 struct pciide_dma_maps *dma_maps = 572 &sc->pciide_channels[channel].dma_maps[drive]; 573 int atapi; 574 575 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 576 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ? 577 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 578 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1; 579 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 580 PDC262_ATAPI(channel), atapi); 581 } 582 583 pciide_dma_start(v, channel, drive); 584 } 585 586 static int 587 pdc20262_dma_finish(void *v, int channel, int drive, int force) 588 { 589 struct pciide_softc *sc = v; 590 struct pciide_dma_maps *dma_maps = 591 &sc->pciide_channels[channel].dma_maps[drive]; 592 struct ata_channel *chp; 593 int atapi, error; 594 595 error = pciide_dma_finish(v, channel, drive, force); 596 597 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 598 chp = sc->wdc_chanarray[channel]; 599 atapi = 0; 600 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATAPI || 601 chp->ch_drive[1].drive_type == ATA_DRIVET_ATAPI) { 602 if ((!(chp->ch_drive[0].drive_flags & ATA_DRIVE_UDMA) || 603 (chp->ch_drive[1].drive_flags & ATA_DRIVE_UDMA) || 604 !(chp->ch_drive[1].drive_flags & ATA_DRIVE_DMA)) && 605 (!(chp->ch_drive[1].drive_flags & ATA_DRIVE_UDMA) || 606 (chp->ch_drive[0].drive_flags & ATA_DRIVE_UDMA) || 607 !(chp->ch_drive[0].drive_flags & ATA_DRIVE_DMA))) 608 atapi = PDC262_ATAPI_UDMA; 609 } 610 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 611 PDC262_ATAPI(channel), atapi); 612 } 613 614 return error; 615 } 616
Indexes created Thu Oct 02 14:10:14 GMT 2025