pdcide.c revision 1.4
1 /* $NetBSD: pdcide.c,v 1.4 2003/10/24 00:24:15 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_pdc202xx_reg.h> 40 41 static void pdc202xx_chip_map(struct pciide_softc *, struct pci_attach_args *); 42 static void pdc202xx_setup_channel(struct channel_softc *); 43 static void pdc20268_setup_channel(struct channel_softc *); 44 static int pdc202xx_pci_intr(void *); 45 static int pdc20265_pci_intr(void *); 46 static void pdc20262_dma_start(void *, int, int); 47 static int pdc20262_dma_finish(void *, int, int, int); 48 49 static int pdcide_match(struct device *, struct cfdata *, void *); 50 static void pdcide_attach(struct device *, struct device *, void *); 51 52 CFATTACH_DECL(pdcide, sizeof(struct pciide_softc), 53 pdcide_match, pdcide_attach, NULL, NULL); 54 55 static const struct pciide_product_desc pciide_promise_products[] = { 56 { PCI_PRODUCT_PROMISE_ULTRA33, 57 0, 58 "Promise Ultra33/ATA Bus Master IDE Accelerator", 59 pdc202xx_chip_map, 60 }, 61 { PCI_PRODUCT_PROMISE_ULTRA66, 62 0, 63 "Promise Ultra66/ATA Bus Master IDE Accelerator", 64 pdc202xx_chip_map, 65 }, 66 { PCI_PRODUCT_PROMISE_ULTRA100, 67 0, 68 "Promise Ultra100/ATA Bus Master IDE Accelerator", 69 pdc202xx_chip_map, 70 }, 71 { PCI_PRODUCT_PROMISE_ULTRA100X, 72 0, 73 "Promise Ultra100/ATA Bus Master IDE Accelerator", 74 pdc202xx_chip_map, 75 }, 76 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 77 0, 78 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 79 pdc202xx_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 82 0, 83 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 84 pdc202xx_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_ULTRA133, 87 0, 88 "Promise Ultra133/ATA Bus Master IDE Accelerator", 89 pdc202xx_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 92 0, 93 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 94 pdc202xx_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_MBULTRA133, 97 0, 98 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 99 pdc202xx_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 102 0, 103 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 104 pdc202xx_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_FASTTRAK133LITE, 107 0, 108 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 109 pdc202xx_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_SATA150TX2PLUS, 112 0, 113 "Promise Serial ATA/150 TX2plus Bus Master IDE Accelerator", 114 pdc202xx_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_SATA150FT378, 117 0, 118 "Promise FastTrak 378 Serial ATA/150 Bus Master IDE Controller", 119 pdc202xx_chip_map, 120 }, 121 { 0, 122 0, 123 NULL, 124 NULL 125 } 126 }; 127 128 static int 129 pdcide_match(struct device *parent, struct cfdata *match, void *aux) 130 { 131 struct pci_attach_args *pa = aux; 132 133 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 134 if (pciide_lookup_product(pa->pa_id, pciide_promise_products)) 135 return (2); 136 } 137 return (0); 138 } 139 140 static void 141 pdcide_attach(struct device *parent, struct device *self, void *aux) 142 { 143 struct pci_attach_args *pa = aux; 144 struct pciide_softc *sc = (struct pciide_softc *)self; 145 146 pciide_common_attach(sc, pa, 147 pciide_lookup_product(pa->pa_id, pciide_promise_products)); 148 149 } 150 151 /* Macros to test product */ 152 #define PDC_IS_262(sc) \ 153 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 154 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 155 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 156 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 157 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 158 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 159 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 160 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 161 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 162 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 163 #define PDC_IS_265(sc) \ 164 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 165 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 166 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 167 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 168 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 169 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 170 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 171 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 172 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 173 #define PDC_IS_268(sc) \ 174 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 175 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 176 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 177 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 178 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 179 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 180 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 181 #define PDC_IS_276(sc) \ 182 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 183 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 184 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 185 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 186 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 187 188 static void 189 pdc202xx_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 190 { 191 struct pciide_channel *cp; 192 int channel; 193 pcireg_t interface, st, mode; 194 bus_size_t cmdsize, ctlsize; 195 196 if (!PDC_IS_268(sc)) { 197 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 198 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 199 st), DEBUG_PROBE); 200 } 201 if (pciide_chipen(sc, pa) == 0) 202 return; 203 204 /* turn off RAID mode */ 205 if (!PDC_IS_268(sc)) 206 st &= ~PDC2xx_STATE_IDERAID; 207 208 /* 209 * can't rely on the PCI_CLASS_REG content if the chip was in raid 210 * mode. We have to fake interface 211 */ 212 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 213 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 214 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 215 216 aprint_normal("%s: bus-master DMA support present", 217 sc->sc_wdcdev.sc_dev.dv_xname); 218 pciide_mapreg_dma(sc, pa); 219 aprint_normal("\n"); 220 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 221 WDC_CAPABILITY_MODE; 222 if (sc->sc_dma_ok) { 223 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 224 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 225 sc->sc_wdcdev.irqack = pciide_irqack; 226 } 227 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 228 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 229 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 230 sc->sc_wdcdev.PIO_cap = 4; 231 sc->sc_wdcdev.DMA_cap = 2; 232 if (PDC_IS_276(sc)) 233 sc->sc_wdcdev.UDMA_cap = 6; 234 else if (PDC_IS_265(sc)) 235 sc->sc_wdcdev.UDMA_cap = 5; 236 else if (PDC_IS_262(sc)) 237 sc->sc_wdcdev.UDMA_cap = 4; 238 else 239 sc->sc_wdcdev.UDMA_cap = 2; 240 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 241 pdc20268_setup_channel : pdc202xx_setup_channel; 242 sc->sc_wdcdev.channels = sc->wdc_chanarray; 243 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 244 245 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || 246 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || 247 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) { 248 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 249 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 250 } 251 252 if (!PDC_IS_268(sc)) { 253 /* setup failsafe defaults */ 254 mode = 0; 255 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 256 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 257 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 258 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 259 for (channel = 0; 260 channel < sc->sc_wdcdev.nchannels; 261 channel++) { 262 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 263 "drive 0 initial timings 0x%x, now 0x%x\n", 264 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 265 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 266 DEBUG_PROBE); 267 pci_conf_write(sc->sc_pc, sc->sc_tag, 268 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 269 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 270 "drive 1 initial timings 0x%x, now 0x%x\n", 271 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 272 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 273 pci_conf_write(sc->sc_pc, sc->sc_tag, 274 PDC2xx_TIM(channel, 1), mode); 275 } 276 277 mode = PDC2xx_SCR_DMA; 278 if (PDC_IS_265(sc)) { 279 mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT); 280 } else if (PDC_IS_262(sc)) { 281 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 282 } else { 283 /* the BIOS set it up this way */ 284 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 285 } 286 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 287 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 288 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 289 "now 0x%x\n", 290 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 291 PDC2xx_SCR), 292 mode), DEBUG_PROBE); 293 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 294 PDC2xx_SCR, mode); 295 296 /* controller initial state register is OK even without BIOS */ 297 /* Set DMA mode to IDE DMA compatibility */ 298 mode = 299 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 300 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 301 DEBUG_PROBE); 302 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 303 mode | 0x1); 304 mode = 305 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 306 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 307 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 308 mode | 0x1); 309 } 310 311 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 312 cp = &sc->pciide_channels[channel]; 313 if (pciide_chansetup(sc, channel, interface) == 0) 314 continue; 315 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 316 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 317 aprint_normal("%s: %s channel ignored (disabled)\n", 318 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 319 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 320 continue; 321 } 322 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 323 PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr); 324 } 325 if (!PDC_IS_268(sc)) { 326 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 327 "0x%x\n", st), DEBUG_PROBE); 328 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 329 } 330 return; 331 } 332 333 static void 334 pdc202xx_setup_channel(struct channel_softc *chp) 335 { 336 struct ata_drive_datas *drvp; 337 int drive; 338 pcireg_t mode, st; 339 u_int32_t idedma_ctl, scr, atapi; 340 struct pciide_channel *cp = (struct pciide_channel*)chp; 341 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 342 int channel = chp->channel; 343 344 /* setup DMA if needed */ 345 pciide_channel_dma_setup(cp); 346 347 idedma_ctl = 0; 348 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 349 sc->sc_wdcdev.sc_dev.dv_xname, 350 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 351 DEBUG_PROBE); 352 353 /* Per channel settings */ 354 if (PDC_IS_262(sc)) { 355 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 356 PDC262_U66); 357 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 358 /* Trim UDMA mode */ 359 if ((st & PDC262_STATE_80P(channel)) != 0 || 360 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 361 chp->ch_drive[0].UDMA_mode <= 2) || 362 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 363 chp->ch_drive[1].UDMA_mode <= 2)) { 364 if (chp->ch_drive[0].UDMA_mode > 2) 365 chp->ch_drive[0].UDMA_mode = 2; 366 if (chp->ch_drive[1].UDMA_mode > 2) 367 chp->ch_drive[1].UDMA_mode = 2; 368 } 369 /* Set U66 if needed */ 370 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 371 chp->ch_drive[0].UDMA_mode > 2) || 372 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 373 chp->ch_drive[1].UDMA_mode > 2)) 374 scr |= PDC262_U66_EN(channel); 375 else 376 scr &= ~PDC262_U66_EN(channel); 377 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 378 PDC262_U66, scr); 379 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 380 sc->sc_wdcdev.sc_dev.dv_xname, channel, 381 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 382 PDC262_ATAPI(channel))), DEBUG_PROBE); 383 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 384 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 385 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 386 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 387 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 388 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 389 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 390 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 391 atapi = 0; 392 else 393 atapi = PDC262_ATAPI_UDMA; 394 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 395 PDC262_ATAPI(channel), atapi); 396 } 397 } 398 for (drive = 0; drive < 2; drive++) { 399 drvp = &chp->ch_drive[drive]; 400 /* If no drive, skip */ 401 if ((drvp->drive_flags & DRIVE) == 0) 402 continue; 403 mode = 0; 404 if (drvp->drive_flags & DRIVE_UDMA) { 405 /* use Ultra/DMA */ 406 drvp->drive_flags &= ~DRIVE_DMA; 407 mode = PDC2xx_TIM_SET_MB(mode, 408 pdc2xx_udma_mb[drvp->UDMA_mode]); 409 mode = PDC2xx_TIM_SET_MC(mode, 410 pdc2xx_udma_mc[drvp->UDMA_mode]); 411 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 412 } else if (drvp->drive_flags & DRIVE_DMA) { 413 mode = PDC2xx_TIM_SET_MB(mode, 414 pdc2xx_dma_mb[drvp->DMA_mode]); 415 mode = PDC2xx_TIM_SET_MC(mode, 416 pdc2xx_dma_mc[drvp->DMA_mode]); 417 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 418 } else { 419 mode = PDC2xx_TIM_SET_MB(mode, 420 pdc2xx_dma_mb[0]); 421 mode = PDC2xx_TIM_SET_MC(mode, 422 pdc2xx_dma_mc[0]); 423 } 424 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 425 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 426 if (drvp->drive_flags & DRIVE_ATA) 427 mode |= PDC2xx_TIM_PRE; 428 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 429 if (drvp->PIO_mode >= 3) { 430 mode |= PDC2xx_TIM_IORDY; 431 if (drive == 0) 432 mode |= PDC2xx_TIM_IORDYp; 433 } 434 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 435 "timings 0x%x\n", 436 sc->sc_wdcdev.sc_dev.dv_xname, 437 chp->channel, drive, mode), DEBUG_PROBE); 438 pci_conf_write(sc->sc_pc, sc->sc_tag, 439 PDC2xx_TIM(chp->channel, drive), mode); 440 } 441 if (idedma_ctl != 0) { 442 /* Add software bits in status register */ 443 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 444 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 445 idedma_ctl); 446 } 447 } 448 449 static void 450 pdc20268_setup_channel(struct channel_softc *chp) 451 { 452 struct ata_drive_datas *drvp; 453 int drive; 454 u_int32_t idedma_ctl; 455 struct pciide_channel *cp = (struct pciide_channel*)chp; 456 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 457 int u100; 458 459 /* setup DMA if needed */ 460 pciide_channel_dma_setup(cp); 461 462 idedma_ctl = 0; 463 464 /* I don't know what this is for, FreeBSD does it ... */ 465 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 466 IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * chp->channel, 0x0b); 467 468 /* 469 * cable type detect, from FreeBSD 470 */ 471 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 472 IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * chp->channel) & 0x04) ? 473 0 : 1; 474 475 for (drive = 0; drive < 2; drive++) { 476 drvp = &chp->ch_drive[drive]; 477 /* If no drive, skip */ 478 if ((drvp->drive_flags & DRIVE) == 0) 479 continue; 480 if (drvp->drive_flags & DRIVE_UDMA) { 481 /* use Ultra/DMA */ 482 drvp->drive_flags &= ~DRIVE_DMA; 483 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 484 if (drvp->UDMA_mode > 2 && u100 == 0) 485 drvp->UDMA_mode = 2; 486 } else if (drvp->drive_flags & DRIVE_DMA) { 487 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 488 } 489 } 490 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 491 if (idedma_ctl != 0) { 492 /* Add software bits in status register */ 493 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 494 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 495 idedma_ctl); 496 } 497 } 498 499 static int 500 pdc202xx_pci_intr(void *arg) 501 { 502 struct pciide_softc *sc = arg; 503 struct pciide_channel *cp; 504 struct channel_softc *wdc_cp; 505 int i, rv, crv; 506 u_int32_t scr; 507 508 rv = 0; 509 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 510 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 511 cp = &sc->pciide_channels[i]; 512 wdc_cp = &cp->wdc_channel; 513 /* If a compat channel skip. */ 514 if (cp->compat) 515 continue; 516 if (scr & PDC2xx_SCR_INT(i)) { 517 crv = wdcintr(wdc_cp); 518 if (crv == 0) 519 printf("%s:%d: bogus intr (reg 0x%x)\n", 520 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 521 else 522 rv = 1; 523 } 524 } 525 return rv; 526 } 527 528 static int 529 pdc20265_pci_intr(void *arg) 530 { 531 struct pciide_softc *sc = arg; 532 struct pciide_channel *cp; 533 struct channel_softc *wdc_cp; 534 int i, rv, crv; 535 u_int32_t dmastat; 536 537 rv = 0; 538 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 539 cp = &sc->pciide_channels[i]; 540 wdc_cp = &cp->wdc_channel; 541 /* If a compat channel skip. */ 542 if (cp->compat) 543 continue; 544 #if 0 545 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * i, 0x0b); 546 if ((bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * i) & 0x20) == 0) 547 continue; 548 #endif 549 /* 550 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 551 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 552 * So use it instead (requires 2 reg reads instead of 1, 553 * but we can't do it another way). 554 */ 555 dmastat = bus_space_read_1(sc->sc_dma_iot, 556 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 557 if((dmastat & IDEDMA_CTL_INTR) == 0) 558 continue; 559 crv = wdcintr(wdc_cp); 560 if (crv == 0) 561 printf("%s:%d: bogus intr\n", 562 sc->sc_wdcdev.sc_dev.dv_xname, i); 563 else 564 rv = 1; 565 } 566 return rv; 567 } 568 569 static void 570 pdc20262_dma_start(void *v, int channel, int drive) 571 { 572 struct pciide_softc *sc = v; 573 struct pciide_dma_maps *dma_maps = 574 &sc->pciide_channels[channel].dma_maps[drive]; 575 int atapi; 576 577 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 578 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ? 579 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 580 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1; 581 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 582 PDC262_ATAPI(channel), atapi); 583 } 584 585 pciide_dma_start(v, channel, drive); 586 } 587 588 static int 589 pdc20262_dma_finish(void *v, int channel, int drive, int force) 590 { 591 struct pciide_softc *sc = v; 592 struct pciide_dma_maps *dma_maps = 593 &sc->pciide_channels[channel].dma_maps[drive]; 594 struct channel_softc *chp; 595 int atapi, error; 596 597 error = pciide_dma_finish(v, channel, drive, force); 598 599 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 600 chp = sc->wdc_chanarray[channel]; 601 atapi = 0; 602 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 603 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 604 if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 605 (chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 606 !(chp->ch_drive[1].drive_flags & DRIVE_DMA)) && 607 (!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 608 (chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 609 !(chp->ch_drive[0].drive_flags & DRIVE_DMA))) 610 atapi = PDC262_ATAPI_UDMA; 611 } 612 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 613 PDC262_ATAPI(channel), atapi); 614 } 615 616 return error; 617 } 618
Indexes created Fri Oct 03 02:09:57 GMT 2025