pdcide.c revision 1.7
1 /* $NetBSD: pdcide.c,v 1.7 2003/11/15 16:40:46 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_pdc202xx_reg.h> 40 41 static void pdc202xx_chip_map(struct pciide_softc *, struct pci_attach_args *); 42 static void pdc202xx_setup_channel(struct channel_softc *); 43 static void pdc20268_setup_channel(struct channel_softc *); 44 static int pdc202xx_pci_intr(void *); 45 static int pdc20265_pci_intr(void *); 46 static void pdc20262_dma_start(void *, int, int); 47 static int pdc20262_dma_finish(void *, int, int, int); 48 49 static int pdcide_match(struct device *, struct cfdata *, void *); 50 static void pdcide_attach(struct device *, struct device *, void *); 51 52 CFATTACH_DECL(pdcide, sizeof(struct pciide_softc), 53 pdcide_match, pdcide_attach, NULL, NULL); 54 55 static const struct pciide_product_desc pciide_promise_products[] = { 56 { PCI_PRODUCT_PROMISE_ULTRA33, 57 0, 58 "Promise Ultra33/ATA Bus Master IDE Accelerator", 59 pdc202xx_chip_map, 60 }, 61 { PCI_PRODUCT_PROMISE_ULTRA66, 62 0, 63 "Promise Ultra66/ATA Bus Master IDE Accelerator", 64 pdc202xx_chip_map, 65 }, 66 { PCI_PRODUCT_PROMISE_ULTRA100, 67 0, 68 "Promise Ultra100/ATA Bus Master IDE Accelerator", 69 pdc202xx_chip_map, 70 }, 71 { PCI_PRODUCT_PROMISE_ULTRA100X, 72 0, 73 "Promise Ultra100/ATA Bus Master IDE Accelerator", 74 pdc202xx_chip_map, 75 }, 76 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 77 0, 78 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 79 pdc202xx_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 82 0, 83 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 84 pdc202xx_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_ULTRA133, 87 0, 88 "Promise Ultra133/ATA Bus Master IDE Accelerator", 89 pdc202xx_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 92 0, 93 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 94 pdc202xx_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_MBULTRA133, 97 0, 98 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 99 pdc202xx_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 102 0, 103 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 104 pdc202xx_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_FASTTRAK133LITE, 107 0, 108 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 109 pdc202xx_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_SATA150TX2PLUS, 112 0, 113 "Promise Serial ATA/150 TX2plus Bus Master IDE Accelerator", 114 pdc202xx_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_SATA150FT378, 117 0, 118 "Promise FastTrak 378 Serial ATA/150 Bus Master IDE Controller", 119 pdc202xx_chip_map, 120 }, 121 { 0, 122 0, 123 NULL, 124 NULL 125 } 126 }; 127 128 static int 129 pdcide_match(struct device *parent, struct cfdata *match, void *aux) 130 { 131 struct pci_attach_args *pa = aux; 132 133 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 134 if (pciide_lookup_product(pa->pa_id, pciide_promise_products)) 135 return (2); 136 } 137 return (0); 138 } 139 140 static void 141 pdcide_attach(struct device *parent, struct device *self, void *aux) 142 { 143 struct pci_attach_args *pa = aux; 144 struct pciide_softc *sc = (struct pciide_softc *)self; 145 146 pciide_common_attach(sc, pa, 147 pciide_lookup_product(pa->pa_id, pciide_promise_products)); 148 149 } 150 151 /* Macros to test product */ 152 #define PDC_IS_262(sc) \ 153 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 154 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 155 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 156 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 157 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 158 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 159 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 160 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 161 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 162 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 163 #define PDC_IS_265(sc) \ 164 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 165 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 166 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 167 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 168 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 169 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 170 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 171 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 172 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 173 #define PDC_IS_268(sc) \ 174 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 175 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 176 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 177 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 178 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 179 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 180 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 181 #define PDC_IS_276(sc) \ 182 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 183 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 184 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 185 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 186 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 187 188 static void 189 pdc202xx_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 190 { 191 struct pciide_channel *cp; 192 int channel; 193 pcireg_t interface, st, mode; 194 bus_size_t cmdsize, ctlsize; 195 196 if (!PDC_IS_268(sc)) { 197 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 198 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 199 st), DEBUG_PROBE); 200 /* turn off RAID mode */ 201 if (st & PDC2xx_STATE_IDERAID) { 202 WDCDEBUG_PRINT(("pdc202xx_setup_chip: turning off RAID mode\n"), DEBUG_PROBE); 203 st &= ~PDC2xx_STATE_IDERAID; 204 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 205 } 206 } else 207 st = PDC2xx_STATE_NATIVE | PDC262_STATE_EN(0) | PDC262_STATE_EN(1); 208 209 if (pciide_chipen(sc, pa) == 0) 210 return; 211 212 /* 213 * can't rely on the PCI_CLASS_REG content if the chip was in raid 214 * mode. We have to fake interface 215 */ 216 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 217 if (st & PDC2xx_STATE_NATIVE) 218 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 219 220 aprint_normal("%s: bus-master DMA support present", 221 sc->sc_wdcdev.sc_dev.dv_xname); 222 pciide_mapreg_dma(sc, pa); 223 aprint_normal("\n"); 224 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 225 WDC_CAPABILITY_MODE; 226 if (sc->sc_dma_ok) { 227 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 228 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 229 sc->sc_wdcdev.irqack = pciide_irqack; 230 } 231 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 232 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 233 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 234 sc->sc_wdcdev.PIO_cap = 4; 235 sc->sc_wdcdev.DMA_cap = 2; 236 if (PDC_IS_276(sc)) 237 sc->sc_wdcdev.UDMA_cap = 6; 238 else if (PDC_IS_265(sc)) 239 sc->sc_wdcdev.UDMA_cap = 5; 240 else if (PDC_IS_262(sc)) 241 sc->sc_wdcdev.UDMA_cap = 4; 242 else 243 sc->sc_wdcdev.UDMA_cap = 2; 244 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 245 pdc20268_setup_channel : pdc202xx_setup_channel; 246 sc->sc_wdcdev.channels = sc->wdc_chanarray; 247 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 248 249 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || 250 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || 251 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) { 252 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 253 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 254 } 255 256 if (!PDC_IS_268(sc)) { 257 /* setup failsafe defaults */ 258 mode = 0; 259 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 260 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 261 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 262 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 263 for (channel = 0; 264 channel < sc->sc_wdcdev.nchannels; 265 channel++) { 266 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 267 "drive 0 initial timings 0x%x, now 0x%x\n", 268 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 269 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 270 DEBUG_PROBE); 271 pci_conf_write(sc->sc_pc, sc->sc_tag, 272 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 273 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 274 "drive 1 initial timings 0x%x, now 0x%x\n", 275 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 276 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 277 pci_conf_write(sc->sc_pc, sc->sc_tag, 278 PDC2xx_TIM(channel, 1), mode); 279 } 280 281 mode = PDC2xx_SCR_DMA; 282 if (PDC_IS_265(sc)) { 283 mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT); 284 } else if (PDC_IS_262(sc)) { 285 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 286 } else { 287 /* the BIOS set it up this way */ 288 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 289 } 290 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 291 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 292 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 293 "now 0x%x\n", 294 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 295 PDC2xx_SCR), 296 mode), DEBUG_PROBE); 297 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 298 PDC2xx_SCR, mode); 299 300 /* controller initial state register is OK even without BIOS */ 301 /* Set DMA mode to IDE DMA compatibility */ 302 mode = 303 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 304 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 305 DEBUG_PROBE); 306 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 307 mode | 0x1); 308 mode = 309 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 310 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 311 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 312 mode | 0x1); 313 } 314 315 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 316 cp = &sc->pciide_channels[channel]; 317 if (pciide_chansetup(sc, channel, interface) == 0) 318 continue; 319 if ((st & (PDC_IS_262(sc) ? 320 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 321 aprint_normal("%s: %s channel ignored (disabled)\n", 322 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 323 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 324 continue; 325 } 326 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 327 PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr); 328 /* clear interrupt, in case there is one pending */ 329 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 330 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, IDEDMA_CTL_INTR); 331 } 332 return; 333 } 334 335 static void 336 pdc202xx_setup_channel(struct channel_softc *chp) 337 { 338 struct ata_drive_datas *drvp; 339 int drive; 340 pcireg_t mode, st; 341 u_int32_t idedma_ctl, scr, atapi; 342 struct pciide_channel *cp = (struct pciide_channel*)chp; 343 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 344 int channel = chp->channel; 345 346 /* setup DMA if needed */ 347 pciide_channel_dma_setup(cp); 348 349 idedma_ctl = 0; 350 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 351 sc->sc_wdcdev.sc_dev.dv_xname, 352 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 353 DEBUG_PROBE); 354 355 /* Per channel settings */ 356 if (PDC_IS_262(sc)) { 357 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 358 PDC262_U66); 359 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 360 /* Trim UDMA mode */ 361 if ((st & PDC262_STATE_80P(channel)) != 0 || 362 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 363 chp->ch_drive[0].UDMA_mode <= 2) || 364 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 365 chp->ch_drive[1].UDMA_mode <= 2)) { 366 if (chp->ch_drive[0].UDMA_mode > 2) 367 chp->ch_drive[0].UDMA_mode = 2; 368 if (chp->ch_drive[1].UDMA_mode > 2) 369 chp->ch_drive[1].UDMA_mode = 2; 370 } 371 /* Set U66 if needed */ 372 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 373 chp->ch_drive[0].UDMA_mode > 2) || 374 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 375 chp->ch_drive[1].UDMA_mode > 2)) 376 scr |= PDC262_U66_EN(channel); 377 else 378 scr &= ~PDC262_U66_EN(channel); 379 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 380 PDC262_U66, scr); 381 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 382 sc->sc_wdcdev.sc_dev.dv_xname, channel, 383 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 384 PDC262_ATAPI(channel))), DEBUG_PROBE); 385 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 386 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 387 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 388 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 389 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 390 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 391 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 392 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 393 atapi = 0; 394 else 395 atapi = PDC262_ATAPI_UDMA; 396 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 397 PDC262_ATAPI(channel), atapi); 398 } 399 } 400 for (drive = 0; drive < 2; drive++) { 401 drvp = &chp->ch_drive[drive]; 402 /* If no drive, skip */ 403 if ((drvp->drive_flags & DRIVE) == 0) 404 continue; 405 mode = 0; 406 if (drvp->drive_flags & DRIVE_UDMA) { 407 /* use Ultra/DMA */ 408 drvp->drive_flags &= ~DRIVE_DMA; 409 mode = PDC2xx_TIM_SET_MB(mode, 410 pdc2xx_udma_mb[drvp->UDMA_mode]); 411 mode = PDC2xx_TIM_SET_MC(mode, 412 pdc2xx_udma_mc[drvp->UDMA_mode]); 413 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 414 } else if (drvp->drive_flags & DRIVE_DMA) { 415 mode = PDC2xx_TIM_SET_MB(mode, 416 pdc2xx_dma_mb[drvp->DMA_mode]); 417 mode = PDC2xx_TIM_SET_MC(mode, 418 pdc2xx_dma_mc[drvp->DMA_mode]); 419 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 420 } else { 421 mode = PDC2xx_TIM_SET_MB(mode, 422 pdc2xx_dma_mb[0]); 423 mode = PDC2xx_TIM_SET_MC(mode, 424 pdc2xx_dma_mc[0]); 425 } 426 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 427 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 428 if (drvp->drive_flags & DRIVE_ATA) 429 mode |= PDC2xx_TIM_PRE; 430 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 431 if (drvp->PIO_mode >= 3) { 432 mode |= PDC2xx_TIM_IORDY; 433 if (drive == 0) 434 mode |= PDC2xx_TIM_IORDYp; 435 } 436 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 437 "timings 0x%x\n", 438 sc->sc_wdcdev.sc_dev.dv_xname, 439 chp->channel, drive, mode), DEBUG_PROBE); 440 pci_conf_write(sc->sc_pc, sc->sc_tag, 441 PDC2xx_TIM(chp->channel, drive), mode); 442 } 443 if (idedma_ctl != 0) { 444 /* Add software bits in status register */ 445 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 446 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 447 idedma_ctl); 448 } 449 } 450 451 static void 452 pdc20268_setup_channel(struct channel_softc *chp) 453 { 454 struct ata_drive_datas *drvp; 455 int drive; 456 u_int32_t idedma_ctl; 457 struct pciide_channel *cp = (struct pciide_channel*)chp; 458 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 459 int u100; 460 461 /* setup DMA if needed */ 462 pciide_channel_dma_setup(cp); 463 464 idedma_ctl = 0; 465 466 /* I don't know what this is for, FreeBSD does it ... */ 467 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 468 IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * chp->channel, 0x0b); 469 470 /* 471 * cable type detect, from FreeBSD 472 */ 473 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 474 IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * chp->channel) & 0x04) ? 475 0 : 1; 476 477 for (drive = 0; drive < 2; drive++) { 478 drvp = &chp->ch_drive[drive]; 479 /* If no drive, skip */ 480 if ((drvp->drive_flags & DRIVE) == 0) 481 continue; 482 if (drvp->drive_flags & DRIVE_UDMA) { 483 /* use Ultra/DMA */ 484 drvp->drive_flags &= ~DRIVE_DMA; 485 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 486 if (drvp->UDMA_mode > 2 && u100 == 0) 487 drvp->UDMA_mode = 2; 488 } else if (drvp->drive_flags & DRIVE_DMA) { 489 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 490 } 491 } 492 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 493 if (idedma_ctl != 0) { 494 /* Add software bits in status register */ 495 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 496 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 497 idedma_ctl); 498 } 499 } 500 501 static int 502 pdc202xx_pci_intr(void *arg) 503 { 504 struct pciide_softc *sc = arg; 505 struct pciide_channel *cp; 506 struct channel_softc *wdc_cp; 507 int i, rv, crv; 508 u_int32_t scr; 509 510 rv = 0; 511 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 512 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 513 cp = &sc->pciide_channels[i]; 514 wdc_cp = &cp->wdc_channel; 515 /* If a compat channel skip. */ 516 if (cp->compat) 517 continue; 518 if (scr & PDC2xx_SCR_INT(i)) { 519 crv = wdcintr(wdc_cp); 520 if (crv == 0) 521 printf("%s:%d: bogus intr (reg 0x%x)\n", 522 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 523 else 524 rv = 1; 525 } 526 } 527 return rv; 528 } 529 530 static int 531 pdc20265_pci_intr(void *arg) 532 { 533 struct pciide_softc *sc = arg; 534 struct pciide_channel *cp; 535 struct channel_softc *wdc_cp; 536 int i, rv, crv; 537 u_int32_t dmastat; 538 539 rv = 0; 540 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 541 cp = &sc->pciide_channels[i]; 542 wdc_cp = &cp->wdc_channel; 543 /* If a compat channel skip. */ 544 if (cp->compat) 545 continue; 546 #if 0 547 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * i, 0x0b); 548 if ((bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * i) & 0x20) == 0) 549 continue; 550 #endif 551 /* 552 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 553 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 554 * So use it instead (requires 2 reg reads instead of 1, 555 * but we can't do it another way). 556 */ 557 dmastat = bus_space_read_1(sc->sc_dma_iot, 558 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 559 if((dmastat & IDEDMA_CTL_INTR) == 0) 560 continue; 561 crv = wdcintr(wdc_cp); 562 if (crv == 0) 563 printf("%s:%d: bogus intr\n", 564 sc->sc_wdcdev.sc_dev.dv_xname, i); 565 else 566 rv = 1; 567 } 568 return rv; 569 } 570 571 static void 572 pdc20262_dma_start(void *v, int channel, int drive) 573 { 574 struct pciide_softc *sc = v; 575 struct pciide_dma_maps *dma_maps = 576 &sc->pciide_channels[channel].dma_maps[drive]; 577 int atapi; 578 579 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 580 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ? 581 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 582 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1; 583 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 584 PDC262_ATAPI(channel), atapi); 585 } 586 587 pciide_dma_start(v, channel, drive); 588 } 589 590 static int 591 pdc20262_dma_finish(void *v, int channel, int drive, int force) 592 { 593 struct pciide_softc *sc = v; 594 struct pciide_dma_maps *dma_maps = 595 &sc->pciide_channels[channel].dma_maps[drive]; 596 struct channel_softc *chp; 597 int atapi, error; 598 599 error = pciide_dma_finish(v, channel, drive, force); 600 601 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 602 chp = sc->wdc_chanarray[channel]; 603 atapi = 0; 604 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 605 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 606 if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 607 (chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 608 !(chp->ch_drive[1].drive_flags & DRIVE_DMA)) && 609 (!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 610 (chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 611 !(chp->ch_drive[0].drive_flags & DRIVE_DMA))) 612 atapi = PDC262_ATAPI_UDMA; 613 } 614 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 615 PDC262_ATAPI(channel), atapi); 616 } 617 618 return error; 619 } 620
Indexes created Fri Oct 03 02:09:57 GMT 2025