pdcsata.c revision 1.2.2.2
1 1.2.2.2 skrll /* $NetBSD: pdcsata.c,v 1.2.2.2 2004/11/29 07:24:17 skrll Exp $ */ 2 1.2.2.2 skrll 3 1.2.2.2 skrll /* 4 1.2.2.2 skrll * Copyright (c) 2004, Manuel Bouyer. 5 1.2.2.2 skrll * 6 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 7 1.2.2.2 skrll * modification, are permitted provided that the following conditions 8 1.2.2.2 skrll * are met: 9 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 10 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 11 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 12 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 13 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 14 1.2.2.2 skrll * 3. All advertising materials mentioning features or use of this software 15 1.2.2.2 skrll * must display the following acknowledgement: 16 1.2.2.2 skrll * This product includes software developed by Manuel Bouyer. 17 1.2.2.2 skrll * 4. The name of the author may not be used to endorse or promote products 18 1.2.2.2 skrll * derived from this software without specific prior written permission. 19 1.2.2.2 skrll * 20 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 1.2.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 1.2.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 1.2.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 1.2.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 1.2.2.2 skrll * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 1.2.2.2 skrll * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 1.2.2.2 skrll * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 1.2.2.2 skrll * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 1.2.2.2 skrll * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 1.2.2.2 skrll */ 31 1.2.2.2 skrll 32 1.2.2.2 skrll #include <sys/types.h> 33 1.2.2.2 skrll #include <sys/malloc.h> 34 1.2.2.2 skrll #include <sys/param.h> 35 1.2.2.2 skrll #include <sys/systm.h> 36 1.2.2.2 skrll 37 1.2.2.2 skrll #include <dev/pci/pcivar.h> 38 1.2.2.2 skrll #include <dev/pci/pcidevs.h> 39 1.2.2.2 skrll #include <dev/pci/pciidereg.h> 40 1.2.2.2 skrll #include <dev/pci/pciidevar.h> 41 1.2.2.2 skrll 42 1.2.2.2 skrll #define PDC203xx_NCHANNELS 4 43 1.2.2.2 skrll 44 1.2.2.2 skrll #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 45 1.2.2.2 skrll 46 1.2.2.2 skrll static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 1.2.2.2 skrll static void pdc203xx_setup_channel(struct ata_channel *); 48 1.2.2.2 skrll static int pdc203xx_pci_intr(void *); 49 1.2.2.2 skrll static void pdc203xx_irqack(struct ata_channel *); 50 1.2.2.2 skrll static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 51 1.2.2.2 skrll static void pdc203xx_dma_start(void *,int ,int); 52 1.2.2.2 skrll static int pdc203xx_dma_finish(void *, int, int, int); 53 1.2.2.2 skrll 54 1.2.2.2 skrll static int pdcsata_match(struct device *, struct cfdata *, void *); 55 1.2.2.2 skrll static void pdcsata_attach(struct device *, struct device *, void *); 56 1.2.2.2 skrll 57 1.2.2.2 skrll CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 58 1.2.2.2 skrll pdcsata_match, pdcsata_attach, NULL, NULL); 59 1.2.2.2 skrll 60 1.2.2.2 skrll static const struct pciide_product_desc pciide_pdcsata_products[] = { 61 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20318, 62 1.2.2.2 skrll 0, 63 1.2.2.2 skrll "Promise PDC20318 SATA150 controller", 64 1.2.2.2 skrll pdcsata_chip_map, 65 1.2.2.2 skrll }, 66 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20319, 67 1.2.2.2 skrll 0, 68 1.2.2.2 skrll "Promise PDC20319 SATA150 controller", 69 1.2.2.2 skrll pdcsata_chip_map, 70 1.2.2.2 skrll }, 71 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20371, 72 1.2.2.2 skrll 0, 73 1.2.2.2 skrll "Promise PDC20371 SATA150 controller", 74 1.2.2.2 skrll pdcsata_chip_map, 75 1.2.2.2 skrll }, 76 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20375, 77 1.2.2.2 skrll 0, 78 1.2.2.2 skrll "Promise PDC20375 SATA150 controller", 79 1.2.2.2 skrll pdcsata_chip_map, 80 1.2.2.2 skrll }, 81 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20376, 82 1.2.2.2 skrll 0, 83 1.2.2.2 skrll "Promise PDC20376 SATA150 controller", 84 1.2.2.2 skrll pdcsata_chip_map, 85 1.2.2.2 skrll }, 86 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20377, 87 1.2.2.2 skrll 0, 88 1.2.2.2 skrll "Promise PDC20377 SATA150 controller", 89 1.2.2.2 skrll pdcsata_chip_map, 90 1.2.2.2 skrll }, 91 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20378, 92 1.2.2.2 skrll 0, 93 1.2.2.2 skrll "Promise PDC20378 SATA150 controller", 94 1.2.2.2 skrll pdcsata_chip_map, 95 1.2.2.2 skrll }, 96 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20379, 97 1.2.2.2 skrll 0, 98 1.2.2.2 skrll "Promise PDC20379 SATA150 controller", 99 1.2.2.2 skrll pdcsata_chip_map, 100 1.2.2.2 skrll }, 101 1.2.2.2 skrll { 0, 102 1.2.2.2 skrll 0, 103 1.2.2.2 skrll NULL, 104 1.2.2.2 skrll NULL 105 1.2.2.2 skrll } 106 1.2.2.2 skrll }; 107 1.2.2.2 skrll 108 1.2.2.2 skrll static int 109 1.2.2.2 skrll pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 110 1.2.2.2 skrll { 111 1.2.2.2 skrll struct pci_attach_args *pa = aux; 112 1.2.2.2 skrll 113 1.2.2.2 skrll if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 114 1.2.2.2 skrll if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 115 1.2.2.2 skrll return (2); 116 1.2.2.2 skrll } 117 1.2.2.2 skrll return (0); 118 1.2.2.2 skrll } 119 1.2.2.2 skrll 120 1.2.2.2 skrll static void 121 1.2.2.2 skrll pdcsata_attach(struct device *parent, struct device *self, void *aux) 122 1.2.2.2 skrll { 123 1.2.2.2 skrll struct pci_attach_args *pa = aux; 124 1.2.2.2 skrll struct pciide_softc *sc = (struct pciide_softc *)self; 125 1.2.2.2 skrll 126 1.2.2.2 skrll pciide_common_attach(sc, pa, 127 1.2.2.2 skrll pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 128 1.2.2.2 skrll } 129 1.2.2.2 skrll 130 1.2.2.2 skrll static void 131 1.2.2.2 skrll pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 132 1.2.2.2 skrll { 133 1.2.2.2 skrll struct pciide_channel *cp; 134 1.2.2.2 skrll struct ata_channel *wdc_cp; 135 1.2.2.2 skrll struct wdc_regs *wdr; 136 1.2.2.2 skrll int channel, i; 137 1.2.2.2 skrll bus_size_t dmasize; 138 1.2.2.2 skrll pci_intr_handle_t intrhandle; 139 1.2.2.2 skrll const char *intrstr; 140 1.2.2.2 skrll 141 1.2.2.2 skrll /* 142 1.2.2.2 skrll * Promise SATA controllers have 3 or 4 channels, 143 1.2.2.2 skrll * the usual IDE registers are mapped in I/O space, with offsets. 144 1.2.2.2 skrll */ 145 1.2.2.2 skrll if (pci_intr_map(pa, &intrhandle) != 0) { 146 1.2.2.2 skrll aprint_error("%s: couldn't map interrupt\n", 147 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 148 1.2.2.2 skrll return; 149 1.2.2.2 skrll } 150 1.2.2.2 skrll intrstr = pci_intr_string(pa->pa_pc, intrhandle); 151 1.2.2.2 skrll sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 152 1.2.2.2 skrll intrhandle, IPL_BIO, pdc203xx_pci_intr, sc); 153 1.2.2.2 skrll if (sc->sc_pci_ih == NULL) { 154 1.2.2.2 skrll aprint_error("%s: couldn't establish native-PCI interrupt", 155 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 156 1.2.2.2 skrll if (intrstr != NULL) 157 1.2.2.2 skrll aprint_normal(" at %s", intrstr); 158 1.2.2.2 skrll aprint_normal("\n"); 159 1.2.2.2 skrll return; 160 1.2.2.2 skrll } 161 1.2.2.2 skrll aprint_normal("%s: interrupting at %s\n", 162 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 163 1.2.2.2 skrll intrstr ? intrstr : "unknown interrupt"); 164 1.2.2.2 skrll 165 1.2.2.2 skrll sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 166 1.2.2.2 skrll PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 167 1.2.2.2 skrll &sc->sc_dma_ioh, NULL, &dmasize) == 0); 168 1.2.2.2 skrll if (!sc->sc_dma_ok) { 169 1.2.2.2 skrll aprint_error("%s: couldn't map bus-master DMA registers\n", 170 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 171 1.2.2.2 skrll pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 172 1.2.2.2 skrll return; 173 1.2.2.2 skrll } 174 1.2.2.2 skrll 175 1.2.2.2 skrll sc->sc_dmat = pa->pa_dmat; 176 1.2.2.2 skrll 177 1.2.2.2 skrll if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 178 1.2.2.2 skrll PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 179 1.2.2.2 skrll &sc->sc_ba5_sh, NULL, NULL) != 0) { 180 1.2.2.2 skrll aprint_error("%s: couldn't map IDE registers\n", 181 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 182 1.2.2.2 skrll bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 183 1.2.2.2 skrll pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 184 1.2.2.2 skrll return; 185 1.2.2.2 skrll } 186 1.2.2.2 skrll 187 1.2.2.2 skrll aprint_normal("%s: bus-master DMA support present\n", 188 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 189 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 190 1.2.2.2 skrll if (sc->sc_dma_ok) { 191 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 192 1.2.2.2 skrll } 193 1.2.2.2 skrll if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 194 1.2.2.2 skrll PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 195 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 196 1.2.2.2 skrll sc->sc_wdcdev.irqack = pdc203xx_irqack; 197 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 198 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 199 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 200 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 201 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 202 1.2.2.2 skrll bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x06c, 0x00ff0033); 203 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_nchannels = 204 1.2.2.2 skrll (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 205 1.2.2.2 skrll PDC203xx_NCHANNELS : 3; 206 1.2.2.2 skrll wdc_allocate_regs(&sc->sc_wdcdev); 207 1.2.2.2 skrll 208 1.2.2.2 skrll sc->sc_wdcdev.dma_arg = sc; 209 1.2.2.2 skrll sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 210 1.2.2.2 skrll sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 211 1.2.2.2 skrll sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 212 1.2.2.2 skrll 213 1.2.2.2 skrll for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 214 1.2.2.2 skrll channel++) { 215 1.2.2.2 skrll cp = &sc->pciide_channels[channel]; 216 1.2.2.2 skrll sc->wdc_chanarray[channel] = &cp->ata_channel; 217 1.2.2.2 skrll 218 1.2.2.2 skrll cp->ih = sc->sc_pci_ih; 219 1.2.2.2 skrll cp->name = NULL; 220 1.2.2.2 skrll cp->ata_channel.ch_channel = channel; 221 1.2.2.2 skrll cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 222 1.2.2.2 skrll cp->ata_channel.ch_queue = 223 1.2.2.2 skrll malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 224 1.2.2.2 skrll if (cp->ata_channel.ch_queue == NULL) { 225 1.2.2.2 skrll aprint_error("%s channel %d: " 226 1.2.2.2 skrll "can't allocate memory for command queue\n", 227 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 228 1.2.2.2 skrll goto next_channel; 229 1.2.2.2 skrll } 230 1.2.2.2 skrll wdc_cp = &cp->ata_channel; 231 1.2.2.2 skrll wdr = CHAN_TO_WDC_REGS(wdc_cp); 232 1.2.2.2 skrll 233 1.2.2.2 skrll wdr->ctl_iot = sc->sc_ba5_st; 234 1.2.2.2 skrll wdr->cmd_iot = sc->sc_ba5_st; 235 1.2.2.2 skrll 236 1.2.2.2 skrll if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 237 1.2.2.2 skrll 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 238 1.2.2.2 skrll aprint_error("%s: couldn't map channel %d ctl regs\n", 239 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 240 1.2.2.2 skrll channel); 241 1.2.2.2 skrll goto next_channel; 242 1.2.2.2 skrll } 243 1.2.2.2 skrll for (i = 0; i < WDC_NREG; i++) { 244 1.2.2.2 skrll if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 245 1.2.2.2 skrll 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 246 1.2.2.2 skrll &wdr->cmd_iohs[i]) != 0) { 247 1.2.2.2 skrll aprint_error("%s: couldn't map channel %d cmd " 248 1.2.2.2 skrll "regs\n", 249 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 250 1.2.2.2 skrll channel); 251 1.2.2.2 skrll goto next_channel; 252 1.2.2.2 skrll } 253 1.2.2.2 skrll } 254 1.2.2.2 skrll wdc_init_shadow_regs(wdc_cp); 255 1.2.2.2 skrll 256 1.2.2.2 skrll /* 257 1.2.2.2 skrll * subregion de busmaster registers. They're spread all over 258 1.2.2.2 skrll * the controller's register space :(. They are also 4 bytes 259 1.2.2.2 skrll * sized, with some specific extentions in the extra bits. 260 1.2.2.2 skrll * It also seems that the IDEDMA_CTL register isn't available. 261 1.2.2.2 skrll */ 262 1.2.2.2 skrll if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 263 1.2.2.2 skrll 0x260 + (channel << 7), 1, 264 1.2.2.2 skrll &cp->dma_iohs[IDEDMA_CMD]) != 0) { 265 1.2.2.2 skrll aprint_normal("%s channel %d: can't subregion DMA " 266 1.2.2.2 skrll "registers\n", 267 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 268 1.2.2.2 skrll goto next_channel; 269 1.2.2.2 skrll } 270 1.2.2.2 skrll if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 271 1.2.2.2 skrll 0x244 + (channel << 7), 4, 272 1.2.2.2 skrll &cp->dma_iohs[IDEDMA_TBL]) != 0) { 273 1.2.2.2 skrll aprint_normal("%s channel %d: can't subregion DMA " 274 1.2.2.2 skrll "registers\n", 275 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 276 1.2.2.2 skrll goto next_channel; 277 1.2.2.2 skrll } 278 1.2.2.2 skrll 279 1.2.2.2 skrll wdcattach(wdc_cp); 280 1.2.2.2 skrll bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 281 1.2.2.2 skrll (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 282 1.2.2.2 skrll 0) & ~0x00003f9f) | (channel + 1)); 283 1.2.2.2 skrll bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 284 1.2.2.2 skrll (channel + 1) << 2, 0x00000001); 285 1.2.2.2 skrll next_channel: 286 1.2.2.2 skrll continue; 287 1.2.2.2 skrll } 288 1.2.2.2 skrll return; 289 1.2.2.2 skrll } 290 1.2.2.2 skrll 291 1.2.2.2 skrll static void 292 1.2.2.2 skrll pdc203xx_setup_channel(struct ata_channel *chp) 293 1.2.2.2 skrll { 294 1.2.2.2 skrll struct ata_drive_datas *drvp; 295 1.2.2.2 skrll int drive, s; 296 1.2.2.2 skrll struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 297 1.2.2.2 skrll 298 1.2.2.2 skrll pciide_channel_dma_setup(cp); 299 1.2.2.2 skrll 300 1.2.2.2 skrll for (drive = 0; drive < 2; drive++) { 301 1.2.2.2 skrll drvp = &chp->ch_drive[drive]; 302 1.2.2.2 skrll if ((drvp->drive_flags & DRIVE) == 0) 303 1.2.2.2 skrll continue; 304 1.2.2.2 skrll if (drvp->drive_flags & DRIVE_UDMA) { 305 1.2.2.2 skrll s = splbio(); 306 1.2.2.2 skrll drvp->drive_flags &= ~DRIVE_DMA; 307 1.2.2.2 skrll splx(s); 308 1.2.2.2 skrll } 309 1.2.2.2 skrll } 310 1.2.2.2 skrll } 311 1.2.2.2 skrll 312 1.2.2.2 skrll static int 313 1.2.2.2 skrll pdc203xx_pci_intr(void *arg) 314 1.2.2.2 skrll { 315 1.2.2.2 skrll struct pciide_softc *sc = arg; 316 1.2.2.2 skrll struct pciide_channel *cp; 317 1.2.2.2 skrll struct ata_channel *wdc_cp; 318 1.2.2.2 skrll int i, rv, crv; 319 1.2.2.2 skrll u_int32_t scr; 320 1.2.2.2 skrll 321 1.2.2.2 skrll rv = 0; 322 1.2.2.2 skrll scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x00040); 323 1.2.2.2 skrll 324 1.2.2.2 skrll for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 325 1.2.2.2 skrll cp = &sc->pciide_channels[i]; 326 1.2.2.2 skrll wdc_cp = &cp->ata_channel; 327 1.2.2.2 skrll if (scr & (1 << (i + 1))) { 328 1.2.2.2 skrll crv = wdcintr(wdc_cp); 329 1.2.2.2 skrll if (crv == 0) { 330 1.2.2.2 skrll printf("%s:%d: bogus intr (reg 0x%x)\n", 331 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 332 1.2.2.2 skrll i, scr); 333 1.2.2.2 skrll } else 334 1.2.2.2 skrll rv = 1; 335 1.2.2.2 skrll } 336 1.2.2.2 skrll } 337 1.2.2.2 skrll return rv; 338 1.2.2.2 skrll } 339 1.2.2.2 skrll 340 1.2.2.2 skrll static void 341 1.2.2.2 skrll pdc203xx_irqack(struct ata_channel *chp) 342 1.2.2.2 skrll { 343 1.2.2.2 skrll struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 344 1.2.2.2 skrll struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 345 1.2.2.2 skrll 346 1.2.2.2 skrll bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 347 1.2.2.2 skrll (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 348 1.2.2.2 skrll 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 349 1.2.2.2 skrll bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 350 1.2.2.2 skrll (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 351 1.2.2.2 skrll } 352 1.2.2.2 skrll 353 1.2.2.2 skrll static int 354 1.2.2.2 skrll pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 355 1.2.2.2 skrll size_t datalen, int flags) 356 1.2.2.2 skrll { 357 1.2.2.2 skrll struct pciide_softc *sc = v; 358 1.2.2.2 skrll 359 1.2.2.2 skrll return pciide_dma_dmamap_setup(sc, channel, drive, 360 1.2.2.2 skrll databuf, datalen, flags); 361 1.2.2.2 skrll } 362 1.2.2.2 skrll 363 1.2.2.2 skrll static void 364 1.2.2.2 skrll pdc203xx_dma_start(void *v, int channel, int drive) 365 1.2.2.2 skrll { 366 1.2.2.2 skrll struct pciide_softc *sc = v; 367 1.2.2.2 skrll struct pciide_channel *cp = &sc->pciide_channels[channel]; 368 1.2.2.2 skrll struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 369 1.2.2.2 skrll 370 1.2.2.2 skrll /* Write table addr */ 371 1.2.2.2 skrll bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 372 1.2.2.2 skrll dma_maps->dmamap_table->dm_segs[0].ds_addr); 373 1.2.2.2 skrll /* start DMA engine */ 374 1.2.2.2 skrll bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 375 1.2.2.2 skrll (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 376 1.2.2.2 skrll 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 377 1.2.2.2 skrll } 378 1.2.2.2 skrll 379 1.2.2.2 skrll static int 380 1.2.2.2 skrll pdc203xx_dma_finish(void *v, int channel, int drive, int force) 381 1.2.2.2 skrll { 382 1.2.2.2 skrll struct pciide_softc *sc = v; 383 1.2.2.2 skrll struct pciide_channel *cp = &sc->pciide_channels[channel]; 384 1.2.2.2 skrll struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 385 1.2.2.2 skrll 386 1.2.2.2 skrll /* stop DMA channel */ 387 1.2.2.2 skrll bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 388 1.2.2.2 skrll (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 389 1.2.2.2 skrll 0) & ~0x80)); 390 1.2.2.2 skrll 391 1.2.2.2 skrll /* Unload the map of the data buffer */ 392 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 393 1.2.2.2 skrll dma_maps->dmamap_xfer->dm_mapsize, 394 1.2.2.2 skrll (dma_maps->dma_flags & WDC_DMA_READ) ? 395 1.2.2.2 skrll BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 396 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 397 1.2.2.2 skrll 398 1.2.2.2 skrll return 0; 399 1.2.2.2 skrll } 400
Indexes created Fri Oct 03 02:09:57 GMT 2025