pdcsata.c revision 1.2.2.4
1 1.2.2.4 christos /* $NetBSD: pdcsata.c,v 1.2.2.4 2005/12/11 10:28:59 christos Exp $ */ 2 1.2.2.2 skrll 3 1.2.2.2 skrll /* 4 1.2.2.2 skrll * Copyright (c) 2004, Manuel Bouyer. 5 1.2.2.2 skrll * 6 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 7 1.2.2.2 skrll * modification, are permitted provided that the following conditions 8 1.2.2.2 skrll * are met: 9 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 10 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 11 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 12 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 13 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 14 1.2.2.2 skrll * 3. All advertising materials mentioning features or use of this software 15 1.2.2.2 skrll * must display the following acknowledgement: 16 1.2.2.2 skrll * This product includes software developed by Manuel Bouyer. 17 1.2.2.2 skrll * 4. The name of the author may not be used to endorse or promote products 18 1.2.2.2 skrll * derived from this software without specific prior written permission. 19 1.2.2.2 skrll * 20 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 1.2.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 1.2.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 1.2.2.3 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 1.2.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 1.2.2.2 skrll * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 1.2.2.2 skrll * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 1.2.2.2 skrll * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 1.2.2.2 skrll * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 1.2.2.2 skrll * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 1.2.2.2 skrll */ 31 1.2.2.2 skrll 32 1.2.2.2 skrll #include <sys/types.h> 33 1.2.2.2 skrll #include <sys/malloc.h> 34 1.2.2.2 skrll #include <sys/param.h> 35 1.2.2.2 skrll #include <sys/systm.h> 36 1.2.2.2 skrll 37 1.2.2.2 skrll #include <dev/pci/pcivar.h> 38 1.2.2.2 skrll #include <dev/pci/pcidevs.h> 39 1.2.2.2 skrll #include <dev/pci/pciidereg.h> 40 1.2.2.2 skrll #include <dev/pci/pciidevar.h> 41 1.2.2.4 christos #include <dev/ata/atareg.h> 42 1.2.2.4 christos #include <dev/ata/satavar.h> 43 1.2.2.4 christos #include <dev/ata/satareg.h> 44 1.2.2.2 skrll 45 1.2.2.2 skrll #define PDC203xx_NCHANNELS 4 46 1.2.2.4 christos #define PDC40718_NCHANNELS 4 47 1.2.2.2 skrll 48 1.2.2.2 skrll #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 49 1.2.2.2 skrll 50 1.2.2.2 skrll static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 51 1.2.2.2 skrll static void pdc203xx_setup_channel(struct ata_channel *); 52 1.2.2.2 skrll static int pdc203xx_pci_intr(void *); 53 1.2.2.2 skrll static void pdc203xx_irqack(struct ata_channel *); 54 1.2.2.2 skrll static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 55 1.2.2.2 skrll static void pdc203xx_dma_start(void *,int ,int); 56 1.2.2.2 skrll static int pdc203xx_dma_finish(void *, int, int, int); 57 1.2.2.2 skrll 58 1.2.2.4 christos /* PDC205xx, PDC405xx and PDC407xx. but tested only pdc40718 */ 59 1.2.2.4 christos static int pdc205xx_pci_intr(void *); 60 1.2.2.4 christos static void pdc205xx_do_reset(struct ata_channel *, int); 61 1.2.2.4 christos static void pdc205xx_drv_probe(struct ata_channel *); 62 1.2.2.4 christos 63 1.2.2.2 skrll static int pdcsata_match(struct device *, struct cfdata *, void *); 64 1.2.2.2 skrll static void pdcsata_attach(struct device *, struct device *, void *); 65 1.2.2.2 skrll 66 1.2.2.2 skrll CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 67 1.2.2.2 skrll pdcsata_match, pdcsata_attach, NULL, NULL); 68 1.2.2.2 skrll 69 1.2.2.2 skrll static const struct pciide_product_desc pciide_pdcsata_products[] = { 70 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20318, 71 1.2.2.2 skrll 0, 72 1.2.2.2 skrll "Promise PDC20318 SATA150 controller", 73 1.2.2.2 skrll pdcsata_chip_map, 74 1.2.2.2 skrll }, 75 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20319, 76 1.2.2.2 skrll 0, 77 1.2.2.2 skrll "Promise PDC20319 SATA150 controller", 78 1.2.2.2 skrll pdcsata_chip_map, 79 1.2.2.2 skrll }, 80 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20371, 81 1.2.2.2 skrll 0, 82 1.2.2.2 skrll "Promise PDC20371 SATA150 controller", 83 1.2.2.2 skrll pdcsata_chip_map, 84 1.2.2.2 skrll }, 85 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20375, 86 1.2.2.2 skrll 0, 87 1.2.2.2 skrll "Promise PDC20375 SATA150 controller", 88 1.2.2.2 skrll pdcsata_chip_map, 89 1.2.2.2 skrll }, 90 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20376, 91 1.2.2.2 skrll 0, 92 1.2.2.2 skrll "Promise PDC20376 SATA150 controller", 93 1.2.2.2 skrll pdcsata_chip_map, 94 1.2.2.2 skrll }, 95 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20377, 96 1.2.2.2 skrll 0, 97 1.2.2.2 skrll "Promise PDC20377 SATA150 controller", 98 1.2.2.2 skrll pdcsata_chip_map, 99 1.2.2.2 skrll }, 100 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20378, 101 1.2.2.2 skrll 0, 102 1.2.2.2 skrll "Promise PDC20378 SATA150 controller", 103 1.2.2.2 skrll pdcsata_chip_map, 104 1.2.2.2 skrll }, 105 1.2.2.2 skrll { PCI_PRODUCT_PROMISE_PDC20379, 106 1.2.2.2 skrll 0, 107 1.2.2.2 skrll "Promise PDC20379 SATA150 controller", 108 1.2.2.2 skrll pdcsata_chip_map, 109 1.2.2.2 skrll }, 110 1.2.2.4 christos { PCI_PRODUCT_PROMISE_PDC40718, 111 1.2.2.4 christos 0, 112 1.2.2.4 christos "Promise PDC40718 SATA300 controller", 113 1.2.2.4 christos pdcsata_chip_map, 114 1.2.2.4 christos }, 115 1.2.2.4 christos { PCI_PRODUCT_PROMISE_PDC40719, 116 1.2.2.4 christos 0, 117 1.2.2.4 christos "Promise PDC40719 SATA300 controller", 118 1.2.2.4 christos pdcsata_chip_map, 119 1.2.2.4 christos }, 120 1.2.2.2 skrll { 0, 121 1.2.2.2 skrll 0, 122 1.2.2.2 skrll NULL, 123 1.2.2.2 skrll NULL 124 1.2.2.2 skrll } 125 1.2.2.2 skrll }; 126 1.2.2.2 skrll 127 1.2.2.2 skrll static int 128 1.2.2.2 skrll pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 129 1.2.2.2 skrll { 130 1.2.2.2 skrll struct pci_attach_args *pa = aux; 131 1.2.2.2 skrll 132 1.2.2.2 skrll if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 133 1.2.2.2 skrll if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 134 1.2.2.2 skrll return (2); 135 1.2.2.2 skrll } 136 1.2.2.2 skrll return (0); 137 1.2.2.2 skrll } 138 1.2.2.2 skrll 139 1.2.2.2 skrll static void 140 1.2.2.2 skrll pdcsata_attach(struct device *parent, struct device *self, void *aux) 141 1.2.2.2 skrll { 142 1.2.2.2 skrll struct pci_attach_args *pa = aux; 143 1.2.2.2 skrll struct pciide_softc *sc = (struct pciide_softc *)self; 144 1.2.2.2 skrll 145 1.2.2.2 skrll pciide_common_attach(sc, pa, 146 1.2.2.2 skrll pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 147 1.2.2.2 skrll } 148 1.2.2.2 skrll 149 1.2.2.2 skrll static void 150 1.2.2.2 skrll pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 151 1.2.2.2 skrll { 152 1.2.2.2 skrll struct pciide_channel *cp; 153 1.2.2.2 skrll struct ata_channel *wdc_cp; 154 1.2.2.2 skrll struct wdc_regs *wdr; 155 1.2.2.2 skrll int channel, i; 156 1.2.2.2 skrll bus_size_t dmasize; 157 1.2.2.2 skrll pci_intr_handle_t intrhandle; 158 1.2.2.2 skrll const char *intrstr; 159 1.2.2.2 skrll 160 1.2.2.2 skrll /* 161 1.2.2.2 skrll * Promise SATA controllers have 3 or 4 channels, 162 1.2.2.2 skrll * the usual IDE registers are mapped in I/O space, with offsets. 163 1.2.2.2 skrll */ 164 1.2.2.2 skrll if (pci_intr_map(pa, &intrhandle) != 0) { 165 1.2.2.2 skrll aprint_error("%s: couldn't map interrupt\n", 166 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 167 1.2.2.2 skrll return; 168 1.2.2.2 skrll } 169 1.2.2.2 skrll intrstr = pci_intr_string(pa->pa_pc, intrhandle); 170 1.2.2.4 christos 171 1.2.2.4 christos switch (sc->sc_pp->ide_product) { 172 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20318: 173 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20319: 174 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20371: 175 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20375: 176 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20376: 177 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20377: 178 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20378: 179 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20379: 180 1.2.2.4 christos default: 181 1.2.2.4 christos sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 182 1.2.2.4 christos intrhandle, IPL_BIO, pdc203xx_pci_intr, sc); 183 1.2.2.4 christos break; 184 1.2.2.4 christos 185 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC40718: 186 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC40719: 187 1.2.2.4 christos sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 188 1.2.2.4 christos intrhandle, IPL_BIO, pdc205xx_pci_intr, sc); 189 1.2.2.4 christos break; 190 1.2.2.4 christos } 191 1.2.2.4 christos 192 1.2.2.2 skrll if (sc->sc_pci_ih == NULL) { 193 1.2.2.2 skrll aprint_error("%s: couldn't establish native-PCI interrupt", 194 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 195 1.2.2.2 skrll if (intrstr != NULL) 196 1.2.2.2 skrll aprint_normal(" at %s", intrstr); 197 1.2.2.2 skrll aprint_normal("\n"); 198 1.2.2.2 skrll return; 199 1.2.2.2 skrll } 200 1.2.2.2 skrll aprint_normal("%s: interrupting at %s\n", 201 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 202 1.2.2.2 skrll intrstr ? intrstr : "unknown interrupt"); 203 1.2.2.3 skrll 204 1.2.2.2 skrll sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 205 1.2.2.2 skrll PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 206 1.2.2.2 skrll &sc->sc_dma_ioh, NULL, &dmasize) == 0); 207 1.2.2.2 skrll if (!sc->sc_dma_ok) { 208 1.2.2.2 skrll aprint_error("%s: couldn't map bus-master DMA registers\n", 209 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 210 1.2.2.2 skrll pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 211 1.2.2.2 skrll return; 212 1.2.2.2 skrll } 213 1.2.2.2 skrll 214 1.2.2.2 skrll sc->sc_dmat = pa->pa_dmat; 215 1.2.2.2 skrll 216 1.2.2.2 skrll if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 217 1.2.2.2 skrll PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 218 1.2.2.2 skrll &sc->sc_ba5_sh, NULL, NULL) != 0) { 219 1.2.2.2 skrll aprint_error("%s: couldn't map IDE registers\n", 220 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 221 1.2.2.2 skrll bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 222 1.2.2.2 skrll pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 223 1.2.2.2 skrll return; 224 1.2.2.2 skrll } 225 1.2.2.2 skrll 226 1.2.2.2 skrll aprint_normal("%s: bus-master DMA support present\n", 227 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 228 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 229 1.2.2.2 skrll if (sc->sc_dma_ok) { 230 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 231 1.2.2.2 skrll } 232 1.2.2.2 skrll if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 233 1.2.2.2 skrll PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 234 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 235 1.2.2.2 skrll sc->sc_wdcdev.irqack = pdc203xx_irqack; 236 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 237 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 238 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 239 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 240 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 241 1.2.2.4 christos 242 1.2.2.4 christos switch (sc->sc_pp->ide_product) { 243 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20318: 244 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20319: 245 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20371: 246 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20375: 247 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20376: 248 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20377: 249 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20378: 250 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC20379: 251 1.2.2.4 christos default: 252 1.2.2.4 christos bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 0x00ff0033); 253 1.2.2.4 christos sc->sc_wdcdev.sc_atac.atac_nchannels = 254 1.2.2.4 christos (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 255 1.2.2.4 christos PDC203xx_NCHANNELS : 3; 256 1.2.2.4 christos 257 1.2.2.4 christos break; 258 1.2.2.4 christos 259 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC40718: 260 1.2.2.4 christos case PCI_PRODUCT_PROMISE_PDC40719: 261 1.2.2.4 christos bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 262 1.2.2.4 christos sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_NCHANNELS; 263 1.2.2.4 christos 264 1.2.2.4 christos sc->sc_wdcdev.reset = pdc205xx_do_reset; 265 1.2.2.4 christos sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 266 1.2.2.4 christos 267 1.2.2.4 christos break; 268 1.2.2.4 christos } 269 1.2.2.4 christos 270 1.2.2.2 skrll wdc_allocate_regs(&sc->sc_wdcdev); 271 1.2.2.2 skrll 272 1.2.2.2 skrll sc->sc_wdcdev.dma_arg = sc; 273 1.2.2.2 skrll sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 274 1.2.2.2 skrll sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 275 1.2.2.2 skrll sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 276 1.2.2.2 skrll 277 1.2.2.2 skrll for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 278 1.2.2.2 skrll channel++) { 279 1.2.2.2 skrll cp = &sc->pciide_channels[channel]; 280 1.2.2.2 skrll sc->wdc_chanarray[channel] = &cp->ata_channel; 281 1.2.2.2 skrll 282 1.2.2.2 skrll cp->ih = sc->sc_pci_ih; 283 1.2.2.2 skrll cp->name = NULL; 284 1.2.2.2 skrll cp->ata_channel.ch_channel = channel; 285 1.2.2.2 skrll cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 286 1.2.2.2 skrll cp->ata_channel.ch_queue = 287 1.2.2.2 skrll malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 288 1.2.2.2 skrll if (cp->ata_channel.ch_queue == NULL) { 289 1.2.2.2 skrll aprint_error("%s channel %d: " 290 1.2.2.2 skrll "can't allocate memory for command queue\n", 291 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 292 1.2.2.2 skrll goto next_channel; 293 1.2.2.2 skrll } 294 1.2.2.2 skrll wdc_cp = &cp->ata_channel; 295 1.2.2.2 skrll wdr = CHAN_TO_WDC_REGS(wdc_cp); 296 1.2.2.2 skrll 297 1.2.2.2 skrll wdr->ctl_iot = sc->sc_ba5_st; 298 1.2.2.2 skrll wdr->cmd_iot = sc->sc_ba5_st; 299 1.2.2.2 skrll 300 1.2.2.2 skrll if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 301 1.2.2.2 skrll 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 302 1.2.2.2 skrll aprint_error("%s: couldn't map channel %d ctl regs\n", 303 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 304 1.2.2.2 skrll channel); 305 1.2.2.2 skrll goto next_channel; 306 1.2.2.2 skrll } 307 1.2.2.2 skrll for (i = 0; i < WDC_NREG; i++) { 308 1.2.2.2 skrll if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 309 1.2.2.2 skrll 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 310 1.2.2.2 skrll &wdr->cmd_iohs[i]) != 0) { 311 1.2.2.2 skrll aprint_error("%s: couldn't map channel %d cmd " 312 1.2.2.2 skrll "regs\n", 313 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 314 1.2.2.2 skrll channel); 315 1.2.2.2 skrll goto next_channel; 316 1.2.2.2 skrll } 317 1.2.2.2 skrll } 318 1.2.2.2 skrll wdc_init_shadow_regs(wdc_cp); 319 1.2.2.2 skrll 320 1.2.2.2 skrll /* 321 1.2.2.2 skrll * subregion de busmaster registers. They're spread all over 322 1.2.2.2 skrll * the controller's register space :(. They are also 4 bytes 323 1.2.2.2 skrll * sized, with some specific extentions in the extra bits. 324 1.2.2.2 skrll * It also seems that the IDEDMA_CTL register isn't available. 325 1.2.2.2 skrll */ 326 1.2.2.2 skrll if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 327 1.2.2.2 skrll 0x260 + (channel << 7), 1, 328 1.2.2.2 skrll &cp->dma_iohs[IDEDMA_CMD]) != 0) { 329 1.2.2.2 skrll aprint_normal("%s channel %d: can't subregion DMA " 330 1.2.2.2 skrll "registers\n", 331 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 332 1.2.2.2 skrll goto next_channel; 333 1.2.2.2 skrll } 334 1.2.2.2 skrll if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 335 1.2.2.2 skrll 0x244 + (channel << 7), 4, 336 1.2.2.2 skrll &cp->dma_iohs[IDEDMA_TBL]) != 0) { 337 1.2.2.2 skrll aprint_normal("%s channel %d: can't subregion DMA " 338 1.2.2.2 skrll "registers\n", 339 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 340 1.2.2.2 skrll goto next_channel; 341 1.2.2.2 skrll } 342 1.2.2.2 skrll 343 1.2.2.2 skrll wdcattach(wdc_cp); 344 1.2.2.2 skrll bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 345 1.2.2.2 skrll (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 346 1.2.2.2 skrll 0) & ~0x00003f9f) | (channel + 1)); 347 1.2.2.2 skrll bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 348 1.2.2.2 skrll (channel + 1) << 2, 0x00000001); 349 1.2.2.2 skrll next_channel: 350 1.2.2.2 skrll continue; 351 1.2.2.2 skrll } 352 1.2.2.2 skrll return; 353 1.2.2.2 skrll } 354 1.2.2.2 skrll 355 1.2.2.2 skrll static void 356 1.2.2.2 skrll pdc203xx_setup_channel(struct ata_channel *chp) 357 1.2.2.2 skrll { 358 1.2.2.2 skrll struct ata_drive_datas *drvp; 359 1.2.2.2 skrll int drive, s; 360 1.2.2.2 skrll struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 361 1.2.2.2 skrll 362 1.2.2.2 skrll pciide_channel_dma_setup(cp); 363 1.2.2.2 skrll 364 1.2.2.2 skrll for (drive = 0; drive < 2; drive++) { 365 1.2.2.2 skrll drvp = &chp->ch_drive[drive]; 366 1.2.2.2 skrll if ((drvp->drive_flags & DRIVE) == 0) 367 1.2.2.2 skrll continue; 368 1.2.2.2 skrll if (drvp->drive_flags & DRIVE_UDMA) { 369 1.2.2.2 skrll s = splbio(); 370 1.2.2.2 skrll drvp->drive_flags &= ~DRIVE_DMA; 371 1.2.2.2 skrll splx(s); 372 1.2.2.2 skrll } 373 1.2.2.2 skrll } 374 1.2.2.2 skrll } 375 1.2.2.2 skrll 376 1.2.2.2 skrll static int 377 1.2.2.2 skrll pdc203xx_pci_intr(void *arg) 378 1.2.2.2 skrll { 379 1.2.2.2 skrll struct pciide_softc *sc = arg; 380 1.2.2.2 skrll struct pciide_channel *cp; 381 1.2.2.2 skrll struct ata_channel *wdc_cp; 382 1.2.2.3 skrll int i, rv, crv; 383 1.2.2.2 skrll u_int32_t scr; 384 1.2.2.2 skrll 385 1.2.2.2 skrll rv = 0; 386 1.2.2.2 skrll scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x00040); 387 1.2.2.2 skrll 388 1.2.2.2 skrll for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 389 1.2.2.2 skrll cp = &sc->pciide_channels[i]; 390 1.2.2.2 skrll wdc_cp = &cp->ata_channel; 391 1.2.2.2 skrll if (scr & (1 << (i + 1))) { 392 1.2.2.2 skrll crv = wdcintr(wdc_cp); 393 1.2.2.2 skrll if (crv == 0) { 394 1.2.2.2 skrll printf("%s:%d: bogus intr (reg 0x%x)\n", 395 1.2.2.2 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 396 1.2.2.2 skrll i, scr); 397 1.2.2.2 skrll } else 398 1.2.2.2 skrll rv = 1; 399 1.2.2.2 skrll } 400 1.2.2.2 skrll } 401 1.2.2.2 skrll return rv; 402 1.2.2.2 skrll } 403 1.2.2.2 skrll 404 1.2.2.4 christos static int 405 1.2.2.4 christos pdc205xx_pci_intr(void *arg) 406 1.2.2.4 christos { 407 1.2.2.4 christos struct pciide_softc *sc = arg; 408 1.2.2.4 christos struct pciide_channel *cp; 409 1.2.2.4 christos struct ata_channel *wdc_cp; 410 1.2.2.4 christos int i, rv, crv; 411 1.2.2.4 christos u_int32_t scr, status; 412 1.2.2.4 christos 413 1.2.2.4 christos rv = 0; 414 1.2.2.4 christos scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 415 1.2.2.4 christos bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 416 1.2.2.4 christos 417 1.2.2.4 christos status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60); 418 1.2.2.4 christos bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, status & 0x000000ff); 419 1.2.2.4 christos 420 1.2.2.4 christos for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 421 1.2.2.4 christos cp = &sc->pciide_channels[i]; 422 1.2.2.4 christos wdc_cp = &cp->ata_channel; 423 1.2.2.4 christos if (scr & (1 << (i + 1))) { 424 1.2.2.4 christos crv = wdcintr(wdc_cp); 425 1.2.2.4 christos if (crv == 0) { 426 1.2.2.4 christos printf("%s:%d: bogus intr (reg 0x%x)\n", 427 1.2.2.4 christos sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 428 1.2.2.4 christos i, scr); 429 1.2.2.4 christos } else 430 1.2.2.4 christos rv = 1; 431 1.2.2.4 christos } 432 1.2.2.4 christos } 433 1.2.2.4 christos return rv; 434 1.2.2.4 christos } 435 1.2.2.4 christos 436 1.2.2.2 skrll static void 437 1.2.2.2 skrll pdc203xx_irqack(struct ata_channel *chp) 438 1.2.2.2 skrll { 439 1.2.2.2 skrll struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 440 1.2.2.2 skrll struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 441 1.2.2.2 skrll 442 1.2.2.2 skrll bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 443 1.2.2.2 skrll (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 444 1.2.2.2 skrll 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 445 1.2.2.2 skrll bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 446 1.2.2.2 skrll (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 447 1.2.2.2 skrll } 448 1.2.2.2 skrll 449 1.2.2.2 skrll static int 450 1.2.2.2 skrll pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 451 1.2.2.2 skrll size_t datalen, int flags) 452 1.2.2.2 skrll { 453 1.2.2.2 skrll struct pciide_softc *sc = v; 454 1.2.2.2 skrll 455 1.2.2.2 skrll return pciide_dma_dmamap_setup(sc, channel, drive, 456 1.2.2.2 skrll databuf, datalen, flags); 457 1.2.2.2 skrll } 458 1.2.2.2 skrll 459 1.2.2.2 skrll static void 460 1.2.2.2 skrll pdc203xx_dma_start(void *v, int channel, int drive) 461 1.2.2.2 skrll { 462 1.2.2.2 skrll struct pciide_softc *sc = v; 463 1.2.2.2 skrll struct pciide_channel *cp = &sc->pciide_channels[channel]; 464 1.2.2.2 skrll struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 465 1.2.2.2 skrll 466 1.2.2.2 skrll /* Write table addr */ 467 1.2.2.2 skrll bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 468 1.2.2.2 skrll dma_maps->dmamap_table->dm_segs[0].ds_addr); 469 1.2.2.2 skrll /* start DMA engine */ 470 1.2.2.2 skrll bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 471 1.2.2.2 skrll (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 472 1.2.2.2 skrll 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 473 1.2.2.2 skrll } 474 1.2.2.2 skrll 475 1.2.2.2 skrll static int 476 1.2.2.2 skrll pdc203xx_dma_finish(void *v, int channel, int drive, int force) 477 1.2.2.2 skrll { 478 1.2.2.2 skrll struct pciide_softc *sc = v; 479 1.2.2.2 skrll struct pciide_channel *cp = &sc->pciide_channels[channel]; 480 1.2.2.2 skrll struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 481 1.2.2.2 skrll 482 1.2.2.2 skrll /* stop DMA channel */ 483 1.2.2.2 skrll bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 484 1.2.2.2 skrll (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 485 1.2.2.2 skrll 0) & ~0x80)); 486 1.2.2.2 skrll 487 1.2.2.2 skrll /* Unload the map of the data buffer */ 488 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 489 1.2.2.2 skrll dma_maps->dmamap_xfer->dm_mapsize, 490 1.2.2.2 skrll (dma_maps->dma_flags & WDC_DMA_READ) ? 491 1.2.2.2 skrll BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 492 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 493 1.2.2.2 skrll 494 1.2.2.2 skrll return 0; 495 1.2.2.2 skrll } 496 1.2.2.4 christos 497 1.2.2.4 christos #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 498 1.2.2.4 christos #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 499 1.2.2.4 christos #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 500 1.2.2.4 christos #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 501 1.2.2.4 christos #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 502 1.2.2.4 christos 503 1.2.2.4 christos 504 1.2.2.4 christos #define SCONTROL_WRITE(sc,channel,scontrol) \ 505 1.2.2.4 christos bus_space_write_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 506 1.2.2.4 christos PDC205_SCONTROL(channel), scontrol) 507 1.2.2.4 christos 508 1.2.2.4 christos #define SSTATUS_READ(sc,channel) \ 509 1.2.2.4 christos bus_space_read_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 510 1.2.2.4 christos PDC205_SSTATUS(channel)) 511 1.2.2.4 christos 512 1.2.2.4 christos 513 1.2.2.4 christos 514 1.2.2.4 christos static void 515 1.2.2.4 christos pdc205xx_do_reset(struct ata_channel *chp, int poll) 516 1.2.2.4 christos { 517 1.2.2.4 christos struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 518 1.2.2.4 christos u_int32_t scontrol; 519 1.2.2.4 christos 520 1.2.2.4 christos wdc_do_reset(chp, poll); 521 1.2.2.4 christos 522 1.2.2.4 christos /* reset SATA */ 523 1.2.2.4 christos scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 524 1.2.2.4 christos SCONTROL_WRITE(sc, chp->ch_channel, scontrol); 525 1.2.2.4 christos delay(50*1000); 526 1.2.2.4 christos 527 1.2.2.4 christos scontrol &= ~SControl_DET_INIT; 528 1.2.2.4 christos SCONTROL_WRITE(sc, chp->ch_channel, scontrol); 529 1.2.2.4 christos delay(50*1000); 530 1.2.2.4 christos } 531 1.2.2.4 christos 532 1.2.2.4 christos 533 1.2.2.4 christos 534 1.2.2.4 christos static void 535 1.2.2.4 christos pdc205xx_drv_probe(struct ata_channel *chp) 536 1.2.2.4 christos { 537 1.2.2.4 christos struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 538 1.2.2.4 christos struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 539 1.2.2.4 christos u_int32_t scontrol, sstatus; 540 1.2.2.4 christos u_int16_t scnt, sn, cl, ch; 541 1.2.2.4 christos int i, s; 542 1.2.2.4 christos 543 1.2.2.4 christos /* XXX This should be done by other code. */ 544 1.2.2.4 christos for (i = 0; i < 2; i++) { 545 1.2.2.4 christos chp->ch_drive[i].chnl_softc = chp; 546 1.2.2.4 christos chp->ch_drive[i].drive = i; 547 1.2.2.4 christos } 548 1.2.2.4 christos 549 1.2.2.4 christos SCONTROL_WRITE(sc, chp->ch_channel, 0); 550 1.2.2.4 christos delay(50*1000); 551 1.2.2.4 christos 552 1.2.2.4 christos scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 553 1.2.2.4 christos SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 554 1.2.2.4 christos delay(50*1000); 555 1.2.2.4 christos 556 1.2.2.4 christos scontrol &= ~SControl_DET_INIT; 557 1.2.2.4 christos SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 558 1.2.2.4 christos delay(50*1000); 559 1.2.2.4 christos 560 1.2.2.4 christos sstatus = SSTATUS_READ(sc,chp->ch_channel); 561 1.2.2.4 christos 562 1.2.2.4 christos switch (sstatus & SStatus_DET_mask) { 563 1.2.2.4 christos case SStatus_DET_NODEV: 564 1.2.2.4 christos /* No Device; be silent. */ 565 1.2.2.4 christos break; 566 1.2.2.4 christos 567 1.2.2.4 christos case SStatus_DET_DEV_NE: 568 1.2.2.4 christos aprint_error("%s: port %d: device connected, but " 569 1.2.2.4 christos "communication not established\n", 570 1.2.2.4 christos sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 571 1.2.2.4 christos break; 572 1.2.2.4 christos 573 1.2.2.4 christos case SStatus_DET_OFFLINE: 574 1.2.2.4 christos aprint_error("%s: port %d: PHY offline\n", 575 1.2.2.4 christos sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 576 1.2.2.4 christos break; 577 1.2.2.4 christos 578 1.2.2.4 christos case SStatus_DET_DEV: 579 1.2.2.4 christos bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 580 1.2.2.4 christos WDSD_IBM); 581 1.2.2.4 christos delay(10); /* 400ns delay */ 582 1.2.2.4 christos scnt = bus_space_read_2(wdr->cmd_iot, 583 1.2.2.4 christos wdr->cmd_iohs[wd_seccnt], 0); 584 1.2.2.4 christos sn = bus_space_read_2(wdr->cmd_iot, 585 1.2.2.4 christos wdr->cmd_iohs[wd_sector], 0); 586 1.2.2.4 christos cl = bus_space_read_2(wdr->cmd_iot, 587 1.2.2.4 christos wdr->cmd_iohs[wd_cyl_lo], 0); 588 1.2.2.4 christos ch = bus_space_read_2(wdr->cmd_iot, 589 1.2.2.4 christos wdr->cmd_iohs[wd_cyl_hi], 0); 590 1.2.2.4 christos #if 0 591 1.2.2.4 christos printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 592 1.2.2.4 christos sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 593 1.2.2.4 christos scnt, sn, cl, ch); 594 1.2.2.4 christos #endif 595 1.2.2.4 christos /* 596 1.2.2.4 christos * scnt and sn are supposed to be 0x1 for ATAPI, but in some 597 1.2.2.4 christos * cases we get wrong values here, so ignore it. 598 1.2.2.4 christos */ 599 1.2.2.4 christos s = splbio(); 600 1.2.2.4 christos if (cl == 0x14 && ch == 0xeb) 601 1.2.2.4 christos chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 602 1.2.2.4 christos else 603 1.2.2.4 christos chp->ch_drive[0].drive_flags |= DRIVE_ATA; 604 1.2.2.4 christos splx(s); 605 1.2.2.4 christos #if 0 606 1.2.2.4 christos aprint_normal("%s: port %d: device present, speed: %s\n", 607 1.2.2.4 christos sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 608 1.2.2.4 christos sata_speed(sstatus)); 609 1.2.2.4 christos #endif 610 1.2.2.4 christos break; 611 1.2.2.4 christos 612 1.2.2.4 christos default: 613 1.2.2.4 christos aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 614 1.2.2.4 christos sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 615 1.2.2.4 christos sstatus); 616 1.2.2.4 christos } 617 1.2.2.4 christos } 618
Indexes created Fri Oct 03 02:09:57 GMT 2025