pdcsata.c revision 1.10
1 /* $NetBSD: pdcsata.c,v 1.10 2006/08/13 09:39:25 dsainty Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.10 2006/08/13 09:39:25 dsainty Exp $"); 34 35 #include <sys/types.h> 36 #include <sys/malloc.h> 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcidevs.h> 42 #include <dev/pci/pciidereg.h> 43 #include <dev/pci/pciidevar.h> 44 #include <dev/ata/atareg.h> 45 #include <dev/ata/satavar.h> 46 #include <dev/ata/satareg.h> 47 48 #define PDC203xx_NCHANNELS 4 49 #define PDC40718_NCHANNELS 4 50 #define PDC20575_NCHANNELS 3 51 52 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 53 54 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 55 #define PDC_ERRMASK 0x00780700 56 57 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 58 static void pdc203xx_setup_channel(struct ata_channel *); 59 static void pdc203xx_irqack(struct ata_channel *); 60 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 61 static void pdc203xx_dma_start(void *,int ,int); 62 static int pdc203xx_dma_finish(void *, int, int, int); 63 static int pdcsata_pci_intr(void *); 64 static void pdcsata_do_reset(struct ata_channel *, int); 65 66 /* PDC205xx, PDC405xx and PDC407xx. but tested only pdc40718 */ 67 static void pdc205xx_drv_probe(struct ata_channel *); 68 69 static int pdcsata_match(struct device *, struct cfdata *, void *); 70 static void pdcsata_attach(struct device *, struct device *, void *); 71 72 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 73 pdcsata_match, pdcsata_attach, NULL, NULL); 74 75 static const struct pciide_product_desc pciide_pdcsata_products[] = { 76 { PCI_PRODUCT_PROMISE_PDC20318, 77 0, 78 "Promise PDC20318 SATA150 controller", 79 pdcsata_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_PDC20319, 82 0, 83 "Promise PDC20319 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20371, 87 0, 88 "Promise PDC20371 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20375, 92 0, 93 "Promise PDC20375 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20376, 97 0, 98 "Promise PDC20376 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_PDC20377, 102 0, 103 "Promise PDC20377 SATA150 controller", 104 pdcsata_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_PDC20378, 107 0, 108 "Promise PDC20378 SATA150 controller", 109 pdcsata_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_PDC20379, 112 0, 113 "Promise PDC20379 SATA150 controller", 114 pdcsata_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_PDC40518, 117 0, 118 "Promise PDC40518 SATA 150 controller", 119 pdcsata_chip_map, 120 }, 121 { PCI_PRODUCT_PROMISE_PDC40718, 122 0, 123 "Promise PDC40718 SATA300 controller", 124 pdcsata_chip_map, 125 }, 126 { PCI_PRODUCT_PROMISE_PDC40719, 127 0, 128 "Promise PDC40719 SATA300 controller", 129 pdcsata_chip_map, 130 }, 131 { PCI_PRODUCT_PROMISE_PDC20571, 132 0, 133 "Promise PDC20571 SATA150 controller", 134 pdcsata_chip_map, 135 }, 136 { PCI_PRODUCT_PROMISE_PDC20575, 137 0, 138 "Promise PDC20575 SATA150 controller", 139 pdcsata_chip_map, 140 }, 141 { PCI_PRODUCT_PROMISE_PDC20579, 142 0, 143 "Promise PDC20579 SATA150 controller", 144 pdcsata_chip_map, 145 }, 146 { PCI_PRODUCT_PROMISE_PDC20771, 147 0, 148 "Promise PDC20771 SATA300 controller", 149 pdcsata_chip_map, 150 }, 151 { PCI_PRODUCT_PROMISE_PDC20775, 152 0, 153 "Promise PDC20775 SATA300 controller", 154 pdcsata_chip_map, 155 }, 156 { 0, 157 0, 158 NULL, 159 NULL 160 } 161 }; 162 163 static int 164 pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 165 { 166 struct pci_attach_args *pa = aux; 167 168 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 169 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 170 return (2); 171 } 172 return (0); 173 } 174 175 static void 176 pdcsata_attach(struct device *parent, struct device *self, void *aux) 177 { 178 struct pci_attach_args *pa = aux; 179 struct pciide_softc *sc = (struct pciide_softc *)self; 180 181 pciide_common_attach(sc, pa, 182 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 183 } 184 185 static void 186 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 187 { 188 struct pciide_channel *cp; 189 struct ata_channel *wdc_cp; 190 struct wdc_regs *wdr; 191 int channel, i; 192 bus_size_t dmasize; 193 pci_intr_handle_t intrhandle; 194 const char *intrstr; 195 196 /* 197 * Promise SATA controllers have 3 or 4 channels, 198 * the usual IDE registers are mapped in I/O space, with offsets. 199 */ 200 if (pci_intr_map(pa, &intrhandle) != 0) { 201 aprint_error("%s: couldn't map interrupt\n", 202 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 203 return; 204 } 205 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 206 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 207 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 208 209 if (sc->sc_pci_ih == NULL) { 210 aprint_error("%s: couldn't establish native-PCI interrupt", 211 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 212 if (intrstr != NULL) 213 aprint_normal(" at %s", intrstr); 214 aprint_normal("\n"); 215 return; 216 } 217 aprint_normal("%s: interrupting at %s\n", 218 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 219 intrstr ? intrstr : "unknown interrupt"); 220 221 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 222 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 223 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 224 if (!sc->sc_dma_ok) { 225 aprint_error("%s: couldn't map bus-master DMA registers\n", 226 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 227 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 228 return; 229 } 230 231 sc->sc_dmat = pa->pa_dmat; 232 233 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 234 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 235 &sc->sc_ba5_sh, NULL, NULL) != 0) { 236 aprint_error("%s: couldn't map IDE registers\n", 237 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 238 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 239 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 240 return; 241 } 242 243 aprint_normal("%s: bus-master DMA support present\n", 244 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 245 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 246 if (sc->sc_dma_ok) { 247 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 248 } 249 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 250 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 251 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 252 sc->sc_wdcdev.irqack = pdc203xx_irqack; 253 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 254 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 255 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 256 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 257 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 258 259 sc->sc_wdcdev.reset = pdcsata_do_reset; 260 261 switch (sc->sc_pp->ide_product) { 262 case PCI_PRODUCT_PROMISE_PDC20318: 263 case PCI_PRODUCT_PROMISE_PDC20319: 264 case PCI_PRODUCT_PROMISE_PDC20371: 265 case PCI_PRODUCT_PROMISE_PDC20375: 266 case PCI_PRODUCT_PROMISE_PDC20376: 267 case PCI_PRODUCT_PROMISE_PDC20377: 268 case PCI_PRODUCT_PROMISE_PDC20378: 269 case PCI_PRODUCT_PROMISE_PDC20379: 270 default: 271 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 0x00ff0033); 272 sc->sc_wdcdev.sc_atac.atac_nchannels = 273 (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 274 PDC203xx_NCHANNELS : 3; 275 276 break; 277 278 case PCI_PRODUCT_PROMISE_PDC40518: 279 case PCI_PRODUCT_PROMISE_PDC40718: 280 case PCI_PRODUCT_PROMISE_PDC40719: 281 case PCI_PRODUCT_PROMISE_PDC20571: 282 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 283 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_NCHANNELS; 284 285 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 286 287 break; 288 case PCI_PRODUCT_PROMISE_PDC20575: 289 case PCI_PRODUCT_PROMISE_PDC20579: 290 case PCI_PRODUCT_PROMISE_PDC20771: 291 case PCI_PRODUCT_PROMISE_PDC20775: 292 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 293 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_NCHANNELS; 294 295 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 296 297 break; 298 } 299 300 wdc_allocate_regs(&sc->sc_wdcdev); 301 302 sc->sc_wdcdev.dma_arg = sc; 303 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 304 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 305 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 306 307 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 308 channel++) { 309 cp = &sc->pciide_channels[channel]; 310 sc->wdc_chanarray[channel] = &cp->ata_channel; 311 312 cp->ih = sc->sc_pci_ih; 313 cp->name = NULL; 314 cp->ata_channel.ch_channel = channel; 315 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 316 cp->ata_channel.ch_queue = 317 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 318 cp->ata_channel.ch_ndrive = 2; 319 if (cp->ata_channel.ch_queue == NULL) { 320 aprint_error("%s channel %d: " 321 "can't allocate memory for command queue\n", 322 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 323 goto next_channel; 324 } 325 wdc_cp = &cp->ata_channel; 326 wdr = CHAN_TO_WDC_REGS(wdc_cp); 327 328 wdr->ctl_iot = sc->sc_ba5_st; 329 wdr->cmd_iot = sc->sc_ba5_st; 330 331 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 332 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 333 aprint_error("%s: couldn't map channel %d ctl regs\n", 334 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 335 channel); 336 goto next_channel; 337 } 338 for (i = 0; i < WDC_NREG; i++) { 339 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 340 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 341 &wdr->cmd_iohs[i]) != 0) { 342 aprint_error("%s: couldn't map channel %d cmd " 343 "regs\n", 344 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 345 channel); 346 goto next_channel; 347 } 348 } 349 wdc_init_shadow_regs(wdc_cp); 350 351 /* 352 * subregion de busmaster registers. They're spread all over 353 * the controller's register space :(. They are also 4 bytes 354 * sized, with some specific extentions in the extra bits. 355 * It also seems that the IDEDMA_CTL register isn't available. 356 */ 357 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 358 0x260 + (channel << 7), 1, 359 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 360 aprint_normal("%s channel %d: can't subregion DMA " 361 "registers\n", 362 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 363 goto next_channel; 364 } 365 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 366 0x244 + (channel << 7), 4, 367 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 368 aprint_normal("%s channel %d: can't subregion DMA " 369 "registers\n", 370 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 371 goto next_channel; 372 } 373 374 wdcattach(wdc_cp); 375 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 376 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 377 0) & ~0x00003f9f) | (channel + 1)); 378 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 379 (channel + 1) << 2, 0x00000001); 380 next_channel: 381 continue; 382 } 383 return; 384 } 385 386 static void 387 pdc203xx_setup_channel(struct ata_channel *chp) 388 { 389 struct ata_drive_datas *drvp; 390 int drive, s; 391 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 392 393 pciide_channel_dma_setup(cp); 394 395 for (drive = 0; drive < 2; drive++) { 396 drvp = &chp->ch_drive[drive]; 397 if ((drvp->drive_flags & DRIVE) == 0) 398 continue; 399 if (drvp->drive_flags & DRIVE_UDMA) { 400 s = splbio(); 401 drvp->drive_flags &= ~DRIVE_DMA; 402 splx(s); 403 } 404 } 405 } 406 407 static int 408 pdcsata_pci_intr(void *arg) 409 { 410 struct pciide_softc *sc = arg; 411 struct pciide_channel *cp; 412 struct ata_channel *wdc_cp; 413 int i, rv, crv; 414 u_int32_t scr, status, chanbase; 415 416 rv = 0; 417 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 418 if (scr == 0xffffffff) return(rv); 419 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 420 scr = scr & 0x0000ffff; 421 if (!scr) return(rv); 422 423 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 424 cp = &sc->pciide_channels[i]; 425 wdc_cp = &cp->ata_channel; 426 if (scr & (1 << (i + 1))) { 427 chanbase = PDC_CHANNELBASE(i) + 0x48; 428 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 429 if (status & PDC_ERRMASK) { 430 chanbase = PDC_CHANNELBASE(i) + 0x60; 431 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 432 status |= 0x800; 433 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 434 status &= ~0x800; 435 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 436 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 437 continue; 438 } 439 crv = wdcintr(wdc_cp); 440 if (crv == 0) { 441 printf("%s:%d: bogus intr (reg 0x%x)\n", 442 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 443 i, scr); 444 } else 445 rv = 1; 446 } 447 } 448 return rv; 449 } 450 451 static void 452 pdc203xx_irqack(struct ata_channel *chp) 453 { 454 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 455 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 456 457 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 458 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 459 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 460 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 461 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 462 } 463 464 static int 465 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 466 size_t datalen, int flags) 467 { 468 struct pciide_softc *sc = v; 469 470 return pciide_dma_dmamap_setup(sc, channel, drive, 471 databuf, datalen, flags); 472 } 473 474 static void 475 pdc203xx_dma_start(void *v, int channel, int drive) 476 { 477 struct pciide_softc *sc = v; 478 struct pciide_channel *cp = &sc->pciide_channels[channel]; 479 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 480 481 /* Write table addr */ 482 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 483 dma_maps->dmamap_table->dm_segs[0].ds_addr); 484 /* start DMA engine */ 485 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 486 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 487 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 488 } 489 490 static int 491 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 492 { 493 struct pciide_softc *sc = v; 494 struct pciide_channel *cp = &sc->pciide_channels[channel]; 495 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 496 497 /* stop DMA channel */ 498 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 499 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 500 0) & ~0x80)); 501 502 /* Unload the map of the data buffer */ 503 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 504 dma_maps->dmamap_xfer->dm_mapsize, 505 (dma_maps->dma_flags & WDC_DMA_READ) ? 506 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 507 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 508 509 return 0; 510 } 511 512 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 513 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 514 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 515 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 516 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 517 518 519 #define SCONTROL_WRITE(sc,channel,scontrol) \ 520 bus_space_write_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 521 PDC205_SCONTROL(channel), scontrol) 522 523 #define SSTATUS_READ(sc,channel) \ 524 bus_space_read_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 525 PDC205_SSTATUS(channel)) 526 527 528 529 static void 530 pdcsata_do_reset(struct ata_channel *chp, int poll) 531 { 532 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 533 int reset, status, i, chanbase; 534 535 /* reset SATA */ 536 reset = (1 << 11); 537 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 538 for (i = 0; i < 11;i ++) { 539 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 540 if (status & reset) break; 541 delay(100); 542 status |= reset; 543 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 544 } 545 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 546 status &= ~reset; 547 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 548 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 549 550 wdc_do_reset(chp, poll); 551 552 } 553 554 static void 555 pdc205xx_drv_probe(struct ata_channel *chp) 556 { 557 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 558 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 559 u_int32_t scontrol, sstatus; 560 u_int16_t scnt, sn, cl, ch; 561 int i, s; 562 563 /* XXX This should be done by other code. */ 564 for (i = 0; i < 2; i++) { 565 chp->ch_drive[i].chnl_softc = chp; 566 chp->ch_drive[i].drive = i; 567 } 568 569 SCONTROL_WRITE(sc, chp->ch_channel, 0); 570 delay(50*1000); 571 572 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 573 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 574 delay(50*1000); 575 576 scontrol &= ~SControl_DET_INIT; 577 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 578 delay(50*1000); 579 580 sstatus = SSTATUS_READ(sc,chp->ch_channel); 581 582 switch (sstatus & SStatus_DET_mask) { 583 case SStatus_DET_NODEV: 584 /* No Device; be silent. */ 585 break; 586 587 case SStatus_DET_DEV_NE: 588 aprint_error("%s: port %d: device connected, but " 589 "communication not established\n", 590 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 591 break; 592 593 case SStatus_DET_OFFLINE: 594 aprint_error("%s: port %d: PHY offline\n", 595 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 596 break; 597 598 case SStatus_DET_DEV: 599 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 600 WDSD_IBM); 601 delay(10); /* 400ns delay */ 602 scnt = bus_space_read_2(wdr->cmd_iot, 603 wdr->cmd_iohs[wd_seccnt], 0); 604 sn = bus_space_read_2(wdr->cmd_iot, 605 wdr->cmd_iohs[wd_sector], 0); 606 cl = bus_space_read_2(wdr->cmd_iot, 607 wdr->cmd_iohs[wd_cyl_lo], 0); 608 ch = bus_space_read_2(wdr->cmd_iot, 609 wdr->cmd_iohs[wd_cyl_hi], 0); 610 #if 0 611 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 612 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 613 scnt, sn, cl, ch); 614 #endif 615 /* 616 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 617 * cases we get wrong values here, so ignore it. 618 */ 619 s = splbio(); 620 if (cl == 0x14 && ch == 0xeb) 621 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 622 else 623 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 624 splx(s); 625 #if 0 626 aprint_normal("%s: port %d: device present, speed: %s\n", 627 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 628 sata_speed(sstatus)); 629 #endif 630 break; 631 632 default: 633 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 634 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 635 sstatus); 636 } 637 } 638
Indexes created Tue Sep 30 07:10:03 GMT 2025