pdcsata.c revision 1.11
1 /* $NetBSD: pdcsata.c,v 1.11 2006/09/03 12:18:03 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.11 2006/09/03 12:18:03 xtraeme Exp $"); 34 35 #include <sys/types.h> 36 #include <sys/malloc.h> 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcidevs.h> 42 #include <dev/pci/pciidereg.h> 43 #include <dev/pci/pciidevar.h> 44 #include <dev/ata/atareg.h> 45 #include <dev/ata/satavar.h> 46 #include <dev/ata/satareg.h> 47 48 #define PDC203xx_NCHANNELS 4 49 #define PDC40718_NCHANNELS 4 50 #define PDC20575_NCHANNELS 3 51 52 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 53 54 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 55 #define PDC_ERRMASK 0x00780700 56 57 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 58 static void pdc203xx_setup_channel(struct ata_channel *); 59 static void pdc203xx_irqack(struct ata_channel *); 60 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 61 static void pdc203xx_dma_start(void *,int ,int); 62 static int pdc203xx_dma_finish(void *, int, int, int); 63 static int pdcsata_pci_intr(void *); 64 static void pdcsata_do_reset(struct ata_channel *, int); 65 66 /* PDC205xx, PDC405xx and PDC407xx. but tested only pdc40718 */ 67 static void pdc205xx_drv_probe(struct ata_channel *); 68 69 static int pdcsata_match(struct device *, struct cfdata *, void *); 70 static void pdcsata_attach(struct device *, struct device *, void *); 71 72 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 73 pdcsata_match, pdcsata_attach, NULL, NULL); 74 75 static const struct pciide_product_desc pciide_pdcsata_products[] = { 76 { PCI_PRODUCT_PROMISE_PDC20318, 77 0, 78 "Promise PDC20318 SATA150 controller", 79 pdcsata_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_PDC20319, 82 0, 83 "Promise PDC20319 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20371, 87 0, 88 "Promise PDC20371 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20375, 92 0, 93 "Promise PDC20375 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20376, 97 0, 98 "Promise PDC20376 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_PDC20377, 102 0, 103 "Promise PDC20377 SATA150 controller", 104 pdcsata_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_PDC20378, 107 0, 108 "Promise PDC20378 SATA150 controller", 109 pdcsata_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_PDC20379, 112 0, 113 "Promise PDC20379 SATA150 controller", 114 pdcsata_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_PDC40518, 117 0, 118 "Promise PDC40518 SATA150 controller", 119 pdcsata_chip_map, 120 }, 121 { PCI_PRODUCT_PROMISE_PDC40519, 122 0, 123 "Promise PDC40519 SATA 150 controller", 124 pdcsata_chip_map, 125 }, 126 { PCI_PRODUCT_PROMISE_PDC40718, 127 0, 128 "Promise PDC40718 SATA300 controller", 129 pdcsata_chip_map, 130 }, 131 { PCI_PRODUCT_PROMISE_PDC40719, 132 0, 133 "Promise PDC40719 SATA300 controller", 134 pdcsata_chip_map, 135 }, 136 { PCI_PRODUCT_PROMISE_PDC40779, 137 0, 138 "Promise PDC40779 SATA300 controller", 139 pdcsata_chip_map, 140 }, 141 { PCI_PRODUCT_PROMISE_PDC20571, 142 0, 143 "Promise PDC20571 SATA150 controller", 144 pdcsata_chip_map, 145 }, 146 { PCI_PRODUCT_PROMISE_PDC20575, 147 0, 148 "Promise PDC20575 SATA150 controller", 149 pdcsata_chip_map, 150 }, 151 { PCI_PRODUCT_PROMISE_PDC20579, 152 0, 153 "Promise PDC20579 SATA150 controller", 154 pdcsata_chip_map, 155 }, 156 { PCI_PRODUCT_PROMISE_PDC20771, 157 0, 158 "Promise PDC20771 SATA300 controller", 159 pdcsata_chip_map, 160 }, 161 { PCI_PRODUCT_PROMISE_PDC20775, 162 0, 163 "Promise PDC20775 SATA300 controller", 164 pdcsata_chip_map, 165 }, 166 { 0, 167 0, 168 NULL, 169 NULL 170 } 171 }; 172 173 static int 174 pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 175 { 176 struct pci_attach_args *pa = aux; 177 178 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 179 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 180 return (2); 181 } 182 return (0); 183 } 184 185 static void 186 pdcsata_attach(struct device *parent, struct device *self, void *aux) 187 { 188 struct pci_attach_args *pa = aux; 189 struct pciide_softc *sc = (struct pciide_softc *)self; 190 191 pciide_common_attach(sc, pa, 192 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 193 } 194 195 static void 196 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 197 { 198 struct pciide_channel *cp; 199 struct ata_channel *wdc_cp; 200 struct wdc_regs *wdr; 201 int channel, i; 202 bus_size_t dmasize; 203 pci_intr_handle_t intrhandle; 204 const char *intrstr; 205 206 /* 207 * Promise SATA controllers have 3 or 4 channels, 208 * the usual IDE registers are mapped in I/O space, with offsets. 209 */ 210 if (pci_intr_map(pa, &intrhandle) != 0) { 211 aprint_error("%s: couldn't map interrupt\n", 212 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 213 return; 214 } 215 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 216 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 217 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 218 219 if (sc->sc_pci_ih == NULL) { 220 aprint_error("%s: couldn't establish native-PCI interrupt", 221 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 222 if (intrstr != NULL) 223 aprint_normal(" at %s", intrstr); 224 aprint_normal("\n"); 225 return; 226 } 227 aprint_normal("%s: interrupting at %s\n", 228 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 229 intrstr ? intrstr : "unknown interrupt"); 230 231 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 232 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 233 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 234 if (!sc->sc_dma_ok) { 235 aprint_error("%s: couldn't map bus-master DMA registers\n", 236 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 237 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 238 return; 239 } 240 241 sc->sc_dmat = pa->pa_dmat; 242 243 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 244 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 245 &sc->sc_ba5_sh, NULL, NULL) != 0) { 246 aprint_error("%s: couldn't map IDE registers\n", 247 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 248 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 249 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 250 return; 251 } 252 253 aprint_normal("%s: bus-master DMA support present\n", 254 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 255 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 256 if (sc->sc_dma_ok) { 257 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 258 } 259 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 260 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 261 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 262 sc->sc_wdcdev.irqack = pdc203xx_irqack; 263 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 264 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 265 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 266 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 267 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 268 269 sc->sc_wdcdev.reset = pdcsata_do_reset; 270 271 switch (sc->sc_pp->ide_product) { 272 case PCI_PRODUCT_PROMISE_PDC20318: 273 case PCI_PRODUCT_PROMISE_PDC20319: 274 case PCI_PRODUCT_PROMISE_PDC20371: 275 case PCI_PRODUCT_PROMISE_PDC20375: 276 case PCI_PRODUCT_PROMISE_PDC20376: 277 case PCI_PRODUCT_PROMISE_PDC20377: 278 case PCI_PRODUCT_PROMISE_PDC20378: 279 case PCI_PRODUCT_PROMISE_PDC20379: 280 default: 281 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 0x00ff0033); 282 sc->sc_wdcdev.sc_atac.atac_nchannels = 283 (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 284 PDC203xx_NCHANNELS : 3; 285 286 break; 287 288 case PCI_PRODUCT_PROMISE_PDC40518: 289 case PCI_PRODUCT_PROMISE_PDC40519: 290 case PCI_PRODUCT_PROMISE_PDC40718: 291 case PCI_PRODUCT_PROMISE_PDC40719: 292 case PCI_PRODUCT_PROMISE_PDC40779: 293 case PCI_PRODUCT_PROMISE_PDC20571: 294 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 295 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_NCHANNELS; 296 297 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 298 299 break; 300 case PCI_PRODUCT_PROMISE_PDC20575: 301 case PCI_PRODUCT_PROMISE_PDC20579: 302 case PCI_PRODUCT_PROMISE_PDC20771: 303 case PCI_PRODUCT_PROMISE_PDC20775: 304 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 305 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_NCHANNELS; 306 307 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 308 309 break; 310 } 311 312 wdc_allocate_regs(&sc->sc_wdcdev); 313 314 sc->sc_wdcdev.dma_arg = sc; 315 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 316 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 317 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 318 319 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 320 channel++) { 321 cp = &sc->pciide_channels[channel]; 322 sc->wdc_chanarray[channel] = &cp->ata_channel; 323 324 cp->ih = sc->sc_pci_ih; 325 cp->name = NULL; 326 cp->ata_channel.ch_channel = channel; 327 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 328 cp->ata_channel.ch_queue = 329 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 330 cp->ata_channel.ch_ndrive = 2; 331 if (cp->ata_channel.ch_queue == NULL) { 332 aprint_error("%s channel %d: " 333 "can't allocate memory for command queue\n", 334 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 335 goto next_channel; 336 } 337 wdc_cp = &cp->ata_channel; 338 wdr = CHAN_TO_WDC_REGS(wdc_cp); 339 340 wdr->ctl_iot = sc->sc_ba5_st; 341 wdr->cmd_iot = sc->sc_ba5_st; 342 343 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 344 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 345 aprint_error("%s: couldn't map channel %d ctl regs\n", 346 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 347 channel); 348 goto next_channel; 349 } 350 for (i = 0; i < WDC_NREG; i++) { 351 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 352 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 353 &wdr->cmd_iohs[i]) != 0) { 354 aprint_error("%s: couldn't map channel %d cmd " 355 "regs\n", 356 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 357 channel); 358 goto next_channel; 359 } 360 } 361 wdc_init_shadow_regs(wdc_cp); 362 363 /* 364 * subregion de busmaster registers. They're spread all over 365 * the controller's register space :(. They are also 4 bytes 366 * sized, with some specific extentions in the extra bits. 367 * It also seems that the IDEDMA_CTL register isn't available. 368 */ 369 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 370 0x260 + (channel << 7), 1, 371 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 372 aprint_normal("%s channel %d: can't subregion DMA " 373 "registers\n", 374 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 375 goto next_channel; 376 } 377 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 378 0x244 + (channel << 7), 4, 379 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 380 aprint_normal("%s channel %d: can't subregion DMA " 381 "registers\n", 382 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 383 goto next_channel; 384 } 385 386 wdcattach(wdc_cp); 387 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 388 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 389 0) & ~0x00003f9f) | (channel + 1)); 390 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 391 (channel + 1) << 2, 0x00000001); 392 next_channel: 393 continue; 394 } 395 return; 396 } 397 398 static void 399 pdc203xx_setup_channel(struct ata_channel *chp) 400 { 401 struct ata_drive_datas *drvp; 402 int drive, s; 403 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 404 405 pciide_channel_dma_setup(cp); 406 407 for (drive = 0; drive < 2; drive++) { 408 drvp = &chp->ch_drive[drive]; 409 if ((drvp->drive_flags & DRIVE) == 0) 410 continue; 411 if (drvp->drive_flags & DRIVE_UDMA) { 412 s = splbio(); 413 drvp->drive_flags &= ~DRIVE_DMA; 414 splx(s); 415 } 416 } 417 } 418 419 static int 420 pdcsata_pci_intr(void *arg) 421 { 422 struct pciide_softc *sc = arg; 423 struct pciide_channel *cp; 424 struct ata_channel *wdc_cp; 425 int i, rv, crv; 426 u_int32_t scr, status, chanbase; 427 428 rv = 0; 429 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 430 if (scr == 0xffffffff) return(rv); 431 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 432 scr = scr & 0x0000ffff; 433 if (!scr) return(rv); 434 435 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 436 cp = &sc->pciide_channels[i]; 437 wdc_cp = &cp->ata_channel; 438 if (scr & (1 << (i + 1))) { 439 chanbase = PDC_CHANNELBASE(i) + 0x48; 440 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 441 if (status & PDC_ERRMASK) { 442 chanbase = PDC_CHANNELBASE(i) + 0x60; 443 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 444 status |= 0x800; 445 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 446 status &= ~0x800; 447 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 448 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 449 continue; 450 } 451 crv = wdcintr(wdc_cp); 452 if (crv == 0) { 453 printf("%s:%d: bogus intr (reg 0x%x)\n", 454 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 455 i, scr); 456 } else 457 rv = 1; 458 } 459 } 460 return rv; 461 } 462 463 static void 464 pdc203xx_irqack(struct ata_channel *chp) 465 { 466 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 467 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 468 469 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 470 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 471 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 472 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 473 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 474 } 475 476 static int 477 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 478 size_t datalen, int flags) 479 { 480 struct pciide_softc *sc = v; 481 482 return pciide_dma_dmamap_setup(sc, channel, drive, 483 databuf, datalen, flags); 484 } 485 486 static void 487 pdc203xx_dma_start(void *v, int channel, int drive) 488 { 489 struct pciide_softc *sc = v; 490 struct pciide_channel *cp = &sc->pciide_channels[channel]; 491 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 492 493 /* Write table addr */ 494 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 495 dma_maps->dmamap_table->dm_segs[0].ds_addr); 496 /* start DMA engine */ 497 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 498 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 499 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 500 } 501 502 static int 503 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 504 { 505 struct pciide_softc *sc = v; 506 struct pciide_channel *cp = &sc->pciide_channels[channel]; 507 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 508 509 /* stop DMA channel */ 510 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 511 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 512 0) & ~0x80)); 513 514 /* Unload the map of the data buffer */ 515 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 516 dma_maps->dmamap_xfer->dm_mapsize, 517 (dma_maps->dma_flags & WDC_DMA_READ) ? 518 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 519 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 520 521 return 0; 522 } 523 524 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 525 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 526 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 527 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 528 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 529 530 531 #define SCONTROL_WRITE(sc,channel,scontrol) \ 532 bus_space_write_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 533 PDC205_SCONTROL(channel), scontrol) 534 535 #define SSTATUS_READ(sc,channel) \ 536 bus_space_read_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 537 PDC205_SSTATUS(channel)) 538 539 540 541 static void 542 pdcsata_do_reset(struct ata_channel *chp, int poll) 543 { 544 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 545 int reset, status, i, chanbase; 546 547 /* reset SATA */ 548 reset = (1 << 11); 549 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 550 for (i = 0; i < 11;i ++) { 551 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 552 if (status & reset) break; 553 delay(100); 554 status |= reset; 555 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 556 } 557 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 558 status &= ~reset; 559 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 560 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 561 562 wdc_do_reset(chp, poll); 563 564 } 565 566 static void 567 pdc205xx_drv_probe(struct ata_channel *chp) 568 { 569 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 570 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 571 u_int32_t scontrol, sstatus; 572 u_int16_t scnt, sn, cl, ch; 573 int i, s; 574 575 /* XXX This should be done by other code. */ 576 for (i = 0; i < 2; i++) { 577 chp->ch_drive[i].chnl_softc = chp; 578 chp->ch_drive[i].drive = i; 579 } 580 581 SCONTROL_WRITE(sc, chp->ch_channel, 0); 582 delay(50*1000); 583 584 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 585 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 586 delay(50*1000); 587 588 scontrol &= ~SControl_DET_INIT; 589 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 590 delay(50*1000); 591 592 sstatus = SSTATUS_READ(sc,chp->ch_channel); 593 594 switch (sstatus & SStatus_DET_mask) { 595 case SStatus_DET_NODEV: 596 /* No Device; be silent. */ 597 break; 598 599 case SStatus_DET_DEV_NE: 600 aprint_error("%s: port %d: device connected, but " 601 "communication not established\n", 602 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 603 break; 604 605 case SStatus_DET_OFFLINE: 606 aprint_error("%s: port %d: PHY offline\n", 607 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 608 break; 609 610 case SStatus_DET_DEV: 611 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 612 WDSD_IBM); 613 delay(10); /* 400ns delay */ 614 scnt = bus_space_read_2(wdr->cmd_iot, 615 wdr->cmd_iohs[wd_seccnt], 0); 616 sn = bus_space_read_2(wdr->cmd_iot, 617 wdr->cmd_iohs[wd_sector], 0); 618 cl = bus_space_read_2(wdr->cmd_iot, 619 wdr->cmd_iohs[wd_cyl_lo], 0); 620 ch = bus_space_read_2(wdr->cmd_iot, 621 wdr->cmd_iohs[wd_cyl_hi], 0); 622 #if 0 623 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 624 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 625 scnt, sn, cl, ch); 626 #endif 627 /* 628 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 629 * cases we get wrong values here, so ignore it. 630 */ 631 s = splbio(); 632 if (cl == 0x14 && ch == 0xeb) 633 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 634 else 635 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 636 splx(s); 637 #if 0 638 aprint_normal("%s: port %d: device present, speed: %s\n", 639 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 640 sata_speed(sstatus)); 641 #endif 642 break; 643 644 default: 645 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 646 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 647 sstatus); 648 } 649 } 650
Indexes created Tue Sep 30 07:10:03 GMT 2025