pdcsata.c revision 1.12
1 /* $NetBSD: pdcsata.c,v 1.12 2006/10/12 01:31:33 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.12 2006/10/12 01:31:33 christos Exp $"); 34 35 #include <sys/types.h> 36 #include <sys/malloc.h> 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcidevs.h> 42 #include <dev/pci/pciidereg.h> 43 #include <dev/pci/pciidevar.h> 44 #include <dev/ata/atareg.h> 45 #include <dev/ata/satavar.h> 46 #include <dev/ata/satareg.h> 47 48 #define PDC203xx_NCHANNELS 4 49 #define PDC40718_NCHANNELS 4 50 #define PDC20575_NCHANNELS 3 51 52 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 53 54 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 55 #define PDC_ERRMASK 0x00780700 56 57 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 58 static void pdc203xx_setup_channel(struct ata_channel *); 59 static void pdc203xx_irqack(struct ata_channel *); 60 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 61 static void pdc203xx_dma_start(void *,int ,int); 62 static int pdc203xx_dma_finish(void *, int, int, int); 63 static int pdcsata_pci_intr(void *); 64 static void pdcsata_do_reset(struct ata_channel *, int); 65 66 /* PDC205xx, PDC405xx and PDC407xx. but tested only pdc40718 */ 67 static void pdc205xx_drv_probe(struct ata_channel *); 68 69 static int pdcsata_match(struct device *, struct cfdata *, void *); 70 static void pdcsata_attach(struct device *, struct device *, void *); 71 72 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 73 pdcsata_match, pdcsata_attach, NULL, NULL); 74 75 static const struct pciide_product_desc pciide_pdcsata_products[] = { 76 { PCI_PRODUCT_PROMISE_PDC20318, 77 0, 78 "Promise PDC20318 SATA150 controller", 79 pdcsata_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_PDC20319, 82 0, 83 "Promise PDC20319 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20371, 87 0, 88 "Promise PDC20371 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20375, 92 0, 93 "Promise PDC20375 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20376, 97 0, 98 "Promise PDC20376 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_PDC20377, 102 0, 103 "Promise PDC20377 SATA150 controller", 104 pdcsata_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_PDC20378, 107 0, 108 "Promise PDC20378 SATA150 controller", 109 pdcsata_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_PDC20379, 112 0, 113 "Promise PDC20379 SATA150 controller", 114 pdcsata_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_PDC40518, 117 0, 118 "Promise PDC40518 SATA150 controller", 119 pdcsata_chip_map, 120 }, 121 { PCI_PRODUCT_PROMISE_PDC40519, 122 0, 123 "Promise PDC40519 SATA 150 controller", 124 pdcsata_chip_map, 125 }, 126 { PCI_PRODUCT_PROMISE_PDC40718, 127 0, 128 "Promise PDC40718 SATA300 controller", 129 pdcsata_chip_map, 130 }, 131 { PCI_PRODUCT_PROMISE_PDC40719, 132 0, 133 "Promise PDC40719 SATA300 controller", 134 pdcsata_chip_map, 135 }, 136 { PCI_PRODUCT_PROMISE_PDC40779, 137 0, 138 "Promise PDC40779 SATA300 controller", 139 pdcsata_chip_map, 140 }, 141 { PCI_PRODUCT_PROMISE_PDC20571, 142 0, 143 "Promise PDC20571 SATA150 controller", 144 pdcsata_chip_map, 145 }, 146 { PCI_PRODUCT_PROMISE_PDC20575, 147 0, 148 "Promise PDC20575 SATA150 controller", 149 pdcsata_chip_map, 150 }, 151 { PCI_PRODUCT_PROMISE_PDC20579, 152 0, 153 "Promise PDC20579 SATA150 controller", 154 pdcsata_chip_map, 155 }, 156 { PCI_PRODUCT_PROMISE_PDC20771, 157 0, 158 "Promise PDC20771 SATA300 controller", 159 pdcsata_chip_map, 160 }, 161 { PCI_PRODUCT_PROMISE_PDC20775, 162 0, 163 "Promise PDC20775 SATA300 controller", 164 pdcsata_chip_map, 165 }, 166 { 0, 167 0, 168 NULL, 169 NULL 170 } 171 }; 172 173 static int 174 pdcsata_match(struct device *parent __unused, struct cfdata *match __unused, 175 void *aux) 176 { 177 struct pci_attach_args *pa = aux; 178 179 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 180 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 181 return (2); 182 } 183 return (0); 184 } 185 186 static void 187 pdcsata_attach(struct device *parent __unused, struct device *self, void *aux) 188 { 189 struct pci_attach_args *pa = aux; 190 struct pciide_softc *sc = (struct pciide_softc *)self; 191 192 pciide_common_attach(sc, pa, 193 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 194 } 195 196 static void 197 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 198 { 199 struct pciide_channel *cp; 200 struct ata_channel *wdc_cp; 201 struct wdc_regs *wdr; 202 int channel, i; 203 bus_size_t dmasize; 204 pci_intr_handle_t intrhandle; 205 const char *intrstr; 206 207 /* 208 * Promise SATA controllers have 3 or 4 channels, 209 * the usual IDE registers are mapped in I/O space, with offsets. 210 */ 211 if (pci_intr_map(pa, &intrhandle) != 0) { 212 aprint_error("%s: couldn't map interrupt\n", 213 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 214 return; 215 } 216 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 217 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 218 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 219 220 if (sc->sc_pci_ih == NULL) { 221 aprint_error("%s: couldn't establish native-PCI interrupt", 222 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 223 if (intrstr != NULL) 224 aprint_normal(" at %s", intrstr); 225 aprint_normal("\n"); 226 return; 227 } 228 aprint_normal("%s: interrupting at %s\n", 229 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 230 intrstr ? intrstr : "unknown interrupt"); 231 232 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 233 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 234 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 235 if (!sc->sc_dma_ok) { 236 aprint_error("%s: couldn't map bus-master DMA registers\n", 237 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 238 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 239 return; 240 } 241 242 sc->sc_dmat = pa->pa_dmat; 243 244 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 245 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 246 &sc->sc_ba5_sh, NULL, NULL) != 0) { 247 aprint_error("%s: couldn't map IDE registers\n", 248 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 249 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 250 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 251 return; 252 } 253 254 aprint_normal("%s: bus-master DMA support present\n", 255 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 256 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 257 if (sc->sc_dma_ok) { 258 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 259 } 260 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 261 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 262 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 263 sc->sc_wdcdev.irqack = pdc203xx_irqack; 264 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 265 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 266 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 267 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 268 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 269 270 sc->sc_wdcdev.reset = pdcsata_do_reset; 271 272 switch (sc->sc_pp->ide_product) { 273 case PCI_PRODUCT_PROMISE_PDC20318: 274 case PCI_PRODUCT_PROMISE_PDC20319: 275 case PCI_PRODUCT_PROMISE_PDC20371: 276 case PCI_PRODUCT_PROMISE_PDC20375: 277 case PCI_PRODUCT_PROMISE_PDC20376: 278 case PCI_PRODUCT_PROMISE_PDC20377: 279 case PCI_PRODUCT_PROMISE_PDC20378: 280 case PCI_PRODUCT_PROMISE_PDC20379: 281 default: 282 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 0x00ff0033); 283 sc->sc_wdcdev.sc_atac.atac_nchannels = 284 (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 285 PDC203xx_NCHANNELS : 3; 286 287 break; 288 289 case PCI_PRODUCT_PROMISE_PDC40518: 290 case PCI_PRODUCT_PROMISE_PDC40519: 291 case PCI_PRODUCT_PROMISE_PDC40718: 292 case PCI_PRODUCT_PROMISE_PDC40719: 293 case PCI_PRODUCT_PROMISE_PDC40779: 294 case PCI_PRODUCT_PROMISE_PDC20571: 295 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 296 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_NCHANNELS; 297 298 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 299 300 break; 301 case PCI_PRODUCT_PROMISE_PDC20575: 302 case PCI_PRODUCT_PROMISE_PDC20579: 303 case PCI_PRODUCT_PROMISE_PDC20771: 304 case PCI_PRODUCT_PROMISE_PDC20775: 305 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 306 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_NCHANNELS; 307 308 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 309 310 break; 311 } 312 313 wdc_allocate_regs(&sc->sc_wdcdev); 314 315 sc->sc_wdcdev.dma_arg = sc; 316 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 317 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 318 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 319 320 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 321 channel++) { 322 cp = &sc->pciide_channels[channel]; 323 sc->wdc_chanarray[channel] = &cp->ata_channel; 324 325 cp->ih = sc->sc_pci_ih; 326 cp->name = NULL; 327 cp->ata_channel.ch_channel = channel; 328 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 329 cp->ata_channel.ch_queue = 330 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 331 cp->ata_channel.ch_ndrive = 2; 332 if (cp->ata_channel.ch_queue == NULL) { 333 aprint_error("%s channel %d: " 334 "can't allocate memory for command queue\n", 335 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 336 goto next_channel; 337 } 338 wdc_cp = &cp->ata_channel; 339 wdr = CHAN_TO_WDC_REGS(wdc_cp); 340 341 wdr->ctl_iot = sc->sc_ba5_st; 342 wdr->cmd_iot = sc->sc_ba5_st; 343 344 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 345 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 346 aprint_error("%s: couldn't map channel %d ctl regs\n", 347 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 348 channel); 349 goto next_channel; 350 } 351 for (i = 0; i < WDC_NREG; i++) { 352 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 353 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 354 &wdr->cmd_iohs[i]) != 0) { 355 aprint_error("%s: couldn't map channel %d cmd " 356 "regs\n", 357 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 358 channel); 359 goto next_channel; 360 } 361 } 362 wdc_init_shadow_regs(wdc_cp); 363 364 /* 365 * subregion de busmaster registers. They're spread all over 366 * the controller's register space :(. They are also 4 bytes 367 * sized, with some specific extentions in the extra bits. 368 * It also seems that the IDEDMA_CTL register isn't available. 369 */ 370 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 371 0x260 + (channel << 7), 1, 372 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 373 aprint_normal("%s channel %d: can't subregion DMA " 374 "registers\n", 375 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 376 goto next_channel; 377 } 378 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 379 0x244 + (channel << 7), 4, 380 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 381 aprint_normal("%s channel %d: can't subregion DMA " 382 "registers\n", 383 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 384 goto next_channel; 385 } 386 387 wdcattach(wdc_cp); 388 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 389 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 390 0) & ~0x00003f9f) | (channel + 1)); 391 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 392 (channel + 1) << 2, 0x00000001); 393 next_channel: 394 continue; 395 } 396 return; 397 } 398 399 static void 400 pdc203xx_setup_channel(struct ata_channel *chp) 401 { 402 struct ata_drive_datas *drvp; 403 int drive, s; 404 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 405 406 pciide_channel_dma_setup(cp); 407 408 for (drive = 0; drive < 2; drive++) { 409 drvp = &chp->ch_drive[drive]; 410 if ((drvp->drive_flags & DRIVE) == 0) 411 continue; 412 if (drvp->drive_flags & DRIVE_UDMA) { 413 s = splbio(); 414 drvp->drive_flags &= ~DRIVE_DMA; 415 splx(s); 416 } 417 } 418 } 419 420 static int 421 pdcsata_pci_intr(void *arg) 422 { 423 struct pciide_softc *sc = arg; 424 struct pciide_channel *cp; 425 struct ata_channel *wdc_cp; 426 int i, rv, crv; 427 u_int32_t scr, status, chanbase; 428 429 rv = 0; 430 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 431 if (scr == 0xffffffff) return(rv); 432 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 433 scr = scr & 0x0000ffff; 434 if (!scr) return(rv); 435 436 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 437 cp = &sc->pciide_channels[i]; 438 wdc_cp = &cp->ata_channel; 439 if (scr & (1 << (i + 1))) { 440 chanbase = PDC_CHANNELBASE(i) + 0x48; 441 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 442 if (status & PDC_ERRMASK) { 443 chanbase = PDC_CHANNELBASE(i) + 0x60; 444 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 445 status |= 0x800; 446 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 447 status &= ~0x800; 448 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 449 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 450 continue; 451 } 452 crv = wdcintr(wdc_cp); 453 if (crv == 0) { 454 printf("%s:%d: bogus intr (reg 0x%x)\n", 455 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 456 i, scr); 457 } else 458 rv = 1; 459 } 460 } 461 return rv; 462 } 463 464 static void 465 pdc203xx_irqack(struct ata_channel *chp) 466 { 467 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 468 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 469 470 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 471 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 472 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 473 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 474 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 475 } 476 477 static int 478 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 479 size_t datalen, int flags) 480 { 481 struct pciide_softc *sc = v; 482 483 return pciide_dma_dmamap_setup(sc, channel, drive, 484 databuf, datalen, flags); 485 } 486 487 static void 488 pdc203xx_dma_start(void *v, int channel, int drive) 489 { 490 struct pciide_softc *sc = v; 491 struct pciide_channel *cp = &sc->pciide_channels[channel]; 492 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 493 494 /* Write table addr */ 495 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 496 dma_maps->dmamap_table->dm_segs[0].ds_addr); 497 /* start DMA engine */ 498 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 499 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 500 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 501 } 502 503 static int 504 pdc203xx_dma_finish(void *v, int channel, int drive, int force __unused) 505 { 506 struct pciide_softc *sc = v; 507 struct pciide_channel *cp = &sc->pciide_channels[channel]; 508 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 509 510 /* stop DMA channel */ 511 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 512 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 513 0) & ~0x80)); 514 515 /* Unload the map of the data buffer */ 516 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 517 dma_maps->dmamap_xfer->dm_mapsize, 518 (dma_maps->dma_flags & WDC_DMA_READ) ? 519 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 520 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 521 522 return 0; 523 } 524 525 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 526 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 527 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 528 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 529 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 530 531 532 #define SCONTROL_WRITE(sc,channel,scontrol) \ 533 bus_space_write_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 534 PDC205_SCONTROL(channel), scontrol) 535 536 #define SSTATUS_READ(sc,channel) \ 537 bus_space_read_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 538 PDC205_SSTATUS(channel)) 539 540 541 542 static void 543 pdcsata_do_reset(struct ata_channel *chp, int poll) 544 { 545 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 546 int reset, status, i, chanbase; 547 548 /* reset SATA */ 549 reset = (1 << 11); 550 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 551 for (i = 0; i < 11;i ++) { 552 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 553 if (status & reset) break; 554 delay(100); 555 status |= reset; 556 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 557 } 558 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 559 status &= ~reset; 560 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 561 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 562 563 wdc_do_reset(chp, poll); 564 565 } 566 567 static void 568 pdc205xx_drv_probe(struct ata_channel *chp) 569 { 570 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 571 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 572 u_int32_t scontrol, sstatus; 573 u_int16_t scnt, sn, cl, ch; 574 int i, s; 575 576 /* XXX This should be done by other code. */ 577 for (i = 0; i < 2; i++) { 578 chp->ch_drive[i].chnl_softc = chp; 579 chp->ch_drive[i].drive = i; 580 } 581 582 SCONTROL_WRITE(sc, chp->ch_channel, 0); 583 delay(50*1000); 584 585 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 586 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 587 delay(50*1000); 588 589 scontrol &= ~SControl_DET_INIT; 590 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 591 delay(50*1000); 592 593 sstatus = SSTATUS_READ(sc,chp->ch_channel); 594 595 switch (sstatus & SStatus_DET_mask) { 596 case SStatus_DET_NODEV: 597 /* No Device; be silent. */ 598 break; 599 600 case SStatus_DET_DEV_NE: 601 aprint_error("%s: port %d: device connected, but " 602 "communication not established\n", 603 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 604 break; 605 606 case SStatus_DET_OFFLINE: 607 aprint_error("%s: port %d: PHY offline\n", 608 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 609 break; 610 611 case SStatus_DET_DEV: 612 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 613 WDSD_IBM); 614 delay(10); /* 400ns delay */ 615 scnt = bus_space_read_2(wdr->cmd_iot, 616 wdr->cmd_iohs[wd_seccnt], 0); 617 sn = bus_space_read_2(wdr->cmd_iot, 618 wdr->cmd_iohs[wd_sector], 0); 619 cl = bus_space_read_2(wdr->cmd_iot, 620 wdr->cmd_iohs[wd_cyl_lo], 0); 621 ch = bus_space_read_2(wdr->cmd_iot, 622 wdr->cmd_iohs[wd_cyl_hi], 0); 623 #if 0 624 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 625 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 626 scnt, sn, cl, ch); 627 #endif 628 /* 629 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 630 * cases we get wrong values here, so ignore it. 631 */ 632 s = splbio(); 633 if (cl == 0x14 && ch == 0xeb) 634 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 635 else 636 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 637 splx(s); 638 #if 0 639 aprint_normal("%s: port %d: device present, speed: %s\n", 640 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 641 sata_speed(sstatus)); 642 #endif 643 break; 644 645 default: 646 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 647 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 648 sstatus); 649 } 650 } 651
Indexes created Tue Sep 30 11:09:46 GMT 2025