pdcsata.c revision 1.14
1 /* $NetBSD: pdcsata.c,v 1.14 2006/11/16 01:33:10 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.14 2006/11/16 01:33:10 christos Exp $"); 34 35 #include <sys/types.h> 36 #include <sys/malloc.h> 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcidevs.h> 42 #include <dev/pci/pciidereg.h> 43 #include <dev/pci/pciidevar.h> 44 #include <dev/ata/atareg.h> 45 #include <dev/ata/satavar.h> 46 #include <dev/ata/satareg.h> 47 48 #define PDC203xx_SATA_NCHANNELS 4 49 #define PDC203xx_COMBO_NCHANNELS 3 50 #define PDC40718_SATA_NCHANNELS 4 51 #define PDC20575_COMBO_NCHANNELS 3 52 53 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 54 55 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 56 #define PDC_ERRMASK 0x00780700 57 58 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 59 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 60 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 61 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 62 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 63 64 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 65 static void pdc203xx_setup_channel(struct ata_channel *); 66 static void pdc203xx_irqack(struct ata_channel *); 67 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 68 static void pdc203xx_dma_start(void *,int ,int); 69 static int pdc203xx_dma_finish(void *, int, int, int); 70 static void pdc203xx_combo_probe(struct ata_channel *); 71 static int pdcsata_pci_intr(void *); 72 static void pdcsata_do_reset(struct ata_channel *, int); 73 74 static int pdcsata_match(struct device *, struct cfdata *, void *); 75 static void pdcsata_attach(struct device *, struct device *, void *); 76 77 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 78 pdcsata_match, pdcsata_attach, NULL, NULL); 79 80 static const struct pciide_product_desc pciide_pdcsata_products[] = { 81 { PCI_PRODUCT_PROMISE_PDC20318, 82 0, 83 "Promise PDC20318 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20319, 87 0, 88 "Promise PDC20319 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20371, 92 0, 93 "Promise PDC20371 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20375, 97 0, 98 "Promise PDC20375 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_PDC20376, 102 0, 103 "Promise PDC20376 SATA150 controller", 104 pdcsata_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_PDC20377, 107 0, 108 "Promise PDC20377 SATA150 controller", 109 pdcsata_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_PDC20378, 112 0, 113 "Promise PDC20378 SATA150 controller", 114 pdcsata_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_PDC20379, 117 0, 118 "Promise PDC20379 SATA150 controller", 119 pdcsata_chip_map, 120 }, 121 { PCI_PRODUCT_PROMISE_PDC40518, 122 0, 123 "Promise PDC40518 SATA150 controller", 124 pdcsata_chip_map, 125 }, 126 { PCI_PRODUCT_PROMISE_PDC40519, 127 0, 128 "Promise PDC40519 SATA 150 controller", 129 pdcsata_chip_map, 130 }, 131 { PCI_PRODUCT_PROMISE_PDC40718, 132 0, 133 "Promise PDC40718 SATA300 controller", 134 pdcsata_chip_map, 135 }, 136 { PCI_PRODUCT_PROMISE_PDC40719, 137 0, 138 "Promise PDC40719 SATA300 controller", 139 pdcsata_chip_map, 140 }, 141 { PCI_PRODUCT_PROMISE_PDC40779, 142 0, 143 "Promise PDC40779 SATA300 controller", 144 pdcsata_chip_map, 145 }, 146 { PCI_PRODUCT_PROMISE_PDC20571, 147 0, 148 "Promise PDC20571 SATA150 controller", 149 pdcsata_chip_map, 150 }, 151 { PCI_PRODUCT_PROMISE_PDC20575, 152 0, 153 "Promise PDC20575 SATA150 controller", 154 pdcsata_chip_map, 155 }, 156 { PCI_PRODUCT_PROMISE_PDC20579, 157 0, 158 "Promise PDC20579 SATA150 controller", 159 pdcsata_chip_map, 160 }, 161 { PCI_PRODUCT_PROMISE_PDC20771, 162 0, 163 "Promise PDC20771 SATA300 controller", 164 pdcsata_chip_map, 165 }, 166 { PCI_PRODUCT_PROMISE_PDC20775, 167 0, 168 "Promise PDC20775 SATA300 controller", 169 pdcsata_chip_map, 170 }, 171 { PCI_PRODUCT_PROMISE_PDC20617, 172 0, 173 "Promise PDC2020617 Ultra/133 controller", 174 pdcsata_chip_map, 175 }, 176 { PCI_PRODUCT_PROMISE_PDC20618, 177 0, 178 "Promise PDC20618 Ultra/133 controller", 179 pdcsata_chip_map, 180 }, 181 { PCI_PRODUCT_PROMISE_PDC20619, 182 0, 183 "Promise PDC20619 Ultra/133 controller", 184 pdcsata_chip_map, 185 }, 186 { PCI_PRODUCT_PROMISE_PDC20620, 187 0, 188 "Promise PDC20620 Ultra/133 controller", 189 pdcsata_chip_map, 190 }, 191 { PCI_PRODUCT_PROMISE_PDC20621, 192 0, 193 "Promise PDC20621 Ultra/133 controller", 194 pdcsata_chip_map, 195 }, 196 { 0, 197 0, 198 NULL, 199 NULL 200 } 201 }; 202 203 static int 204 pdcsata_match(struct device *parent, struct cfdata *match, 205 void *aux) 206 { 207 struct pci_attach_args *pa = aux; 208 209 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 210 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 211 return (2); 212 } 213 return (0); 214 } 215 216 static void 217 pdcsata_attach(struct device *parent, struct device *self, void *aux) 218 { 219 struct pci_attach_args *pa = aux; 220 struct pciide_softc *sc = (struct pciide_softc *)self; 221 222 pciide_common_attach(sc, pa, 223 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 224 } 225 226 static void 227 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 228 { 229 struct pciide_channel *cp; 230 struct ata_channel *wdc_cp; 231 struct wdc_regs *wdr; 232 int channel, i; 233 bus_size_t dmasize; 234 pci_intr_handle_t intrhandle; 235 const char *intrstr; 236 237 /* 238 * Promise SATA controllers have 3 or 4 channels, 239 * the usual IDE registers are mapped in I/O space, with offsets. 240 */ 241 if (pci_intr_map(pa, &intrhandle) != 0) { 242 aprint_error("%s: couldn't map interrupt\n", 243 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 244 return; 245 } 246 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 247 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 248 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 249 250 if (sc->sc_pci_ih == NULL) { 251 aprint_error("%s: couldn't establish native-PCI interrupt", 252 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 253 if (intrstr != NULL) 254 aprint_normal(" at %s", intrstr); 255 aprint_normal("\n"); 256 return; 257 } 258 aprint_normal("%s: interrupting at %s\n", 259 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 260 intrstr ? intrstr : "unknown interrupt"); 261 262 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 263 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 264 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 265 if (!sc->sc_dma_ok) { 266 aprint_error("%s: couldn't map bus-master DMA registers\n", 267 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 268 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 269 return; 270 } 271 272 sc->sc_dmat = pa->pa_dmat; 273 274 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 275 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 276 &sc->sc_ba5_sh, NULL, NULL) != 0) { 277 aprint_error("%s: couldn't map IDE registers\n", 278 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 279 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 280 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 281 return; 282 } 283 284 aprint_normal("%s: bus-master DMA support present\n", 285 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 286 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 287 if (sc->sc_dma_ok) { 288 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 289 } 290 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 291 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 292 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 293 sc->sc_wdcdev.irqack = pdc203xx_irqack; 294 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 295 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 296 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 297 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 298 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 299 300 sc->sc_wdcdev.reset = pdcsata_do_reset; 301 302 switch (sc->sc_pp->ide_product) { 303 case PCI_PRODUCT_PROMISE_PDC20318: 304 case PCI_PRODUCT_PROMISE_PDC20319: 305 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 306 0x00ff0033); 307 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 308 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_SATA_NCHANNELS; 309 break; 310 case PCI_PRODUCT_PROMISE_PDC20371: 311 case PCI_PRODUCT_PROMISE_PDC20375: 312 case PCI_PRODUCT_PROMISE_PDC20376: 313 case PCI_PRODUCT_PROMISE_PDC20377: 314 case PCI_PRODUCT_PROMISE_PDC20378: 315 case PCI_PRODUCT_PROMISE_PDC20379: 316 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 317 0x00ff0033); 318 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 319 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_COMBO_NCHANNELS; 320 break; 321 322 case PCI_PRODUCT_PROMISE_PDC40518: 323 case PCI_PRODUCT_PROMISE_PDC40519: 324 case PCI_PRODUCT_PROMISE_PDC40718: 325 case PCI_PRODUCT_PROMISE_PDC40719: 326 case PCI_PRODUCT_PROMISE_PDC40779: 327 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 328 0x00ff00ff); 329 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_SATA_NCHANNELS; 330 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 331 break; 332 333 case PCI_PRODUCT_PROMISE_PDC20571: 334 case PCI_PRODUCT_PROMISE_PDC20575: 335 case PCI_PRODUCT_PROMISE_PDC20579: 336 case PCI_PRODUCT_PROMISE_PDC20771: 337 case PCI_PRODUCT_PROMISE_PDC20775: 338 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 339 0x00ff00ff); 340 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_COMBO_NCHANNELS; 341 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 342 break; 343 344 case PCI_PRODUCT_PROMISE_PDC20617: 345 case PCI_PRODUCT_PROMISE_PDC20618: 346 case PCI_PRODUCT_PROMISE_PDC20619: 347 case PCI_PRODUCT_PROMISE_PDC20620: 348 case PCI_PRODUCT_PROMISE_PDC20621: 349 sc->sc_wdcdev.sc_atac.atac_nchannels = 350 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 351 0x48) & 0x01) ? 1 : 0) + 352 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 353 0x48) & 0x02) ? 1 : 0) + 354 2; 355 sc->sc_wdcdev.sc_atac.atac_probe = wdc_drvprobe; 356 357 default: 358 aprint_error("unknown promise product 0x%x\n", 359 sc->sc_pp->ide_product); 360 } 361 362 wdc_allocate_regs(&sc->sc_wdcdev); 363 364 sc->sc_wdcdev.dma_arg = sc; 365 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 366 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 367 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 368 369 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 370 channel++) { 371 cp = &sc->pciide_channels[channel]; 372 sc->wdc_chanarray[channel] = &cp->ata_channel; 373 374 cp->ih = sc->sc_pci_ih; 375 cp->name = NULL; 376 cp->ata_channel.ch_channel = channel; 377 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 378 cp->ata_channel.ch_queue = 379 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 380 cp->ata_channel.ch_ndrive = 2; 381 if (cp->ata_channel.ch_queue == NULL) { 382 aprint_error("%s channel %d: " 383 "can't allocate memory for command queue\n", 384 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 385 goto next_channel; 386 } 387 wdc_cp = &cp->ata_channel; 388 wdr = CHAN_TO_WDC_REGS(wdc_cp); 389 390 wdr->ctl_iot = sc->sc_ba5_st; 391 wdr->cmd_iot = sc->sc_ba5_st; 392 393 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 394 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 395 aprint_error("%s: couldn't map channel %d ctl regs\n", 396 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 397 channel); 398 goto next_channel; 399 } 400 for (i = 0; i < WDC_NREG; i++) { 401 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 402 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 403 &wdr->cmd_iohs[i]) != 0) { 404 aprint_error("%s: couldn't map channel %d cmd " 405 "regs\n", 406 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 407 channel); 408 goto next_channel; 409 } 410 } 411 wdc_init_shadow_regs(wdc_cp); 412 413 /* 414 * subregion de busmaster registers. They're spread all over 415 * the controller's register space :(. They are also 4 bytes 416 * sized, with some specific extentions in the extra bits. 417 * It also seems that the IDEDMA_CTL register isn't available. 418 */ 419 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 420 0x260 + (channel << 7), 1, 421 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 422 aprint_normal("%s channel %d: can't subregion DMA " 423 "registers\n", 424 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 425 goto next_channel; 426 } 427 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 428 0x244 + (channel << 7), 4, 429 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 430 aprint_normal("%s channel %d: can't subregion DMA " 431 "registers\n", 432 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 433 goto next_channel; 434 } 435 436 /* subregion the SATA registers */ 437 if (sc->sc_wdcdev.sc_atac.atac_probe == wdc_sataprobe || 438 (sc->sc_wdcdev.sc_atac.atac_probe == pdc203xx_combo_probe 439 && channel < 2)) { 440 wdr->sata_iot = sc->sc_ba5_st; 441 wdr->sata_baseioh = sc->sc_ba5_sh; 442 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 443 PDC205_SSTATUS(channel), 1, 444 &wdr->sata_status) != 0) { 445 aprint_error("%s: couldn't map channel %d " 446 "sata_status regs\n", 447 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 448 channel); 449 goto next_channel; 450 } 451 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 452 PDC205_SERROR(channel), 1, &wdr->sata_error) != 0) { 453 aprint_error("%s: couldn't map channel %d " 454 "sata_error regs\n", 455 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 456 channel); 457 goto next_channel; 458 } 459 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 460 PDC205_SCONTROL(channel), 1, 461 &wdr->sata_control) != 0) { 462 aprint_error("%s: couldn't map channel %d " 463 "sata_control regs\n", 464 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 465 channel); 466 goto next_channel; 467 } 468 } 469 470 wdcattach(wdc_cp); 471 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 472 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 473 0) & ~0x00003f9f) | (channel + 1)); 474 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 475 (channel + 1) << 2, 0x00000001); 476 next_channel: 477 continue; 478 } 479 return; 480 } 481 482 static void 483 pdc203xx_combo_probe(struct ata_channel *chp) 484 { 485 if (chp->ch_channel < 2) 486 wdc_sataprobe(chp); 487 else 488 wdc_drvprobe(chp); 489 } 490 491 static void 492 pdc203xx_setup_channel(struct ata_channel *chp) 493 { 494 struct ata_drive_datas *drvp; 495 int drive, s; 496 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 497 498 pciide_channel_dma_setup(cp); 499 500 for (drive = 0; drive < 2; drive++) { 501 drvp = &chp->ch_drive[drive]; 502 if ((drvp->drive_flags & DRIVE) == 0) 503 continue; 504 if (drvp->drive_flags & DRIVE_UDMA) { 505 s = splbio(); 506 drvp->drive_flags &= ~DRIVE_DMA; 507 splx(s); 508 } 509 } 510 } 511 512 static int 513 pdcsata_pci_intr(void *arg) 514 { 515 struct pciide_softc *sc = arg; 516 struct pciide_channel *cp; 517 struct ata_channel *wdc_cp; 518 int i, rv, crv; 519 u_int32_t scr, status, chanbase; 520 521 rv = 0; 522 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 523 if (scr == 0xffffffff) return(rv); 524 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 525 scr = scr & 0x0000ffff; 526 if (!scr) return(rv); 527 528 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 529 cp = &sc->pciide_channels[i]; 530 wdc_cp = &cp->ata_channel; 531 if (scr & (1 << (i + 1))) { 532 chanbase = PDC_CHANNELBASE(i) + 0x48; 533 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 534 if (status & PDC_ERRMASK) { 535 chanbase = PDC_CHANNELBASE(i) + 0x60; 536 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 537 status |= 0x800; 538 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 539 status &= ~0x800; 540 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 541 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 542 continue; 543 } 544 crv = wdcintr(wdc_cp); 545 if (crv == 0) { 546 printf("%s:%d: bogus intr (reg 0x%x)\n", 547 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 548 i, scr); 549 } else 550 rv = 1; 551 } 552 } 553 return rv; 554 } 555 556 static void 557 pdc203xx_irqack(struct ata_channel *chp) 558 { 559 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 560 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 561 562 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 563 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 564 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 565 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 566 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 567 } 568 569 static int 570 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 571 size_t datalen, int flags) 572 { 573 struct pciide_softc *sc = v; 574 575 return pciide_dma_dmamap_setup(sc, channel, drive, 576 databuf, datalen, flags); 577 } 578 579 static void 580 pdc203xx_dma_start(void *v, int channel, int drive) 581 { 582 struct pciide_softc *sc = v; 583 struct pciide_channel *cp = &sc->pciide_channels[channel]; 584 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 585 586 /* Write table addr */ 587 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 588 dma_maps->dmamap_table->dm_segs[0].ds_addr); 589 /* start DMA engine */ 590 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 591 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 592 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 593 } 594 595 static int 596 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 597 { 598 struct pciide_softc *sc = v; 599 struct pciide_channel *cp = &sc->pciide_channels[channel]; 600 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 601 602 /* stop DMA channel */ 603 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 604 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 605 0) & ~0x80)); 606 607 /* Unload the map of the data buffer */ 608 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 609 dma_maps->dmamap_xfer->dm_mapsize, 610 (dma_maps->dma_flags & WDC_DMA_READ) ? 611 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 612 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 613 614 return 0; 615 } 616 617 618 static void 619 pdcsata_do_reset(struct ata_channel *chp, int poll) 620 { 621 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 622 int reset, status, i, chanbase; 623 624 /* reset SATA */ 625 reset = (1 << 11); 626 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 627 for (i = 0; i < 11;i ++) { 628 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 629 if (status & reset) break; 630 delay(100); 631 status |= reset; 632 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 633 } 634 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 635 status &= ~reset; 636 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 637 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 638 639 wdc_do_reset(chp, poll); 640 641 } 642
Indexes created Mon Sep 29 21:09:56 GMT 2025