pdcsata.c revision 1.16
1 /* $NetBSD: pdcsata.c,v 1.16 2008/03/18 20:46:37 cube Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.16 2008/03/18 20:46:37 cube Exp $"); 34 35 #include <sys/types.h> 36 #include <sys/malloc.h> 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcidevs.h> 42 #include <dev/pci/pciidereg.h> 43 #include <dev/pci/pciidevar.h> 44 #include <dev/ata/atareg.h> 45 #include <dev/ata/satavar.h> 46 #include <dev/ata/satareg.h> 47 48 #define PDC203xx_SATA_NCHANNELS 4 49 #define PDC203xx_COMBO_NCHANNELS 3 50 #define PDC40718_SATA_NCHANNELS 4 51 #define PDC20575_COMBO_NCHANNELS 3 52 53 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 54 55 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 56 #define PDC_ERRMASK 0x00780700 57 58 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 59 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 60 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 61 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 62 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 63 64 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 65 static void pdc203xx_setup_channel(struct ata_channel *); 66 static void pdc203xx_irqack(struct ata_channel *); 67 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 68 static void pdc203xx_dma_start(void *,int ,int); 69 static int pdc203xx_dma_finish(void *, int, int, int); 70 static void pdc203xx_combo_probe(struct ata_channel *); 71 static int pdcsata_pci_intr(void *); 72 static void pdcsata_do_reset(struct ata_channel *, int); 73 74 static int pdcsata_match(device_t, cfdata_t, void *); 75 static void pdcsata_attach(device_t, device_t, void *); 76 77 CFATTACH_DECL_NEW(pdcsata, sizeof(struct pciide_softc), 78 pdcsata_match, pdcsata_attach, NULL, NULL); 79 80 static const struct pciide_product_desc pciide_pdcsata_products[] = { 81 { PCI_PRODUCT_PROMISE_PDC20318, 82 0, 83 "Promise PDC20318 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20319, 87 0, 88 "Promise PDC20319 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20371, 92 0, 93 "Promise PDC20371 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20375, 97 0, 98 "Promise PDC20375 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_PDC20376, 102 0, 103 "Promise PDC20376 SATA150 controller", 104 pdcsata_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_PDC20377, 107 0, 108 "Promise PDC20377 SATA150 controller", 109 pdcsata_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_PDC20378, 112 0, 113 "Promise PDC20378 SATA150 controller", 114 pdcsata_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_PDC20379, 117 0, 118 "Promise PDC20379 SATA150 controller", 119 pdcsata_chip_map, 120 }, 121 { PCI_PRODUCT_PROMISE_PDC40518, 122 0, 123 "Promise PDC40518 SATA150 controller", 124 pdcsata_chip_map, 125 }, 126 { PCI_PRODUCT_PROMISE_PDC40519, 127 0, 128 "Promise PDC40519 SATA 150 controller", 129 pdcsata_chip_map, 130 }, 131 { PCI_PRODUCT_PROMISE_PDC40718, 132 0, 133 "Promise PDC40718 SATA300 controller", 134 pdcsata_chip_map, 135 }, 136 { PCI_PRODUCT_PROMISE_PDC40719, 137 0, 138 "Promise PDC40719 SATA300 controller", 139 pdcsata_chip_map, 140 }, 141 { PCI_PRODUCT_PROMISE_PDC40779, 142 0, 143 "Promise PDC40779 SATA300 controller", 144 pdcsata_chip_map, 145 }, 146 { PCI_PRODUCT_PROMISE_PDC20571, 147 0, 148 "Promise PDC20571 SATA150 controller", 149 pdcsata_chip_map, 150 }, 151 { PCI_PRODUCT_PROMISE_PDC20575, 152 0, 153 "Promise PDC20575 SATA150 controller", 154 pdcsata_chip_map, 155 }, 156 { PCI_PRODUCT_PROMISE_PDC20579, 157 0, 158 "Promise PDC20579 SATA150 controller", 159 pdcsata_chip_map, 160 }, 161 { PCI_PRODUCT_PROMISE_PDC20771, 162 0, 163 "Promise PDC20771 SATA300 controller", 164 pdcsata_chip_map, 165 }, 166 { PCI_PRODUCT_PROMISE_PDC20775, 167 0, 168 "Promise PDC20775 SATA300 controller", 169 pdcsata_chip_map, 170 }, 171 { PCI_PRODUCT_PROMISE_PDC20617, 172 0, 173 "Promise PDC2020617 Ultra/133 controller", 174 pdcsata_chip_map, 175 }, 176 { PCI_PRODUCT_PROMISE_PDC20618, 177 0, 178 "Promise PDC20618 Ultra/133 controller", 179 pdcsata_chip_map, 180 }, 181 { PCI_PRODUCT_PROMISE_PDC20619, 182 0, 183 "Promise PDC20619 Ultra/133 controller", 184 pdcsata_chip_map, 185 }, 186 { PCI_PRODUCT_PROMISE_PDC20620, 187 0, 188 "Promise PDC20620 Ultra/133 controller", 189 pdcsata_chip_map, 190 }, 191 { PCI_PRODUCT_PROMISE_PDC20621, 192 0, 193 "Promise PDC20621 Ultra/133 controller", 194 pdcsata_chip_map, 195 }, 196 { 0, 197 0, 198 NULL, 199 NULL 200 } 201 }; 202 203 static int 204 pdcsata_match(device_t parent, cfdata_t match, void *aux) 205 { 206 struct pci_attach_args *pa = aux; 207 208 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 209 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 210 return (2); 211 } 212 return (0); 213 } 214 215 static void 216 pdcsata_attach(device_t parent, device_t self, void *aux) 217 { 218 struct pci_attach_args *pa = aux; 219 struct pciide_softc *sc = device_private(self); 220 221 sc->sc_wdcdev.sc_atac.atac_dev = self; 222 223 pciide_common_attach(sc, pa, 224 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 225 } 226 227 static void 228 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 229 { 230 struct pciide_channel *cp; 231 struct ata_channel *wdc_cp; 232 struct wdc_regs *wdr; 233 int channel, i; 234 bus_size_t dmasize; 235 pci_intr_handle_t intrhandle; 236 const char *intrstr; 237 238 /* 239 * Promise SATA controllers have 3 or 4 channels, 240 * the usual IDE registers are mapped in I/O space, with offsets. 241 */ 242 if (pci_intr_map(pa, &intrhandle) != 0) { 243 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 244 "couldn't map interrupt\n"); 245 return; 246 } 247 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 248 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 249 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 250 251 if (sc->sc_pci_ih == NULL) { 252 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 253 "couldn't establish native-PCI interrupt"); 254 if (intrstr != NULL) 255 aprint_normal(" at %s", intrstr); 256 aprint_normal("\n"); 257 return; 258 } 259 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 260 "interrupting at %s\n", 261 intrstr ? intrstr : "unknown interrupt"); 262 263 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 264 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 265 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 266 if (!sc->sc_dma_ok) { 267 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 268 "couldn't map bus-master DMA registers\n"); 269 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 270 return; 271 } 272 273 sc->sc_dmat = pa->pa_dmat; 274 275 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 276 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 277 &sc->sc_ba5_sh, NULL, NULL) != 0) { 278 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 279 "couldn't map IDE registers\n"); 280 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 281 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 282 return; 283 } 284 285 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 286 "bus-master DMA support present\n"); 287 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 288 if (sc->sc_dma_ok) { 289 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 290 } 291 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 292 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 293 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 294 sc->sc_wdcdev.irqack = pdc203xx_irqack; 295 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 296 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 297 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 298 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 299 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 300 301 sc->sc_wdcdev.reset = pdcsata_do_reset; 302 303 switch (sc->sc_pp->ide_product) { 304 case PCI_PRODUCT_PROMISE_PDC20318: 305 case PCI_PRODUCT_PROMISE_PDC20319: 306 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 307 0x00ff0033); 308 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 309 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_SATA_NCHANNELS; 310 break; 311 case PCI_PRODUCT_PROMISE_PDC20371: 312 case PCI_PRODUCT_PROMISE_PDC20375: 313 case PCI_PRODUCT_PROMISE_PDC20376: 314 case PCI_PRODUCT_PROMISE_PDC20377: 315 case PCI_PRODUCT_PROMISE_PDC20378: 316 case PCI_PRODUCT_PROMISE_PDC20379: 317 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 318 0x00ff0033); 319 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 320 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_COMBO_NCHANNELS; 321 break; 322 323 case PCI_PRODUCT_PROMISE_PDC40518: 324 case PCI_PRODUCT_PROMISE_PDC40519: 325 case PCI_PRODUCT_PROMISE_PDC40718: 326 case PCI_PRODUCT_PROMISE_PDC40719: 327 case PCI_PRODUCT_PROMISE_PDC40779: 328 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 329 0x00ff00ff); 330 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_SATA_NCHANNELS; 331 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 332 break; 333 334 case PCI_PRODUCT_PROMISE_PDC20571: 335 case PCI_PRODUCT_PROMISE_PDC20575: 336 case PCI_PRODUCT_PROMISE_PDC20579: 337 case PCI_PRODUCT_PROMISE_PDC20771: 338 case PCI_PRODUCT_PROMISE_PDC20775: 339 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 340 0x00ff00ff); 341 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_COMBO_NCHANNELS; 342 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 343 break; 344 345 case PCI_PRODUCT_PROMISE_PDC20617: 346 case PCI_PRODUCT_PROMISE_PDC20618: 347 case PCI_PRODUCT_PROMISE_PDC20619: 348 case PCI_PRODUCT_PROMISE_PDC20620: 349 case PCI_PRODUCT_PROMISE_PDC20621: 350 sc->sc_wdcdev.sc_atac.atac_nchannels = 351 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 352 0x48) & 0x01) ? 1 : 0) + 353 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 354 0x48) & 0x02) ? 1 : 0) + 355 2; 356 sc->sc_wdcdev.sc_atac.atac_probe = wdc_drvprobe; 357 358 default: 359 aprint_error("unknown promise product 0x%x\n", 360 sc->sc_pp->ide_product); 361 } 362 363 wdc_allocate_regs(&sc->sc_wdcdev); 364 365 sc->sc_wdcdev.dma_arg = sc; 366 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 367 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 368 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 369 370 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 371 channel++) { 372 cp = &sc->pciide_channels[channel]; 373 sc->wdc_chanarray[channel] = &cp->ata_channel; 374 375 cp->ih = sc->sc_pci_ih; 376 cp->name = NULL; 377 cp->ata_channel.ch_channel = channel; 378 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 379 cp->ata_channel.ch_queue = 380 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 381 cp->ata_channel.ch_ndrive = 2; 382 if (cp->ata_channel.ch_queue == NULL) { 383 aprint_error("%s channel %d: " 384 "can't allocate memory for command queue\n", 385 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 386 channel); 387 goto next_channel; 388 } 389 wdc_cp = &cp->ata_channel; 390 wdr = CHAN_TO_WDC_REGS(wdc_cp); 391 392 wdr->ctl_iot = sc->sc_ba5_st; 393 wdr->cmd_iot = sc->sc_ba5_st; 394 395 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 396 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 397 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 398 "couldn't map channel %d ctl regs\n", channel); 399 goto next_channel; 400 } 401 for (i = 0; i < WDC_NREG; i++) { 402 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 403 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 404 &wdr->cmd_iohs[i]) != 0) { 405 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 406 "couldn't map channel %d cmd regs\n", 407 channel); 408 goto next_channel; 409 } 410 } 411 wdc_init_shadow_regs(wdc_cp); 412 413 /* 414 * subregion de busmaster registers. They're spread all over 415 * the controller's register space :(. They are also 4 bytes 416 * sized, with some specific extentions in the extra bits. 417 * It also seems that the IDEDMA_CTL register isn't available. 418 */ 419 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 420 0x260 + (channel << 7), 1, 421 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 422 aprint_normal("%s channel %d: can't subregion DMA " 423 "registers\n", 424 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 425 channel); 426 goto next_channel; 427 } 428 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 429 0x244 + (channel << 7), 4, 430 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 431 aprint_normal("%s channel %d: can't subregion DMA " 432 "registers\n", 433 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 434 channel); 435 goto next_channel; 436 } 437 438 /* subregion the SATA registers */ 439 if (sc->sc_wdcdev.sc_atac.atac_probe == wdc_sataprobe || 440 (sc->sc_wdcdev.sc_atac.atac_probe == pdc203xx_combo_probe 441 && channel < 2)) { 442 wdr->sata_iot = sc->sc_ba5_st; 443 wdr->sata_baseioh = sc->sc_ba5_sh; 444 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 445 PDC205_SSTATUS(channel), 1, 446 &wdr->sata_status) != 0) { 447 aprint_error_dev( 448 sc->sc_wdcdev.sc_atac.atac_dev, 449 "couldn't map channel %d " 450 "sata_status regs\n", channel); 451 goto next_channel; 452 } 453 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 454 PDC205_SERROR(channel), 1, &wdr->sata_error) != 0) { 455 aprint_error_dev( 456 sc->sc_wdcdev.sc_atac.atac_dev, 457 "couldn't map channel %d " 458 "sata_error regs\n", channel); 459 goto next_channel; 460 } 461 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 462 PDC205_SCONTROL(channel), 1, 463 &wdr->sata_control) != 0) { 464 aprint_error_dev( 465 sc->sc_wdcdev.sc_atac.atac_dev, 466 "couldn't map channel %d " 467 "sata_control regs\n", channel); 468 goto next_channel; 469 } 470 } 471 472 wdcattach(wdc_cp); 473 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 474 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 475 0) & ~0x00003f9f) | (channel + 1)); 476 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 477 (channel + 1) << 2, 0x00000001); 478 next_channel: 479 continue; 480 } 481 return; 482 } 483 484 static void 485 pdc203xx_combo_probe(struct ata_channel *chp) 486 { 487 if (chp->ch_channel < 2) 488 wdc_sataprobe(chp); 489 else 490 wdc_drvprobe(chp); 491 } 492 493 static void 494 pdc203xx_setup_channel(struct ata_channel *chp) 495 { 496 struct ata_drive_datas *drvp; 497 int drive, s; 498 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 499 500 pciide_channel_dma_setup(cp); 501 502 for (drive = 0; drive < 2; drive++) { 503 drvp = &chp->ch_drive[drive]; 504 if ((drvp->drive_flags & DRIVE) == 0) 505 continue; 506 if (drvp->drive_flags & DRIVE_UDMA) { 507 s = splbio(); 508 drvp->drive_flags &= ~DRIVE_DMA; 509 splx(s); 510 } 511 } 512 } 513 514 static int 515 pdcsata_pci_intr(void *arg) 516 { 517 struct pciide_softc *sc = arg; 518 struct pciide_channel *cp; 519 struct ata_channel *wdc_cp; 520 int i, rv, crv; 521 u_int32_t scr, status, chanbase; 522 523 rv = 0; 524 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 525 if (scr == 0xffffffff) return(rv); 526 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 527 scr = scr & 0x0000ffff; 528 if (!scr) return(rv); 529 530 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 531 cp = &sc->pciide_channels[i]; 532 wdc_cp = &cp->ata_channel; 533 if (scr & (1 << (i + 1))) { 534 chanbase = PDC_CHANNELBASE(i) + 0x48; 535 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 536 if (status & PDC_ERRMASK) { 537 chanbase = PDC_CHANNELBASE(i) + 0x60; 538 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 539 status |= 0x800; 540 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 541 status &= ~0x800; 542 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 543 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 544 continue; 545 } 546 crv = wdcintr(wdc_cp); 547 if (crv == 0) { 548 aprint_error("%s:%d: bogus intr (reg 0x%x)\n", 549 device_xname( 550 sc->sc_wdcdev.sc_atac.atac_dev), i, scr); 551 } else 552 rv = 1; 553 } 554 } 555 return rv; 556 } 557 558 static void 559 pdc203xx_irqack(struct ata_channel *chp) 560 { 561 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 562 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 563 564 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 565 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 566 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 567 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 568 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 569 } 570 571 static int 572 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 573 size_t datalen, int flags) 574 { 575 struct pciide_softc *sc = v; 576 577 return pciide_dma_dmamap_setup(sc, channel, drive, 578 databuf, datalen, flags); 579 } 580 581 static void 582 pdc203xx_dma_start(void *v, int channel, int drive) 583 { 584 struct pciide_softc *sc = v; 585 struct pciide_channel *cp = &sc->pciide_channels[channel]; 586 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 587 588 /* Write table addr */ 589 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 590 dma_maps->dmamap_table->dm_segs[0].ds_addr); 591 /* start DMA engine */ 592 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 593 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 594 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 595 } 596 597 static int 598 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 599 { 600 struct pciide_softc *sc = v; 601 struct pciide_channel *cp = &sc->pciide_channels[channel]; 602 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 603 604 /* stop DMA channel */ 605 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 606 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 607 0) & ~0x80)); 608 609 /* Unload the map of the data buffer */ 610 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 611 dma_maps->dmamap_xfer->dm_mapsize, 612 (dma_maps->dma_flags & WDC_DMA_READ) ? 613 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 614 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 615 616 return 0; 617 } 618 619 620 static void 621 pdcsata_do_reset(struct ata_channel *chp, int poll) 622 { 623 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 624 int reset, status, i, chanbase; 625 626 /* reset SATA */ 627 reset = (1 << 11); 628 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 629 for (i = 0; i < 11;i ++) { 630 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 631 if (status & reset) break; 632 delay(100); 633 status |= reset; 634 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 635 } 636 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 637 status &= ~reset; 638 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 639 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 640 641 wdc_do_reset(chp, poll); 642 } 643
Indexes created Tue Sep 30 07:10:03 GMT 2025