pdcsata.c revision 1.19
1 /* $NetBSD: pdcsata.c,v 1.19 2010/11/05 18:07:24 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.19 2010/11/05 18:07:24 jakllsch Exp $"); 29 30 #include <sys/types.h> 31 #include <sys/malloc.h> 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/ata/atareg.h> 40 #include <dev/ata/satavar.h> 41 #include <dev/ata/satareg.h> 42 43 #define PDC203xx_SATA_NCHANNELS 4 44 #define PDC203xx_COMBO_NCHANNELS 3 45 #define PDC40718_SATA_NCHANNELS 4 46 #define PDC20575_COMBO_NCHANNELS 3 47 48 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 49 50 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 51 #define PDC_ERRMASK 0x00780700 52 53 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 54 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 55 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 56 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 57 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 58 59 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 60 static void pdc203xx_setup_channel(struct ata_channel *); 61 static void pdc203xx_irqack(struct ata_channel *); 62 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 63 static void pdc203xx_dma_start(void *,int ,int); 64 static int pdc203xx_dma_finish(void *, int, int, int); 65 static void pdc203xx_combo_probe(struct ata_channel *); 66 static int pdcsata_pci_intr(void *); 67 static void pdcsata_do_reset(struct ata_channel *, int); 68 69 static int pdcsata_match(device_t, cfdata_t, void *); 70 static void pdcsata_attach(device_t, device_t, void *); 71 72 CFATTACH_DECL_NEW(pdcsata, sizeof(struct pciide_softc), 73 pdcsata_match, pdcsata_attach, NULL, NULL); 74 75 static const struct pciide_product_desc pciide_pdcsata_products[] = { 76 { PCI_PRODUCT_PROMISE_PDC20318, 77 0, 78 "Promise PDC20318 SATA150 controller", 79 pdcsata_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_PDC20319, 82 0, 83 "Promise PDC20319 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20371, 87 0, 88 "Promise PDC20371 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20375, 92 0, 93 "Promise PDC20375 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20376, 97 0, 98 "Promise PDC20376 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_PDC20377, 102 0, 103 "Promise PDC20377 SATA150 controller", 104 pdcsata_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_PDC20378, 107 0, 108 "Promise PDC20378 SATA150 controller", 109 pdcsata_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_PDC20379, 112 0, 113 "Promise PDC20379 SATA150 controller", 114 pdcsata_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_PDC40518, 117 0, 118 "Promise PDC40518 SATA150 controller", 119 pdcsata_chip_map, 120 }, 121 { PCI_PRODUCT_PROMISE_PDC40519, 122 0, 123 "Promise PDC40519 SATA 150 controller", 124 pdcsata_chip_map, 125 }, 126 { PCI_PRODUCT_PROMISE_PDC40718, 127 0, 128 "Promise PDC40718 SATA300 controller", 129 pdcsata_chip_map, 130 }, 131 { PCI_PRODUCT_PROMISE_PDC40719, 132 0, 133 "Promise PDC40719 SATA300 controller", 134 pdcsata_chip_map, 135 }, 136 { PCI_PRODUCT_PROMISE_PDC40779, 137 0, 138 "Promise PDC40779 SATA300 controller", 139 pdcsata_chip_map, 140 }, 141 { PCI_PRODUCT_PROMISE_PDC20571, 142 0, 143 "Promise PDC20571 SATA150 controller", 144 pdcsata_chip_map, 145 }, 146 { PCI_PRODUCT_PROMISE_PDC20575, 147 0, 148 "Promise PDC20575 SATA150 controller", 149 pdcsata_chip_map, 150 }, 151 { PCI_PRODUCT_PROMISE_PDC20579, 152 0, 153 "Promise PDC20579 SATA150 controller", 154 pdcsata_chip_map, 155 }, 156 { PCI_PRODUCT_PROMISE_PDC20771, 157 0, 158 "Promise PDC20771 SATA300 controller", 159 pdcsata_chip_map, 160 }, 161 { PCI_PRODUCT_PROMISE_PDC20775, 162 0, 163 "Promise PDC20775 SATA300 controller", 164 pdcsata_chip_map, 165 }, 166 { PCI_PRODUCT_PROMISE_PDC20617, 167 0, 168 "Promise PDC2020617 Ultra/133 controller", 169 pdcsata_chip_map, 170 }, 171 { PCI_PRODUCT_PROMISE_PDC20618, 172 0, 173 "Promise PDC20618 Ultra/133 controller", 174 pdcsata_chip_map, 175 }, 176 { PCI_PRODUCT_PROMISE_PDC20619, 177 0, 178 "Promise PDC20619 Ultra/133 controller", 179 pdcsata_chip_map, 180 }, 181 { PCI_PRODUCT_PROMISE_PDC20620, 182 0, 183 "Promise PDC20620 Ultra/133 controller", 184 pdcsata_chip_map, 185 }, 186 { PCI_PRODUCT_PROMISE_PDC20621, 187 0, 188 "Promise PDC20621 Ultra/133 controller", 189 pdcsata_chip_map, 190 }, 191 { 0, 192 0, 193 NULL, 194 NULL 195 } 196 }; 197 198 static int 199 pdcsata_match(device_t parent, cfdata_t match, void *aux) 200 { 201 struct pci_attach_args *pa = aux; 202 203 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 204 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 205 return (2); 206 } 207 return (0); 208 } 209 210 static void 211 pdcsata_attach(device_t parent, device_t self, void *aux) 212 { 213 struct pci_attach_args *pa = aux; 214 struct pciide_softc *sc = device_private(self); 215 216 sc->sc_wdcdev.sc_atac.atac_dev = self; 217 218 pciide_common_attach(sc, pa, 219 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 220 } 221 222 static void 223 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 224 { 225 struct pciide_channel *cp; 226 struct ata_channel *wdc_cp; 227 struct wdc_regs *wdr; 228 int channel, i; 229 pci_intr_handle_t intrhandle; 230 const char *intrstr; 231 232 /* 233 * Promise SATA controllers have 3 or 4 channels, 234 * the usual IDE registers are mapped in I/O space, with offsets. 235 */ 236 if (pci_intr_map(pa, &intrhandle) != 0) { 237 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 238 "couldn't map interrupt\n"); 239 return; 240 } 241 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 242 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 243 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 244 245 if (sc->sc_pci_ih == NULL) { 246 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 247 "couldn't establish native-PCI interrupt"); 248 if (intrstr != NULL) 249 aprint_error(" at %s", intrstr); 250 aprint_error("\n"); 251 return; 252 } 253 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 254 "interrupting at %s\n", 255 intrstr ? intrstr : "unknown interrupt"); 256 257 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 258 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 259 &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios) == 0); 260 if (!sc->sc_dma_ok) { 261 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 262 "couldn't map bus-master DMA registers\n"); 263 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 264 return; 265 } 266 267 sc->sc_dmat = pa->pa_dmat; 268 269 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 270 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 271 &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 272 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 273 "couldn't map IDE registers\n"); 274 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios); 275 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 276 return; 277 } 278 279 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 280 "bus-master DMA support present\n"); 281 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 282 if (sc->sc_dma_ok) { 283 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 284 } 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 287 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 288 sc->sc_wdcdev.irqack = pdc203xx_irqack; 289 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 290 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 291 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 292 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 293 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 294 295 sc->sc_wdcdev.reset = pdcsata_do_reset; 296 297 switch (sc->sc_pp->ide_product) { 298 case PCI_PRODUCT_PROMISE_PDC20318: 299 case PCI_PRODUCT_PROMISE_PDC20319: 300 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 301 0x00ff0033); 302 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 303 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_SATA_NCHANNELS; 304 break; 305 case PCI_PRODUCT_PROMISE_PDC20371: 306 case PCI_PRODUCT_PROMISE_PDC20375: 307 case PCI_PRODUCT_PROMISE_PDC20376: 308 case PCI_PRODUCT_PROMISE_PDC20377: 309 case PCI_PRODUCT_PROMISE_PDC20378: 310 case PCI_PRODUCT_PROMISE_PDC20379: 311 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 312 0x00ff0033); 313 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 314 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_COMBO_NCHANNELS; 315 break; 316 317 case PCI_PRODUCT_PROMISE_PDC40518: 318 case PCI_PRODUCT_PROMISE_PDC40519: 319 case PCI_PRODUCT_PROMISE_PDC40718: 320 case PCI_PRODUCT_PROMISE_PDC40719: 321 case PCI_PRODUCT_PROMISE_PDC40779: 322 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 323 0x00ff00ff); 324 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_SATA_NCHANNELS; 325 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 326 break; 327 328 case PCI_PRODUCT_PROMISE_PDC20571: 329 case PCI_PRODUCT_PROMISE_PDC20575: 330 case PCI_PRODUCT_PROMISE_PDC20579: 331 case PCI_PRODUCT_PROMISE_PDC20771: 332 case PCI_PRODUCT_PROMISE_PDC20775: 333 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 334 0x00ff00ff); 335 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_COMBO_NCHANNELS; 336 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 337 break; 338 339 case PCI_PRODUCT_PROMISE_PDC20617: 340 case PCI_PRODUCT_PROMISE_PDC20618: 341 case PCI_PRODUCT_PROMISE_PDC20619: 342 case PCI_PRODUCT_PROMISE_PDC20620: 343 case PCI_PRODUCT_PROMISE_PDC20621: 344 sc->sc_wdcdev.sc_atac.atac_nchannels = 345 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 346 0x48) & 0x01) ? 1 : 0) + 347 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 348 0x48) & 0x02) ? 1 : 0) + 349 2; 350 sc->sc_wdcdev.sc_atac.atac_probe = wdc_drvprobe; 351 352 default: 353 aprint_error("unknown promise product 0x%x\n", 354 sc->sc_pp->ide_product); 355 } 356 357 wdc_allocate_regs(&sc->sc_wdcdev); 358 359 sc->sc_wdcdev.dma_arg = sc; 360 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 361 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 362 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 363 364 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 365 channel++) { 366 cp = &sc->pciide_channels[channel]; 367 sc->wdc_chanarray[channel] = &cp->ata_channel; 368 369 cp->ih = sc->sc_pci_ih; 370 cp->name = NULL; 371 cp->ata_channel.ch_channel = channel; 372 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 373 cp->ata_channel.ch_queue = 374 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 375 cp->ata_channel.ch_ndrive = 2; 376 if (cp->ata_channel.ch_queue == NULL) { 377 aprint_error("%s channel %d: " 378 "can't allocate memory for command queue\n", 379 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 380 channel); 381 goto next_channel; 382 } 383 wdc_cp = &cp->ata_channel; 384 wdr = CHAN_TO_WDC_REGS(wdc_cp); 385 386 wdr->ctl_iot = sc->sc_ba5_st; 387 wdr->cmd_iot = sc->sc_ba5_st; 388 389 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 390 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 391 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 392 "couldn't map channel %d ctl regs\n", channel); 393 goto next_channel; 394 } 395 for (i = 0; i < WDC_NREG; i++) { 396 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 397 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 398 &wdr->cmd_iohs[i]) != 0) { 399 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 400 "couldn't map channel %d cmd regs\n", 401 channel); 402 goto next_channel; 403 } 404 } 405 wdc_init_shadow_regs(wdc_cp); 406 407 /* 408 * subregion de busmaster registers. They're spread all over 409 * the controller's register space :(. They are also 4 bytes 410 * sized, with some specific extentions in the extra bits. 411 * It also seems that the IDEDMA_CTL register isn't available. 412 */ 413 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 414 0x260 + (channel << 7), 1, 415 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 416 aprint_normal("%s channel %d: can't subregion DMA " 417 "registers\n", 418 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 419 channel); 420 goto next_channel; 421 } 422 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 423 0x244 + (channel << 7), 4, 424 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 425 aprint_normal("%s channel %d: can't subregion DMA " 426 "registers\n", 427 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 428 channel); 429 goto next_channel; 430 } 431 432 /* subregion the SATA registers */ 433 if (sc->sc_wdcdev.sc_atac.atac_probe == wdc_sataprobe || 434 (sc->sc_wdcdev.sc_atac.atac_probe == pdc203xx_combo_probe 435 && channel < 2)) { 436 wdr->sata_iot = sc->sc_ba5_st; 437 wdr->sata_baseioh = sc->sc_ba5_sh; 438 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 439 PDC205_SSTATUS(channel), 1, 440 &wdr->sata_status) != 0) { 441 aprint_error_dev( 442 sc->sc_wdcdev.sc_atac.atac_dev, 443 "couldn't map channel %d " 444 "sata_status regs\n", channel); 445 goto next_channel; 446 } 447 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 448 PDC205_SERROR(channel), 1, &wdr->sata_error) != 0) { 449 aprint_error_dev( 450 sc->sc_wdcdev.sc_atac.atac_dev, 451 "couldn't map channel %d " 452 "sata_error regs\n", channel); 453 goto next_channel; 454 } 455 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 456 PDC205_SCONTROL(channel), 1, 457 &wdr->sata_control) != 0) { 458 aprint_error_dev( 459 sc->sc_wdcdev.sc_atac.atac_dev, 460 "couldn't map channel %d " 461 "sata_control regs\n", channel); 462 goto next_channel; 463 } 464 } 465 466 wdcattach(wdc_cp); 467 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 468 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 469 0) & ~0x00003f9f) | (channel + 1)); 470 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 471 (channel + 1) << 2, 0x00000001); 472 next_channel: 473 continue; 474 } 475 return; 476 } 477 478 static void 479 pdc203xx_combo_probe(struct ata_channel *chp) 480 { 481 if (chp->ch_channel < 2) 482 wdc_sataprobe(chp); 483 else 484 wdc_drvprobe(chp); 485 } 486 487 static void 488 pdc203xx_setup_channel(struct ata_channel *chp) 489 { 490 struct ata_drive_datas *drvp; 491 int drive, s; 492 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 493 494 pciide_channel_dma_setup(cp); 495 496 for (drive = 0; drive < 2; drive++) { 497 drvp = &chp->ch_drive[drive]; 498 if ((drvp->drive_flags & DRIVE) == 0) 499 continue; 500 if (drvp->drive_flags & DRIVE_UDMA) { 501 s = splbio(); 502 drvp->drive_flags &= ~DRIVE_DMA; 503 splx(s); 504 } 505 } 506 } 507 508 static int 509 pdcsata_pci_intr(void *arg) 510 { 511 struct pciide_softc *sc = arg; 512 struct pciide_channel *cp; 513 struct ata_channel *wdc_cp; 514 int i, rv, crv; 515 u_int32_t scr, status, chanbase; 516 517 rv = 0; 518 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 519 if (scr == 0xffffffff) return(rv); 520 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 521 scr = scr & 0x0000ffff; 522 if (!scr) return(rv); 523 524 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 525 cp = &sc->pciide_channels[i]; 526 wdc_cp = &cp->ata_channel; 527 if (scr & (1 << (i + 1))) { 528 chanbase = PDC_CHANNELBASE(i) + 0x48; 529 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 530 if (status & PDC_ERRMASK) { 531 chanbase = PDC_CHANNELBASE(i) + 0x60; 532 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 533 status |= 0x800; 534 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 535 status &= ~0x800; 536 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 537 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 538 continue; 539 } 540 crv = wdcintr(wdc_cp); 541 if (crv == 0) { 542 aprint_error("%s:%d: bogus intr (reg 0x%x)\n", 543 device_xname( 544 sc->sc_wdcdev.sc_atac.atac_dev), i, scr); 545 } else 546 rv = 1; 547 } 548 } 549 return rv; 550 } 551 552 static void 553 pdc203xx_irqack(struct ata_channel *chp) 554 { 555 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 556 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 557 558 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 559 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 560 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 561 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 562 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 563 } 564 565 static int 566 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 567 size_t datalen, int flags) 568 { 569 struct pciide_softc *sc = v; 570 571 return pciide_dma_dmamap_setup(sc, channel, drive, 572 databuf, datalen, flags); 573 } 574 575 static void 576 pdc203xx_dma_start(void *v, int channel, int drive) 577 { 578 struct pciide_softc *sc = v; 579 struct pciide_channel *cp = &sc->pciide_channels[channel]; 580 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 581 582 /* Write table addr */ 583 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 584 dma_maps->dmamap_table->dm_segs[0].ds_addr); 585 /* start DMA engine */ 586 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 587 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 588 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 589 } 590 591 static int 592 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 593 { 594 struct pciide_softc *sc = v; 595 struct pciide_channel *cp = &sc->pciide_channels[channel]; 596 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 597 598 /* stop DMA channel */ 599 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 600 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 601 0) & ~0x80)); 602 603 /* Unload the map of the data buffer */ 604 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 605 dma_maps->dmamap_xfer->dm_mapsize, 606 (dma_maps->dma_flags & WDC_DMA_READ) ? 607 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 608 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 609 610 return 0; 611 } 612 613 614 static void 615 pdcsata_do_reset(struct ata_channel *chp, int poll) 616 { 617 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 618 int reset, status, i, chanbase; 619 620 /* reset SATA */ 621 reset = (1 << 11); 622 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 623 for (i = 0; i < 11;i ++) { 624 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 625 if (status & reset) break; 626 delay(100); 627 status |= reset; 628 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 629 } 630 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 631 status &= ~reset; 632 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 633 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 634 635 wdc_do_reset(chp, poll); 636 } 637
Indexes created Tue Sep 30 07:10:03 GMT 2025