pdcsata.c revision 1.2
1 /* $NetBSD: pdcsata.c,v 1.2 2004/11/28 14:34:31 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/malloc.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pciidereg.h> 40 #include <dev/pci/pciidevar.h> 41 42 #define PDC203xx_NCHANNELS 4 43 44 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 45 46 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void pdc203xx_setup_channel(struct ata_channel *); 48 static int pdc203xx_pci_intr(void *); 49 static void pdc203xx_irqack(struct ata_channel *); 50 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 51 static void pdc203xx_dma_start(void *,int ,int); 52 static int pdc203xx_dma_finish(void *, int, int, int); 53 54 static int pdcsata_match(struct device *, struct cfdata *, void *); 55 static void pdcsata_attach(struct device *, struct device *, void *); 56 57 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 58 pdcsata_match, pdcsata_attach, NULL, NULL); 59 60 static const struct pciide_product_desc pciide_pdcsata_products[] = { 61 { PCI_PRODUCT_PROMISE_PDC20318, 62 0, 63 "Promise PDC20318 SATA150 controller", 64 pdcsata_chip_map, 65 }, 66 { PCI_PRODUCT_PROMISE_PDC20319, 67 0, 68 "Promise PDC20319 SATA150 controller", 69 pdcsata_chip_map, 70 }, 71 { PCI_PRODUCT_PROMISE_PDC20371, 72 0, 73 "Promise PDC20371 SATA150 controller", 74 pdcsata_chip_map, 75 }, 76 { PCI_PRODUCT_PROMISE_PDC20375, 77 0, 78 "Promise PDC20375 SATA150 controller", 79 pdcsata_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_PDC20376, 82 0, 83 "Promise PDC20376 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20377, 87 0, 88 "Promise PDC20377 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20378, 92 0, 93 "Promise PDC20378 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20379, 97 0, 98 "Promise PDC20379 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { 0, 102 0, 103 NULL, 104 NULL 105 } 106 }; 107 108 static int 109 pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 110 { 111 struct pci_attach_args *pa = aux; 112 113 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 114 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 115 return (2); 116 } 117 return (0); 118 } 119 120 static void 121 pdcsata_attach(struct device *parent, struct device *self, void *aux) 122 { 123 struct pci_attach_args *pa = aux; 124 struct pciide_softc *sc = (struct pciide_softc *)self; 125 126 pciide_common_attach(sc, pa, 127 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 128 } 129 130 static void 131 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 132 { 133 struct pciide_channel *cp; 134 struct ata_channel *wdc_cp; 135 struct wdc_regs *wdr; 136 int channel, i; 137 bus_size_t dmasize; 138 pci_intr_handle_t intrhandle; 139 const char *intrstr; 140 141 /* 142 * Promise SATA controllers have 3 or 4 channels, 143 * the usual IDE registers are mapped in I/O space, with offsets. 144 */ 145 if (pci_intr_map(pa, &intrhandle) != 0) { 146 aprint_error("%s: couldn't map interrupt\n", 147 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 148 return; 149 } 150 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 151 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 152 intrhandle, IPL_BIO, pdc203xx_pci_intr, sc); 153 if (sc->sc_pci_ih == NULL) { 154 aprint_error("%s: couldn't establish native-PCI interrupt", 155 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 156 if (intrstr != NULL) 157 aprint_normal(" at %s", intrstr); 158 aprint_normal("\n"); 159 return; 160 } 161 aprint_normal("%s: interrupting at %s\n", 162 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 163 intrstr ? intrstr : "unknown interrupt"); 164 165 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 166 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 167 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 168 if (!sc->sc_dma_ok) { 169 aprint_error("%s: couldn't map bus-master DMA registers\n", 170 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 171 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 172 return; 173 } 174 175 sc->sc_dmat = pa->pa_dmat; 176 177 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 178 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 179 &sc->sc_ba5_sh, NULL, NULL) != 0) { 180 aprint_error("%s: couldn't map IDE registers\n", 181 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 182 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 183 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 184 return; 185 } 186 187 aprint_normal("%s: bus-master DMA support present\n", 188 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 189 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 190 if (sc->sc_dma_ok) { 191 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 192 } 193 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 194 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 195 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 196 sc->sc_wdcdev.irqack = pdc203xx_irqack; 197 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 198 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 199 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 200 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 201 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 202 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x06c, 0x00ff0033); 203 sc->sc_wdcdev.sc_atac.atac_nchannels = 204 (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 205 PDC203xx_NCHANNELS : 3; 206 wdc_allocate_regs(&sc->sc_wdcdev); 207 208 sc->sc_wdcdev.dma_arg = sc; 209 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 210 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 211 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 212 213 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 214 channel++) { 215 cp = &sc->pciide_channels[channel]; 216 sc->wdc_chanarray[channel] = &cp->ata_channel; 217 218 cp->ih = sc->sc_pci_ih; 219 cp->name = NULL; 220 cp->ata_channel.ch_channel = channel; 221 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 222 cp->ata_channel.ch_queue = 223 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 224 if (cp->ata_channel.ch_queue == NULL) { 225 aprint_error("%s channel %d: " 226 "can't allocate memory for command queue\n", 227 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 228 goto next_channel; 229 } 230 wdc_cp = &cp->ata_channel; 231 wdr = CHAN_TO_WDC_REGS(wdc_cp); 232 233 wdr->ctl_iot = sc->sc_ba5_st; 234 wdr->cmd_iot = sc->sc_ba5_st; 235 236 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 237 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 238 aprint_error("%s: couldn't map channel %d ctl regs\n", 239 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 240 channel); 241 goto next_channel; 242 } 243 for (i = 0; i < WDC_NREG; i++) { 244 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 245 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 246 &wdr->cmd_iohs[i]) != 0) { 247 aprint_error("%s: couldn't map channel %d cmd " 248 "regs\n", 249 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 250 channel); 251 goto next_channel; 252 } 253 } 254 wdc_init_shadow_regs(wdc_cp); 255 256 /* 257 * subregion de busmaster registers. They're spread all over 258 * the controller's register space :(. They are also 4 bytes 259 * sized, with some specific extentions in the extra bits. 260 * It also seems that the IDEDMA_CTL register isn't available. 261 */ 262 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 263 0x260 + (channel << 7), 1, 264 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 265 aprint_normal("%s channel %d: can't subregion DMA " 266 "registers\n", 267 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 268 goto next_channel; 269 } 270 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 271 0x244 + (channel << 7), 4, 272 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 273 aprint_normal("%s channel %d: can't subregion DMA " 274 "registers\n", 275 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 276 goto next_channel; 277 } 278 279 wdcattach(wdc_cp); 280 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 281 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 282 0) & ~0x00003f9f) | (channel + 1)); 283 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 284 (channel + 1) << 2, 0x00000001); 285 next_channel: 286 continue; 287 } 288 return; 289 } 290 291 static void 292 pdc203xx_setup_channel(struct ata_channel *chp) 293 { 294 struct ata_drive_datas *drvp; 295 int drive, s; 296 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 297 298 pciide_channel_dma_setup(cp); 299 300 for (drive = 0; drive < 2; drive++) { 301 drvp = &chp->ch_drive[drive]; 302 if ((drvp->drive_flags & DRIVE) == 0) 303 continue; 304 if (drvp->drive_flags & DRIVE_UDMA) { 305 s = splbio(); 306 drvp->drive_flags &= ~DRIVE_DMA; 307 splx(s); 308 } 309 } 310 } 311 312 static int 313 pdc203xx_pci_intr(void *arg) 314 { 315 struct pciide_softc *sc = arg; 316 struct pciide_channel *cp; 317 struct ata_channel *wdc_cp; 318 int i, rv, crv; 319 u_int32_t scr; 320 321 rv = 0; 322 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x00040); 323 324 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 325 cp = &sc->pciide_channels[i]; 326 wdc_cp = &cp->ata_channel; 327 if (scr & (1 << (i + 1))) { 328 crv = wdcintr(wdc_cp); 329 if (crv == 0) { 330 printf("%s:%d: bogus intr (reg 0x%x)\n", 331 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 332 i, scr); 333 } else 334 rv = 1; 335 } 336 } 337 return rv; 338 } 339 340 static void 341 pdc203xx_irqack(struct ata_channel *chp) 342 { 343 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 344 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 345 346 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 347 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 348 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 349 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 350 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 351 } 352 353 static int 354 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 355 size_t datalen, int flags) 356 { 357 struct pciide_softc *sc = v; 358 359 return pciide_dma_dmamap_setup(sc, channel, drive, 360 databuf, datalen, flags); 361 } 362 363 static void 364 pdc203xx_dma_start(void *v, int channel, int drive) 365 { 366 struct pciide_softc *sc = v; 367 struct pciide_channel *cp = &sc->pciide_channels[channel]; 368 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 369 370 /* Write table addr */ 371 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 372 dma_maps->dmamap_table->dm_segs[0].ds_addr); 373 /* start DMA engine */ 374 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 375 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 376 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 377 } 378 379 static int 380 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 381 { 382 struct pciide_softc *sc = v; 383 struct pciide_channel *cp = &sc->pciide_channels[channel]; 384 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 385 386 /* stop DMA channel */ 387 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 388 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 389 0) & ~0x80)); 390 391 /* Unload the map of the data buffer */ 392 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 393 dma_maps->dmamap_xfer->dm_mapsize, 394 (dma_maps->dma_flags & WDC_DMA_READ) ? 395 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 396 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 397 398 return 0; 399 } 400
Indexes created Mon Sep 29 21:09:56 GMT 2025