pdcsata.c revision 1.25
1 /* $NetBSD: pdcsata.c,v 1.25 2012/07/31 15:50:36 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.25 2012/07/31 15:50:36 bouyer Exp $"); 29 30 #include <sys/types.h> 31 #include <sys/malloc.h> 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/ata/atareg.h> 40 #include <dev/ata/satavar.h> 41 #include <dev/ata/satareg.h> 42 43 #define PDC203xx_SATA_NCHANNELS 4 44 #define PDC203xx_COMBO_NCHANNELS 3 45 #define PDC40718_SATA_NCHANNELS 4 46 #define PDC20575_COMBO_NCHANNELS 3 47 48 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 49 50 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 51 #define PDC_ERRMASK 0x00780700 52 53 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 54 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 55 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 56 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 57 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 58 59 static void pdcsata_chip_map(struct pciide_softc *, 60 const struct pci_attach_args *); 61 static void pdc203xx_setup_channel(struct ata_channel *); 62 static void pdc203xx_irqack(struct ata_channel *); 63 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 64 static void pdc203xx_dma_start(void *,int ,int); 65 static int pdc203xx_dma_finish(void *, int, int, int); 66 static void pdc203xx_combo_probe(struct ata_channel *); 67 static int pdcsata_pci_intr(void *); 68 static void pdcsata_do_reset(struct ata_channel *, int); 69 70 static int pdcsata_match(device_t, cfdata_t, void *); 71 static void pdcsata_attach(device_t, device_t, void *); 72 73 CFATTACH_DECL_NEW(pdcsata, sizeof(struct pciide_softc), 74 pdcsata_match, pdcsata_attach, NULL, NULL); 75 76 static const struct pciide_product_desc pciide_pdcsata_products[] = { 77 { PCI_PRODUCT_PROMISE_PDC20318, 78 0, 79 "Promise PDC20318 SATA150 controller", 80 pdcsata_chip_map, 81 }, 82 { PCI_PRODUCT_PROMISE_PDC20319, 83 0, 84 "Promise PDC20319 SATA150 controller", 85 pdcsata_chip_map, 86 }, 87 { PCI_PRODUCT_PROMISE_PDC20371, 88 0, 89 "Promise PDC20371 SATA150 controller", 90 pdcsata_chip_map, 91 }, 92 { PCI_PRODUCT_PROMISE_PDC20375, 93 0, 94 "Promise PDC20375 SATA150 controller", 95 pdcsata_chip_map, 96 }, 97 { PCI_PRODUCT_PROMISE_PDC20376, 98 0, 99 "Promise PDC20376 SATA150 controller", 100 pdcsata_chip_map, 101 }, 102 { PCI_PRODUCT_PROMISE_PDC20377, 103 0, 104 "Promise PDC20377 SATA150 controller", 105 pdcsata_chip_map, 106 }, 107 { PCI_PRODUCT_PROMISE_PDC20378, 108 0, 109 "Promise PDC20378 SATA150 controller", 110 pdcsata_chip_map, 111 }, 112 { PCI_PRODUCT_PROMISE_PDC20379, 113 0, 114 "Promise PDC20379 SATA150 controller", 115 pdcsata_chip_map, 116 }, 117 { PCI_PRODUCT_PROMISE_PDC40518, 118 0, 119 "Promise PDC40518 SATA150 controller", 120 pdcsata_chip_map, 121 }, 122 { PCI_PRODUCT_PROMISE_PDC40519, 123 0, 124 "Promise PDC40519 SATA 150 controller", 125 pdcsata_chip_map, 126 }, 127 { PCI_PRODUCT_PROMISE_PDC40718, 128 0, 129 "Promise PDC40718 SATA300 controller", 130 pdcsata_chip_map, 131 }, 132 { PCI_PRODUCT_PROMISE_PDC40719, 133 0, 134 "Promise PDC40719 SATA300 controller", 135 pdcsata_chip_map, 136 }, 137 { PCI_PRODUCT_PROMISE_PDC40779, 138 0, 139 "Promise PDC40779 SATA300 controller", 140 pdcsata_chip_map, 141 }, 142 { PCI_PRODUCT_PROMISE_PDC20571, 143 0, 144 "Promise PDC20571 SATA150 controller", 145 pdcsata_chip_map, 146 }, 147 { PCI_PRODUCT_PROMISE_PDC20575, 148 0, 149 "Promise PDC20575 SATA150 controller", 150 pdcsata_chip_map, 151 }, 152 { PCI_PRODUCT_PROMISE_PDC20579, 153 0, 154 "Promise PDC20579 SATA150 controller", 155 pdcsata_chip_map, 156 }, 157 { PCI_PRODUCT_PROMISE_PDC20771, 158 0, 159 "Promise PDC20771 SATA300 controller", 160 pdcsata_chip_map, 161 }, 162 { PCI_PRODUCT_PROMISE_PDC20775, 163 0, 164 "Promise PDC20775 SATA300 controller", 165 pdcsata_chip_map, 166 }, 167 { PCI_PRODUCT_PROMISE_PDC20617, 168 0, 169 "Promise PDC2020617 Ultra/133 controller", 170 pdcsata_chip_map, 171 }, 172 { PCI_PRODUCT_PROMISE_PDC20618, 173 0, 174 "Promise PDC20618 Ultra/133 controller", 175 pdcsata_chip_map, 176 }, 177 { PCI_PRODUCT_PROMISE_PDC20619, 178 0, 179 "Promise PDC20619 Ultra/133 controller", 180 pdcsata_chip_map, 181 }, 182 { PCI_PRODUCT_PROMISE_PDC20620, 183 0, 184 "Promise PDC20620 Ultra/133 controller", 185 pdcsata_chip_map, 186 }, 187 { PCI_PRODUCT_PROMISE_PDC20621, 188 0, 189 "Promise PDC20621 Ultra/133 controller", 190 pdcsata_chip_map, 191 }, 192 { 0, 193 0, 194 NULL, 195 NULL 196 } 197 }; 198 199 static int 200 pdcsata_match(device_t parent, cfdata_t match, void *aux) 201 { 202 struct pci_attach_args *pa = aux; 203 204 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 205 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 206 return (2); 207 } 208 return (0); 209 } 210 211 static void 212 pdcsata_attach(device_t parent, device_t self, void *aux) 213 { 214 struct pci_attach_args *pa = aux; 215 struct pciide_softc *sc = device_private(self); 216 217 sc->sc_wdcdev.sc_atac.atac_dev = self; 218 219 pciide_common_attach(sc, pa, 220 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 221 } 222 223 static void 224 pdcsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 225 { 226 struct pciide_channel *cp; 227 struct ata_channel *wdc_cp; 228 struct wdc_regs *wdr; 229 int channel, i; 230 pci_intr_handle_t intrhandle; 231 const char *intrstr; 232 233 /* 234 * Promise SATA controllers have 3 or 4 channels, 235 * the usual IDE registers are mapped in I/O space, with offsets. 236 */ 237 if (pci_intr_map(pa, &intrhandle) != 0) { 238 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 239 "couldn't map interrupt\n"); 240 return; 241 } 242 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 243 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 244 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 245 246 if (sc->sc_pci_ih == NULL) { 247 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 248 "couldn't establish native-PCI interrupt"); 249 if (intrstr != NULL) 250 aprint_error(" at %s", intrstr); 251 aprint_error("\n"); 252 return; 253 } 254 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 255 "interrupting at %s\n", 256 intrstr ? intrstr : "unknown interrupt"); 257 258 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 259 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 260 &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios) == 0); 261 if (!sc->sc_dma_ok) { 262 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 263 "couldn't map bus-master DMA registers\n"); 264 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 265 return; 266 } 267 268 sc->sc_dmat = pa->pa_dmat; 269 270 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 271 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 272 &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 273 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 274 "couldn't map IDE registers\n"); 275 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios); 276 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 277 return; 278 } 279 280 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 281 "bus-master DMA support present\n"); 282 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 283 if (sc->sc_dma_ok) { 284 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 285 } 286 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 287 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 288 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 289 sc->sc_wdcdev.irqack = pdc203xx_irqack; 290 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 291 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 292 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 293 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 294 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 295 sc->sc_wdcdev.wdc_maxdrives = 2; 296 297 sc->sc_wdcdev.reset = pdcsata_do_reset; 298 299 switch (sc->sc_pp->ide_product) { 300 case PCI_PRODUCT_PROMISE_PDC20318: 301 case PCI_PRODUCT_PROMISE_PDC20319: 302 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 303 0x00ff0033); 304 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 305 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_SATA_NCHANNELS; 306 sc->sc_wdcdev.wdc_maxdrives = 1; 307 break; 308 case PCI_PRODUCT_PROMISE_PDC20371: 309 case PCI_PRODUCT_PROMISE_PDC20375: 310 case PCI_PRODUCT_PROMISE_PDC20376: 311 case PCI_PRODUCT_PROMISE_PDC20377: 312 case PCI_PRODUCT_PROMISE_PDC20378: 313 case PCI_PRODUCT_PROMISE_PDC20379: 314 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 315 0x00ff0033); 316 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 317 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_COMBO_NCHANNELS; 318 break; 319 320 case PCI_PRODUCT_PROMISE_PDC40518: 321 case PCI_PRODUCT_PROMISE_PDC40519: 322 case PCI_PRODUCT_PROMISE_PDC40718: 323 case PCI_PRODUCT_PROMISE_PDC40719: 324 case PCI_PRODUCT_PROMISE_PDC40779: 325 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 326 0x00ff00ff); 327 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_SATA_NCHANNELS; 328 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 329 sc->sc_wdcdev.wdc_maxdrives = 1; 330 break; 331 332 case PCI_PRODUCT_PROMISE_PDC20571: 333 case PCI_PRODUCT_PROMISE_PDC20575: 334 case PCI_PRODUCT_PROMISE_PDC20579: 335 case PCI_PRODUCT_PROMISE_PDC20771: 336 case PCI_PRODUCT_PROMISE_PDC20775: 337 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 338 0x00ff00ff); 339 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_COMBO_NCHANNELS; 340 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 341 break; 342 343 case PCI_PRODUCT_PROMISE_PDC20617: 344 case PCI_PRODUCT_PROMISE_PDC20618: 345 case PCI_PRODUCT_PROMISE_PDC20619: 346 case PCI_PRODUCT_PROMISE_PDC20620: 347 case PCI_PRODUCT_PROMISE_PDC20621: 348 sc->sc_wdcdev.sc_atac.atac_nchannels = 349 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 350 0x48) & 0x01) ? 1 : 0) + 351 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 352 0x48) & 0x02) ? 1 : 0) + 353 2; 354 sc->sc_wdcdev.sc_atac.atac_probe = wdc_drvprobe; 355 356 default: 357 aprint_error("unknown promise product 0x%x\n", 358 sc->sc_pp->ide_product); 359 } 360 361 wdc_allocate_regs(&sc->sc_wdcdev); 362 363 sc->sc_wdcdev.dma_arg = sc; 364 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 365 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 366 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 367 368 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 369 channel++) { 370 cp = &sc->pciide_channels[channel]; 371 sc->wdc_chanarray[channel] = &cp->ata_channel; 372 373 cp->ih = sc->sc_pci_ih; 374 cp->name = NULL; 375 cp->ata_channel.ch_channel = channel; 376 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 377 cp->ata_channel.ch_queue = 378 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 379 if (cp->ata_channel.ch_queue == NULL) { 380 aprint_error("%s channel %d: " 381 "can't allocate memory for command queue\n", 382 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 383 channel); 384 goto next_channel; 385 } 386 wdc_cp = &cp->ata_channel; 387 wdr = CHAN_TO_WDC_REGS(wdc_cp); 388 389 wdr->ctl_iot = sc->sc_ba5_st; 390 wdr->cmd_iot = sc->sc_ba5_st; 391 392 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 393 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 394 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 395 "couldn't map channel %d ctl regs\n", channel); 396 goto next_channel; 397 } 398 for (i = 0; i < WDC_NREG; i++) { 399 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 400 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 401 &wdr->cmd_iohs[i]) != 0) { 402 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 403 "couldn't map channel %d cmd regs\n", 404 channel); 405 goto next_channel; 406 } 407 } 408 wdc_init_shadow_regs(wdc_cp); 409 410 /* 411 * subregion de busmaster registers. They're spread all over 412 * the controller's register space :(. They are also 4 bytes 413 * sized, with some specific extentions in the extra bits. 414 * It also seems that the IDEDMA_CTL register isn't available. 415 */ 416 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 417 0x260 + (channel << 7), 1, 418 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 419 aprint_normal("%s channel %d: can't subregion DMA " 420 "registers\n", 421 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 422 channel); 423 goto next_channel; 424 } 425 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 426 0x244 + (channel << 7), 4, 427 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 428 aprint_normal("%s channel %d: can't subregion DMA " 429 "registers\n", 430 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 431 channel); 432 goto next_channel; 433 } 434 435 /* subregion the SATA registers */ 436 if (sc->sc_wdcdev.sc_atac.atac_probe == wdc_sataprobe || 437 (sc->sc_wdcdev.sc_atac.atac_probe == pdc203xx_combo_probe 438 && channel < 2)) { 439 wdr->sata_iot = sc->sc_ba5_st; 440 wdr->sata_baseioh = sc->sc_ba5_sh; 441 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 442 PDC205_SSTATUS(channel), 1, 443 &wdr->sata_status) != 0) { 444 aprint_error_dev( 445 sc->sc_wdcdev.sc_atac.atac_dev, 446 "couldn't map channel %d " 447 "sata_status regs\n", channel); 448 goto next_channel; 449 } 450 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 451 PDC205_SERROR(channel), 1, &wdr->sata_error) != 0) { 452 aprint_error_dev( 453 sc->sc_wdcdev.sc_atac.atac_dev, 454 "couldn't map channel %d " 455 "sata_error regs\n", channel); 456 goto next_channel; 457 } 458 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 459 PDC205_SCONTROL(channel), 1, 460 &wdr->sata_control) != 0) { 461 aprint_error_dev( 462 sc->sc_wdcdev.sc_atac.atac_dev, 463 "couldn't map channel %d " 464 "sata_control regs\n", channel); 465 goto next_channel; 466 } 467 } 468 469 wdcattach(wdc_cp); 470 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 471 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 472 0) & ~0x00003f9f) | (channel + 1)); 473 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 474 (channel + 1) << 2, 0x00000001); 475 next_channel: 476 continue; 477 } 478 return; 479 } 480 481 static void 482 pdc203xx_combo_probe(struct ata_channel *chp) 483 { 484 if (chp->ch_channel < 2) 485 wdc_sataprobe(chp); 486 else 487 wdc_drvprobe(chp); 488 } 489 490 static void 491 pdc203xx_setup_channel(struct ata_channel *chp) 492 { 493 struct ata_drive_datas *drvp; 494 int drive, s; 495 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 496 497 pciide_channel_dma_setup(cp); 498 499 for (drive = 0; drive < 2; drive++) { 500 drvp = &chp->ch_drive[drive]; 501 if (drvp->drive_type == ATA_DRIVET_NONE) 502 continue; 503 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 504 s = splbio(); 505 drvp->drive_flags &= ~ATA_DRIVE_DMA; 506 splx(s); 507 } 508 } 509 } 510 511 static int 512 pdcsata_pci_intr(void *arg) 513 { 514 struct pciide_softc *sc = arg; 515 struct pciide_channel *cp; 516 struct ata_channel *wdc_cp; 517 int i, rv, crv; 518 u_int32_t scr, status, chanbase; 519 520 rv = 0; 521 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 522 if (scr == 0xffffffff) return(rv); 523 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 524 scr = scr & 0x0000ffff; 525 if (!scr) return(rv); 526 527 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 528 cp = &sc->pciide_channels[i]; 529 wdc_cp = &cp->ata_channel; 530 if (scr & (1 << (i + 1))) { 531 chanbase = PDC_CHANNELBASE(i) + 0x48; 532 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 533 if (status & PDC_ERRMASK) { 534 chanbase = PDC_CHANNELBASE(i) + 0x60; 535 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 536 status |= 0x800; 537 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 538 status &= ~0x800; 539 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 540 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 541 continue; 542 } 543 crv = wdcintr(wdc_cp); 544 if (crv == 0) { 545 aprint_error("%s:%d: bogus intr (reg 0x%x)\n", 546 device_xname( 547 sc->sc_wdcdev.sc_atac.atac_dev), i, scr); 548 } else 549 rv = 1; 550 } 551 } 552 return rv; 553 } 554 555 static void 556 pdc203xx_irqack(struct ata_channel *chp) 557 { 558 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 559 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 560 561 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 562 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 563 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 564 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 565 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 566 } 567 568 static int 569 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 570 size_t datalen, int flags) 571 { 572 struct pciide_softc *sc = v; 573 574 return pciide_dma_dmamap_setup(sc, channel, drive, 575 databuf, datalen, flags); 576 } 577 578 static void 579 pdc203xx_dma_start(void *v, int channel, int drive) 580 { 581 struct pciide_softc *sc = v; 582 struct pciide_channel *cp = &sc->pciide_channels[channel]; 583 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 584 585 /* Write table addr */ 586 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 587 dma_maps->dmamap_table->dm_segs[0].ds_addr); 588 /* start DMA engine */ 589 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 590 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 591 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 592 } 593 594 static int 595 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 596 { 597 struct pciide_softc *sc = v; 598 struct pciide_channel *cp = &sc->pciide_channels[channel]; 599 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 600 601 /* stop DMA channel */ 602 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 603 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 604 0) & ~0x80)); 605 606 /* Unload the map of the data buffer */ 607 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 608 dma_maps->dmamap_xfer->dm_mapsize, 609 (dma_maps->dma_flags & WDC_DMA_READ) ? 610 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 611 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 612 613 return 0; 614 } 615 616 617 static void 618 pdcsata_do_reset(struct ata_channel *chp, int poll) 619 { 620 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 621 int reset, status, i, chanbase; 622 623 /* reset SATA */ 624 reset = (1 << 11); 625 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 626 for (i = 0; i < 11;i ++) { 627 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 628 if (status & reset) break; 629 delay(100); 630 status |= reset; 631 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 632 } 633 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 634 status &= ~reset; 635 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 636 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 637 638 wdc_do_reset(chp, poll); 639 } 640
Indexes created Tue Sep 30 11:09:46 GMT 2025