pdcsata.c revision 1.25.2.1
1 /* $NetBSD: pdcsata.c,v 1.25.2.1 2012/10/09 13:36:06 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.25.2.1 2012/10/09 13:36:06 bouyer Exp $"); 29 30 #include <sys/types.h> 31 #include <sys/malloc.h> 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/ata/atareg.h> 40 #include <dev/ata/satavar.h> 41 #include <dev/ata/satareg.h> 42 43 #define PDC203xx_SATA_NCHANNELS 4 44 #define PDC203xx_COMBO_NCHANNELS 3 45 #define PDC40718_SATA_NCHANNELS 4 46 #define PDC20575_COMBO_NCHANNELS 3 47 48 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 49 50 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 51 #define PDC_ERRMASK 0x00780700 52 53 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 54 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 55 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 56 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 57 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 58 59 static void pdcsata_chip_map(struct pciide_softc *, 60 const struct pci_attach_args *); 61 static void pdc203xx_setup_channel(struct ata_channel *); 62 static void pdc203xx_irqack(struct ata_channel *); 63 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 64 static void pdc203xx_dma_start(void *,int ,int); 65 static int pdc203xx_dma_finish(void *, int, int, int); 66 static void pdc203xx_combo_probe(struct ata_channel *); 67 static int pdcsata_pci_intr(void *); 68 static void pdcsata_do_reset(struct ata_channel *, int); 69 70 static int pdcsata_match(device_t, cfdata_t, void *); 71 static void pdcsata_attach(device_t, device_t, void *); 72 73 CFATTACH_DECL_NEW(pdcsata, sizeof(struct pciide_softc), 74 pdcsata_match, pdcsata_attach, NULL, NULL); 75 76 static const struct pciide_product_desc pciide_pdcsata_products[] = { 77 { PCI_PRODUCT_PROMISE_PDC20318, 78 0, 79 "Promise PDC20318 SATA150 controller", 80 pdcsata_chip_map, 81 }, 82 { PCI_PRODUCT_PROMISE_PDC20319, 83 0, 84 "Promise PDC20319 SATA150 controller", 85 pdcsata_chip_map, 86 }, 87 { PCI_PRODUCT_PROMISE_PDC20371, 88 0, 89 "Promise PDC20371 SATA150 controller", 90 pdcsata_chip_map, 91 }, 92 { PCI_PRODUCT_PROMISE_PDC20375, 93 0, 94 "Promise PDC20375 SATA150 controller", 95 pdcsata_chip_map, 96 }, 97 { PCI_PRODUCT_PROMISE_PDC20376, 98 0, 99 "Promise PDC20376 SATA150 controller", 100 pdcsata_chip_map, 101 }, 102 { PCI_PRODUCT_PROMISE_PDC20377, 103 0, 104 "Promise PDC20377 SATA150 controller", 105 pdcsata_chip_map, 106 }, 107 { PCI_PRODUCT_PROMISE_PDC20378, 108 0, 109 "Promise PDC20378 SATA150 controller", 110 pdcsata_chip_map, 111 }, 112 { PCI_PRODUCT_PROMISE_PDC20379, 113 0, 114 "Promise PDC20379 SATA150 controller", 115 pdcsata_chip_map, 116 }, 117 { PCI_PRODUCT_PROMISE_PDC40518, 118 0, 119 "Promise PDC40518 SATA150 controller", 120 pdcsata_chip_map, 121 }, 122 { PCI_PRODUCT_PROMISE_PDC40519, 123 0, 124 "Promise PDC40519 SATA 150 controller", 125 pdcsata_chip_map, 126 }, 127 { PCI_PRODUCT_PROMISE_PDC40718, 128 0, 129 "Promise PDC40718 SATA300 controller", 130 pdcsata_chip_map, 131 }, 132 { PCI_PRODUCT_PROMISE_PDC40719, 133 0, 134 "Promise PDC40719 SATA300 controller", 135 pdcsata_chip_map, 136 }, 137 { PCI_PRODUCT_PROMISE_PDC40779, 138 0, 139 "Promise PDC40779 SATA300 controller", 140 pdcsata_chip_map, 141 }, 142 { PCI_PRODUCT_PROMISE_PDC20571, 143 0, 144 "Promise PDC20571 SATA150 controller", 145 pdcsata_chip_map, 146 }, 147 { PCI_PRODUCT_PROMISE_PDC20575, 148 0, 149 "Promise PDC20575 SATA150 controller", 150 pdcsata_chip_map, 151 }, 152 { PCI_PRODUCT_PROMISE_PDC20579, 153 0, 154 "Promise PDC20579 SATA150 controller", 155 pdcsata_chip_map, 156 }, 157 { PCI_PRODUCT_PROMISE_PDC20771, 158 0, 159 "Promise PDC20771 SATA300 controller", 160 pdcsata_chip_map, 161 }, 162 { PCI_PRODUCT_PROMISE_PDC20775, 163 0, 164 "Promise PDC20775 SATA300 controller", 165 pdcsata_chip_map, 166 }, 167 { PCI_PRODUCT_PROMISE_PDC20617, 168 0, 169 "Promise PDC2020617 Ultra/133 controller", 170 pdcsata_chip_map, 171 }, 172 { PCI_PRODUCT_PROMISE_PDC20618, 173 0, 174 "Promise PDC20618 Ultra/133 controller", 175 pdcsata_chip_map, 176 }, 177 { PCI_PRODUCT_PROMISE_PDC20619, 178 0, 179 "Promise PDC20619 Ultra/133 controller", 180 pdcsata_chip_map, 181 }, 182 { PCI_PRODUCT_PROMISE_PDC20620, 183 0, 184 "Promise PDC20620 Ultra/133 controller", 185 pdcsata_chip_map, 186 }, 187 { PCI_PRODUCT_PROMISE_PDC20621, 188 0, 189 "Promise PDC20621 Ultra/133 controller", 190 pdcsata_chip_map, 191 }, 192 { 0, 193 0, 194 NULL, 195 NULL 196 } 197 }; 198 199 static int 200 pdcsata_match(device_t parent, cfdata_t match, void *aux) 201 { 202 struct pci_attach_args *pa = aux; 203 204 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 205 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 206 return (2); 207 } 208 return (0); 209 } 210 211 static void 212 pdcsata_attach(device_t parent, device_t self, void *aux) 213 { 214 struct pci_attach_args *pa = aux; 215 struct pciide_softc *sc = device_private(self); 216 217 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 218 219 sc->sc_wdcdev.sc_atac.atac_dev = self; 220 221 pciide_common_attach(sc, pa, 222 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 223 } 224 225 static void 226 pdcsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 227 { 228 struct pciide_channel *cp; 229 struct ata_channel *wdc_cp; 230 struct wdc_regs *wdr; 231 int channel, i; 232 pci_intr_handle_t intrhandle; 233 const char *intrstr; 234 235 /* 236 * Promise SATA controllers have 3 or 4 channels, 237 * the usual IDE registers are mapped in I/O space, with offsets. 238 */ 239 if (pci_intr_map(pa, &intrhandle) != 0) { 240 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 241 "couldn't map interrupt\n"); 242 return; 243 } 244 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 245 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 246 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 247 248 if (sc->sc_pci_ih == NULL) { 249 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 250 "couldn't establish native-PCI interrupt"); 251 if (intrstr != NULL) 252 aprint_error(" at %s", intrstr); 253 aprint_error("\n"); 254 return; 255 } 256 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 257 "interrupting at %s\n", 258 intrstr ? intrstr : "unknown interrupt"); 259 260 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 261 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 262 &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios) == 0); 263 if (!sc->sc_dma_ok) { 264 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 265 "couldn't map bus-master DMA registers\n"); 266 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 267 return; 268 } 269 270 sc->sc_dmat = pa->pa_dmat; 271 272 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 273 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 274 &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 275 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 276 "couldn't map IDE registers\n"); 277 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios); 278 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 279 return; 280 } 281 282 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 283 "bus-master DMA support present\n"); 284 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 285 if (sc->sc_dma_ok) { 286 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 287 } 288 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 289 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 290 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 291 sc->sc_wdcdev.irqack = pdc203xx_irqack; 292 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 293 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 294 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 295 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 296 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 297 sc->sc_wdcdev.wdc_maxdrives = 2; 298 299 sc->sc_wdcdev.reset = pdcsata_do_reset; 300 301 switch (sc->sc_pp->ide_product) { 302 case PCI_PRODUCT_PROMISE_PDC20318: 303 case PCI_PRODUCT_PROMISE_PDC20319: 304 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 305 0x00ff0033); 306 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 307 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_SATA_NCHANNELS; 308 sc->sc_wdcdev.wdc_maxdrives = 1; 309 break; 310 case PCI_PRODUCT_PROMISE_PDC20371: 311 case PCI_PRODUCT_PROMISE_PDC20375: 312 case PCI_PRODUCT_PROMISE_PDC20376: 313 case PCI_PRODUCT_PROMISE_PDC20377: 314 case PCI_PRODUCT_PROMISE_PDC20378: 315 case PCI_PRODUCT_PROMISE_PDC20379: 316 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 317 0x00ff0033); 318 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 319 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_COMBO_NCHANNELS; 320 break; 321 322 case PCI_PRODUCT_PROMISE_PDC40518: 323 case PCI_PRODUCT_PROMISE_PDC40519: 324 case PCI_PRODUCT_PROMISE_PDC40718: 325 case PCI_PRODUCT_PROMISE_PDC40719: 326 case PCI_PRODUCT_PROMISE_PDC40779: 327 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 328 0x00ff00ff); 329 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_SATA_NCHANNELS; 330 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 331 sc->sc_wdcdev.wdc_maxdrives = 1; 332 break; 333 334 case PCI_PRODUCT_PROMISE_PDC20571: 335 case PCI_PRODUCT_PROMISE_PDC20575: 336 case PCI_PRODUCT_PROMISE_PDC20579: 337 case PCI_PRODUCT_PROMISE_PDC20771: 338 case PCI_PRODUCT_PROMISE_PDC20775: 339 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 340 0x00ff00ff); 341 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_COMBO_NCHANNELS; 342 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 343 break; 344 345 case PCI_PRODUCT_PROMISE_PDC20617: 346 case PCI_PRODUCT_PROMISE_PDC20618: 347 case PCI_PRODUCT_PROMISE_PDC20619: 348 case PCI_PRODUCT_PROMISE_PDC20620: 349 case PCI_PRODUCT_PROMISE_PDC20621: 350 sc->sc_wdcdev.sc_atac.atac_nchannels = 351 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 352 0x48) & 0x01) ? 1 : 0) + 353 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 354 0x48) & 0x02) ? 1 : 0) + 355 2; 356 sc->sc_wdcdev.sc_atac.atac_probe = wdc_drvprobe; 357 358 default: 359 aprint_error("unknown promise product 0x%x\n", 360 sc->sc_pp->ide_product); 361 } 362 363 wdc_allocate_regs(&sc->sc_wdcdev); 364 365 sc->sc_wdcdev.dma_arg = sc; 366 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 367 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 368 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 369 370 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 371 channel++) { 372 cp = &sc->pciide_channels[channel]; 373 sc->wdc_chanarray[channel] = &cp->ata_channel; 374 375 cp->ih = sc->sc_pci_ih; 376 cp->name = NULL; 377 cp->ata_channel.ch_channel = channel; 378 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 379 cp->ata_channel.ch_queue = 380 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 381 if (cp->ata_channel.ch_queue == NULL) { 382 aprint_error("%s channel %d: " 383 "can't allocate memory for command queue\n", 384 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 385 channel); 386 goto next_channel; 387 } 388 wdc_cp = &cp->ata_channel; 389 wdr = CHAN_TO_WDC_REGS(wdc_cp); 390 391 wdr->ctl_iot = sc->sc_ba5_st; 392 wdr->cmd_iot = sc->sc_ba5_st; 393 394 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 395 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 396 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 397 "couldn't map channel %d ctl regs\n", channel); 398 goto next_channel; 399 } 400 for (i = 0; i < WDC_NREG; i++) { 401 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 402 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 403 &wdr->cmd_iohs[i]) != 0) { 404 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 405 "couldn't map channel %d cmd regs\n", 406 channel); 407 goto next_channel; 408 } 409 } 410 wdc_init_shadow_regs(wdc_cp); 411 412 /* 413 * subregion de busmaster registers. They're spread all over 414 * the controller's register space :(. They are also 4 bytes 415 * sized, with some specific extentions in the extra bits. 416 * It also seems that the IDEDMA_CTL register isn't available. 417 */ 418 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 419 0x260 + (channel << 7), 1, 420 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 421 aprint_normal("%s channel %d: can't subregion DMA " 422 "registers\n", 423 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 424 channel); 425 goto next_channel; 426 } 427 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 428 0x244 + (channel << 7), 4, 429 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 430 aprint_normal("%s channel %d: can't subregion DMA " 431 "registers\n", 432 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 433 channel); 434 goto next_channel; 435 } 436 437 /* subregion the SATA registers */ 438 if (sc->sc_wdcdev.sc_atac.atac_probe == wdc_sataprobe || 439 (sc->sc_wdcdev.sc_atac.atac_probe == pdc203xx_combo_probe 440 && channel < 2)) { 441 wdr->sata_iot = sc->sc_ba5_st; 442 wdr->sata_baseioh = sc->sc_ba5_sh; 443 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 444 PDC205_SSTATUS(channel), 1, 445 &wdr->sata_status) != 0) { 446 aprint_error_dev( 447 sc->sc_wdcdev.sc_atac.atac_dev, 448 "couldn't map channel %d " 449 "sata_status regs\n", channel); 450 goto next_channel; 451 } 452 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 453 PDC205_SERROR(channel), 1, &wdr->sata_error) != 0) { 454 aprint_error_dev( 455 sc->sc_wdcdev.sc_atac.atac_dev, 456 "couldn't map channel %d " 457 "sata_error regs\n", channel); 458 goto next_channel; 459 } 460 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 461 PDC205_SCONTROL(channel), 1, 462 &wdr->sata_control) != 0) { 463 aprint_error_dev( 464 sc->sc_wdcdev.sc_atac.atac_dev, 465 "couldn't map channel %d " 466 "sata_control regs\n", channel); 467 goto next_channel; 468 } 469 } 470 471 wdcattach(wdc_cp); 472 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 473 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 474 0) & ~0x00003f9f) | (channel + 1)); 475 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 476 (channel + 1) << 2, 0x00000001); 477 next_channel: 478 continue; 479 } 480 return; 481 } 482 483 static void 484 pdc203xx_combo_probe(struct ata_channel *chp) 485 { 486 if (chp->ch_channel < 2) 487 wdc_sataprobe(chp); 488 else 489 wdc_drvprobe(chp); 490 } 491 492 static void 493 pdc203xx_setup_channel(struct ata_channel *chp) 494 { 495 struct ata_drive_datas *drvp; 496 int drive, s; 497 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 498 499 pciide_channel_dma_setup(cp); 500 501 for (drive = 0; drive < 2; drive++) { 502 drvp = &chp->ch_drive[drive]; 503 if (drvp->drive_type == ATA_DRIVET_NONE) 504 continue; 505 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 506 s = splbio(); 507 drvp->drive_flags &= ~ATA_DRIVE_DMA; 508 splx(s); 509 } 510 } 511 } 512 513 static int 514 pdcsata_pci_intr(void *arg) 515 { 516 struct pciide_softc *sc = arg; 517 struct pciide_channel *cp; 518 struct ata_channel *wdc_cp; 519 int i, rv, crv; 520 u_int32_t scr, status, chanbase; 521 522 rv = 0; 523 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 524 if (scr == 0xffffffff) return(rv); 525 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 526 scr = scr & 0x0000ffff; 527 if (!scr) return(rv); 528 529 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 530 cp = &sc->pciide_channels[i]; 531 wdc_cp = &cp->ata_channel; 532 if (scr & (1 << (i + 1))) { 533 chanbase = PDC_CHANNELBASE(i) + 0x48; 534 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 535 if (status & PDC_ERRMASK) { 536 chanbase = PDC_CHANNELBASE(i) + 0x60; 537 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 538 status |= 0x800; 539 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 540 status &= ~0x800; 541 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 542 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 543 continue; 544 } 545 crv = wdcintr(wdc_cp); 546 if (crv == 0) { 547 aprint_error("%s:%d: bogus intr (reg 0x%x)\n", 548 device_xname( 549 sc->sc_wdcdev.sc_atac.atac_dev), i, scr); 550 } else 551 rv = 1; 552 } 553 } 554 return rv; 555 } 556 557 static void 558 pdc203xx_irqack(struct ata_channel *chp) 559 { 560 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 561 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 562 563 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 564 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 565 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 566 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 567 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 568 } 569 570 static int 571 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 572 size_t datalen, int flags) 573 { 574 struct pciide_softc *sc = v; 575 576 return pciide_dma_dmamap_setup(sc, channel, drive, 577 databuf, datalen, flags); 578 } 579 580 static void 581 pdc203xx_dma_start(void *v, int channel, int drive) 582 { 583 struct pciide_softc *sc = v; 584 struct pciide_channel *cp = &sc->pciide_channels[channel]; 585 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 586 587 /* Write table addr */ 588 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 589 dma_maps->dmamap_table->dm_segs[0].ds_addr); 590 /* start DMA engine */ 591 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 592 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 593 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 594 } 595 596 static int 597 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 598 { 599 struct pciide_softc *sc = v; 600 struct pciide_channel *cp = &sc->pciide_channels[channel]; 601 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 602 603 /* stop DMA channel */ 604 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 605 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 606 0) & ~0x80)); 607 608 /* Unload the map of the data buffer */ 609 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 610 dma_maps->dmamap_xfer->dm_mapsize, 611 (dma_maps->dma_flags & WDC_DMA_READ) ? 612 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 613 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 614 615 return 0; 616 } 617 618 619 static void 620 pdcsata_do_reset(struct ata_channel *chp, int poll) 621 { 622 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 623 int reset, status, i, chanbase; 624 625 /* reset SATA */ 626 reset = (1 << 11); 627 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 628 for (i = 0; i < 11;i ++) { 629 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 630 if (status & reset) break; 631 delay(100); 632 status |= reset; 633 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 634 } 635 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 636 status &= ~reset; 637 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 638 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 639 640 wdc_do_reset(chp, poll); 641 } 642
Indexes created Fri Oct 03 02:09:57 GMT 2025