pdcsata.c revision 1.28
1 /* $NetBSD: pdcsata.c,v 1.28 2017/10/07 16:05:33 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.28 2017/10/07 16:05:33 jdolecek Exp $"); 29 30 #include <sys/types.h> 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/ata/atareg.h> 39 #include <dev/ata/satavar.h> 40 #include <dev/ata/satareg.h> 41 42 #define PDC203xx_SATA_NCHANNELS 4 43 #define PDC203xx_COMBO_NCHANNELS 3 44 #define PDC40718_SATA_NCHANNELS 4 45 #define PDC20575_COMBO_NCHANNELS 3 46 47 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 48 49 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 50 #define PDC_ERRMASK 0x00780700 51 52 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 53 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 54 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 55 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 56 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 57 58 static void pdcsata_chip_map(struct pciide_softc *, 59 const struct pci_attach_args *); 60 static void pdc203xx_setup_channel(struct ata_channel *); 61 static void pdc203xx_irqack(struct ata_channel *); 62 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 63 static void pdc203xx_dma_start(void *,int ,int); 64 static int pdc203xx_dma_finish(void *, int, int, int); 65 static void pdc203xx_combo_probe(struct ata_channel *); 66 static int pdcsata_pci_intr(void *); 67 static void pdcsata_do_reset(struct ata_channel *, int); 68 69 static int pdcsata_match(device_t, cfdata_t, void *); 70 static void pdcsata_attach(device_t, device_t, void *); 71 72 CFATTACH_DECL_NEW(pdcsata, sizeof(struct pciide_softc), 73 pdcsata_match, pdcsata_attach, pciide_detach, NULL); 74 75 static const struct pciide_product_desc pciide_pdcsata_products[] = { 76 { PCI_PRODUCT_PROMISE_PDC20318, 77 0, 78 "Promise PDC20318 SATA150 controller", 79 pdcsata_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_PDC20319, 82 0, 83 "Promise PDC20319 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20371, 87 0, 88 "Promise PDC20371 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20375, 92 0, 93 "Promise PDC20375 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20376, 97 0, 98 "Promise PDC20376 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_PDC20377, 102 0, 103 "Promise PDC20377 SATA150 controller", 104 pdcsata_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_PDC20378, 107 0, 108 "Promise PDC20378 SATA150 controller", 109 pdcsata_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_PDC20379, 112 0, 113 "Promise PDC20379 SATA150 controller", 114 pdcsata_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_PDC40518, 117 0, 118 "Promise PDC40518 SATA150 controller", 119 pdcsata_chip_map, 120 }, 121 { PCI_PRODUCT_PROMISE_PDC40519, 122 0, 123 "Promise PDC40519 SATA 150 controller", 124 pdcsata_chip_map, 125 }, 126 { PCI_PRODUCT_PROMISE_PDC40718, 127 0, 128 "Promise PDC40718 SATA300 controller", 129 pdcsata_chip_map, 130 }, 131 { PCI_PRODUCT_PROMISE_PDC40719, 132 0, 133 "Promise PDC40719 SATA300 controller", 134 pdcsata_chip_map, 135 }, 136 { PCI_PRODUCT_PROMISE_PDC40779, 137 0, 138 "Promise PDC40779 SATA300 controller", 139 pdcsata_chip_map, 140 }, 141 { PCI_PRODUCT_PROMISE_PDC20571, 142 0, 143 "Promise PDC20571 SATA150 controller", 144 pdcsata_chip_map, 145 }, 146 { PCI_PRODUCT_PROMISE_PDC20575, 147 0, 148 "Promise PDC20575 SATA150 controller", 149 pdcsata_chip_map, 150 }, 151 { PCI_PRODUCT_PROMISE_PDC20579, 152 0, 153 "Promise PDC20579 SATA150 controller", 154 pdcsata_chip_map, 155 }, 156 { PCI_PRODUCT_PROMISE_PDC20771, 157 0, 158 "Promise PDC20771 SATA300 controller", 159 pdcsata_chip_map, 160 }, 161 { PCI_PRODUCT_PROMISE_PDC20775, 162 0, 163 "Promise PDC20775 SATA300 controller", 164 pdcsata_chip_map, 165 }, 166 { PCI_PRODUCT_PROMISE_PDC20617, 167 0, 168 "Promise PDC2020617 Ultra/133 controller", 169 pdcsata_chip_map, 170 }, 171 { PCI_PRODUCT_PROMISE_PDC20618, 172 0, 173 "Promise PDC20618 Ultra/133 controller", 174 pdcsata_chip_map, 175 }, 176 { PCI_PRODUCT_PROMISE_PDC20619, 177 0, 178 "Promise PDC20619 Ultra/133 controller", 179 pdcsata_chip_map, 180 }, 181 { PCI_PRODUCT_PROMISE_PDC20620, 182 0, 183 "Promise PDC20620 Ultra/133 controller", 184 pdcsata_chip_map, 185 }, 186 { PCI_PRODUCT_PROMISE_PDC20621, 187 0, 188 "Promise PDC20621 Ultra/133 controller", 189 pdcsata_chip_map, 190 }, 191 { 0, 192 0, 193 NULL, 194 NULL 195 } 196 }; 197 198 static int 199 pdcsata_match(device_t parent, cfdata_t match, void *aux) 200 { 201 struct pci_attach_args *pa = aux; 202 203 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 204 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 205 return (2); 206 } 207 return (0); 208 } 209 210 static void 211 pdcsata_attach(device_t parent, device_t self, void *aux) 212 { 213 struct pci_attach_args *pa = aux; 214 struct pciide_softc *sc = device_private(self); 215 216 sc->sc_wdcdev.sc_atac.atac_dev = self; 217 218 pciide_common_attach(sc, pa, 219 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 220 } 221 222 static void 223 pdcsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 224 { 225 struct pciide_channel *cp; 226 struct ata_channel *wdc_cp; 227 struct wdc_regs *wdr; 228 int channel, i; 229 pci_intr_handle_t intrhandle; 230 const char *intrstr; 231 char intrbuf[PCI_INTRSTR_LEN]; 232 233 /* 234 * Promise SATA controllers have 3 or 4 channels, 235 * the usual IDE registers are mapped in I/O space, with offsets. 236 */ 237 if (pci_intr_map(pa, &intrhandle) != 0) { 238 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 239 "couldn't map interrupt\n"); 240 return; 241 } 242 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 243 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 244 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 245 246 if (sc->sc_pci_ih == NULL) { 247 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 248 "couldn't establish native-PCI interrupt"); 249 if (intrstr != NULL) 250 aprint_error(" at %s", intrstr); 251 aprint_error("\n"); 252 return; 253 } 254 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 255 "interrupting at %s\n", 256 intrstr ? intrstr : "unknown interrupt"); 257 258 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 259 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 260 &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios) == 0); 261 if (!sc->sc_dma_ok) { 262 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 263 "couldn't map bus-master DMA registers\n"); 264 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 265 return; 266 } 267 268 sc->sc_dmat = pa->pa_dmat; 269 270 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 271 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 272 &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 273 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 274 "couldn't map IDE registers\n"); 275 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios); 276 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 277 return; 278 } 279 280 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 281 "bus-master DMA support present\n"); 282 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 283 if (sc->sc_dma_ok) { 284 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 285 } 286 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 287 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 288 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 289 sc->sc_wdcdev.irqack = pdc203xx_irqack; 290 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 291 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 292 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 293 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 294 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 295 sc->sc_wdcdev.wdc_maxdrives = 2; 296 297 sc->sc_wdcdev.reset = pdcsata_do_reset; 298 299 switch (sc->sc_pp->ide_product) { 300 case PCI_PRODUCT_PROMISE_PDC20318: 301 case PCI_PRODUCT_PROMISE_PDC20319: 302 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 303 0x00ff0033); 304 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 305 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_SATA_NCHANNELS; 306 sc->sc_wdcdev.wdc_maxdrives = 1; 307 break; 308 case PCI_PRODUCT_PROMISE_PDC20371: 309 case PCI_PRODUCT_PROMISE_PDC20375: 310 case PCI_PRODUCT_PROMISE_PDC20376: 311 case PCI_PRODUCT_PROMISE_PDC20377: 312 case PCI_PRODUCT_PROMISE_PDC20378: 313 case PCI_PRODUCT_PROMISE_PDC20379: 314 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 315 0x00ff0033); 316 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 317 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_COMBO_NCHANNELS; 318 break; 319 320 case PCI_PRODUCT_PROMISE_PDC40518: 321 case PCI_PRODUCT_PROMISE_PDC40519: 322 case PCI_PRODUCT_PROMISE_PDC40718: 323 case PCI_PRODUCT_PROMISE_PDC40719: 324 case PCI_PRODUCT_PROMISE_PDC40779: 325 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 326 0x00ff00ff); 327 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_SATA_NCHANNELS; 328 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 329 sc->sc_wdcdev.wdc_maxdrives = 1; 330 break; 331 332 case PCI_PRODUCT_PROMISE_PDC20571: 333 case PCI_PRODUCT_PROMISE_PDC20575: 334 case PCI_PRODUCT_PROMISE_PDC20579: 335 case PCI_PRODUCT_PROMISE_PDC20771: 336 case PCI_PRODUCT_PROMISE_PDC20775: 337 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 338 0x00ff00ff); 339 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_COMBO_NCHANNELS; 340 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 341 break; 342 343 case PCI_PRODUCT_PROMISE_PDC20617: 344 case PCI_PRODUCT_PROMISE_PDC20618: 345 case PCI_PRODUCT_PROMISE_PDC20619: 346 case PCI_PRODUCT_PROMISE_PDC20620: 347 case PCI_PRODUCT_PROMISE_PDC20621: 348 sc->sc_wdcdev.sc_atac.atac_nchannels = 349 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 350 0x48) & 0x01) ? 1 : 0) + 351 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 352 0x48) & 0x02) ? 1 : 0) + 353 2; 354 sc->sc_wdcdev.sc_atac.atac_probe = wdc_drvprobe; 355 356 default: 357 aprint_error("unknown promise product 0x%x\n", 358 sc->sc_pp->ide_product); 359 } 360 361 wdc_allocate_regs(&sc->sc_wdcdev); 362 363 sc->sc_wdcdev.dma_arg = sc; 364 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 365 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 366 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 367 368 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 369 channel++) { 370 cp = &sc->pciide_channels[channel]; 371 sc->wdc_chanarray[channel] = &cp->ata_channel; 372 373 cp->ih = sc->sc_pci_ih; 374 cp->name = NULL; 375 cp->ata_channel.ch_channel = channel; 376 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 377 cp->ata_channel.ch_queue = ata_queue_alloc(1); 378 if (cp->ata_channel.ch_queue == NULL) { 379 aprint_error("%s channel %d: " 380 "can't allocate memory for command queue\n", 381 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 382 channel); 383 goto next_channel; 384 } 385 wdc_cp = &cp->ata_channel; 386 wdr = CHAN_TO_WDC_REGS(wdc_cp); 387 388 wdr->ctl_iot = sc->sc_ba5_st; 389 wdr->cmd_iot = sc->sc_ba5_st; 390 391 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 392 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 393 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 394 "couldn't map channel %d ctl regs\n", channel); 395 goto next_channel; 396 } 397 for (i = 0; i < WDC_NREG; i++) { 398 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 399 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 400 &wdr->cmd_iohs[i]) != 0) { 401 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 402 "couldn't map channel %d cmd regs\n", 403 channel); 404 goto next_channel; 405 } 406 } 407 wdc_init_shadow_regs(wdr); 408 409 /* 410 * subregion de busmaster registers. They're spread all over 411 * the controller's register space :(. They are also 4 bytes 412 * sized, with some specific extentions in the extra bits. 413 * It also seems that the IDEDMA_CTL register isn't available. 414 */ 415 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 416 0x260 + (channel << 7), 1, 417 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 418 aprint_normal("%s channel %d: can't subregion DMA " 419 "registers\n", 420 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 421 channel); 422 goto next_channel; 423 } 424 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 425 0x244 + (channel << 7), 4, 426 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 427 aprint_normal("%s channel %d: can't subregion DMA " 428 "registers\n", 429 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 430 channel); 431 goto next_channel; 432 } 433 434 /* subregion the SATA registers */ 435 if (sc->sc_wdcdev.sc_atac.atac_probe == wdc_sataprobe || 436 (sc->sc_wdcdev.sc_atac.atac_probe == pdc203xx_combo_probe 437 && channel < 2)) { 438 wdr->sata_iot = sc->sc_ba5_st; 439 wdr->sata_baseioh = sc->sc_ba5_sh; 440 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 441 PDC205_SSTATUS(channel), 1, 442 &wdr->sata_status) != 0) { 443 aprint_error_dev( 444 sc->sc_wdcdev.sc_atac.atac_dev, 445 "couldn't map channel %d " 446 "sata_status regs\n", channel); 447 goto next_channel; 448 } 449 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 450 PDC205_SERROR(channel), 1, &wdr->sata_error) != 0) { 451 aprint_error_dev( 452 sc->sc_wdcdev.sc_atac.atac_dev, 453 "couldn't map channel %d " 454 "sata_error regs\n", channel); 455 goto next_channel; 456 } 457 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 458 PDC205_SCONTROL(channel), 1, 459 &wdr->sata_control) != 0) { 460 aprint_error_dev( 461 sc->sc_wdcdev.sc_atac.atac_dev, 462 "couldn't map channel %d " 463 "sata_control regs\n", channel); 464 goto next_channel; 465 } 466 } 467 468 wdcattach(wdc_cp); 469 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 470 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 471 0) & ~0x00003f9f) | (channel + 1)); 472 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 473 (channel + 1) << 2, 0x00000001); 474 next_channel: 475 continue; 476 } 477 return; 478 } 479 480 static void 481 pdc203xx_combo_probe(struct ata_channel *chp) 482 { 483 if (chp->ch_channel < 2) 484 wdc_sataprobe(chp); 485 else 486 wdc_drvprobe(chp); 487 } 488 489 static void 490 pdc203xx_setup_channel(struct ata_channel *chp) 491 { 492 struct ata_drive_datas *drvp; 493 int drive, s; 494 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 495 496 pciide_channel_dma_setup(cp); 497 498 for (drive = 0; drive < 2; drive++) { 499 drvp = &chp->ch_drive[drive]; 500 if (drvp->drive_type == ATA_DRIVET_NONE) 501 continue; 502 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 503 s = splbio(); 504 drvp->drive_flags &= ~ATA_DRIVE_DMA; 505 splx(s); 506 } 507 } 508 } 509 510 static int 511 pdcsata_pci_intr(void *arg) 512 { 513 struct pciide_softc *sc = arg; 514 struct pciide_channel *cp; 515 struct ata_channel *wdc_cp; 516 int i, rv, crv; 517 u_int32_t scr, status, chanbase; 518 519 rv = 0; 520 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 521 if (scr == 0xffffffff) return(rv); 522 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 523 scr = scr & 0x0000ffff; 524 if (!scr) return(rv); 525 526 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 527 cp = &sc->pciide_channels[i]; 528 wdc_cp = &cp->ata_channel; 529 if (scr & (1 << (i + 1))) { 530 chanbase = PDC_CHANNELBASE(i) + 0x48; 531 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 532 if (status & PDC_ERRMASK) { 533 chanbase = PDC_CHANNELBASE(i) + 0x60; 534 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 535 status |= 0x800; 536 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 537 status &= ~0x800; 538 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 539 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 540 continue; 541 } 542 crv = wdcintr(wdc_cp); 543 if (crv == 0) { 544 aprint_error("%s:%d: bogus intr (reg 0x%x)\n", 545 device_xname( 546 sc->sc_wdcdev.sc_atac.atac_dev), i, scr); 547 } else 548 rv = 1; 549 } 550 } 551 return rv; 552 } 553 554 static void 555 pdc203xx_irqack(struct ata_channel *chp) 556 { 557 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 558 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 559 560 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 561 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 562 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 563 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 564 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 565 } 566 567 static int 568 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 569 size_t datalen, int flags) 570 { 571 struct pciide_softc *sc = v; 572 573 return pciide_dma_dmamap_setup(sc, channel, drive, 574 databuf, datalen, flags); 575 } 576 577 static void 578 pdc203xx_dma_start(void *v, int channel, int drive) 579 { 580 struct pciide_softc *sc = v; 581 struct pciide_channel *cp = &sc->pciide_channels[channel]; 582 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 583 584 /* Write table addr */ 585 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 586 dma_maps->dmamap_table->dm_segs[0].ds_addr); 587 /* start DMA engine */ 588 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 589 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 590 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 591 } 592 593 static int 594 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 595 { 596 struct pciide_softc *sc = v; 597 struct pciide_channel *cp = &sc->pciide_channels[channel]; 598 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 599 600 /* stop DMA channel */ 601 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 602 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 603 0) & ~0x80)); 604 605 /* Unload the map of the data buffer */ 606 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 607 dma_maps->dmamap_xfer->dm_mapsize, 608 (dma_maps->dma_flags & WDC_DMA_READ) ? 609 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 610 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 611 612 return 0; 613 } 614 615 616 static void 617 pdcsata_do_reset(struct ata_channel *chp, int poll) 618 { 619 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 620 int reset, status, i, chanbase; 621 622 /* reset SATA */ 623 reset = (1 << 11); 624 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 625 for (i = 0; i < 11;i ++) { 626 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 627 if (status & reset) break; 628 delay(100); 629 status |= reset; 630 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 631 } 632 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 633 status &= ~reset; 634 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 635 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 636 637 wdc_do_reset(chp, poll); 638 } 639
Indexes created Tue Sep 30 11:09:46 GMT 2025