pdcsata.c revision 1.3.2.3
1 /* $NetBSD: pdcsata.c,v 1.3.2.3 2006/07/28 03:45:42 riz Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/malloc.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pciidereg.h> 40 #include <dev/pci/pciidevar.h> 41 #include <dev/ata/atareg.h> 42 #include <dev/ata/satavar.h> 43 #include <dev/ata/satareg.h> 44 45 #define PDC203xx_NCHANNELS 4 46 #define PDC40718_NCHANNELS 4 47 #define PDC20575_NCHANNELS 3 48 49 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 50 51 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 52 #define PDC_ERRMASK 0x00780700 53 54 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 55 static void pdc203xx_setup_channel(struct ata_channel *); 56 static void pdc203xx_irqack(struct ata_channel *); 57 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 58 static void pdc203xx_dma_start(void *,int ,int); 59 static int pdc203xx_dma_finish(void *, int, int, int); 60 static int pdcsata_pci_intr(void *); 61 static void pdcsata_do_reset(struct ata_channel *, int); 62 63 /* PDC205xx, PDC405xx and PDC407xx. but tested only pdc40718 */ 64 static void pdc205xx_drv_probe(struct ata_channel *); 65 66 static int pdcsata_match(struct device *, struct cfdata *, void *); 67 static void pdcsata_attach(struct device *, struct device *, void *); 68 69 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 70 pdcsata_match, pdcsata_attach, NULL, NULL); 71 72 static const struct pciide_product_desc pciide_pdcsata_products[] = { 73 { PCI_PRODUCT_PROMISE_PDC20318, 74 0, 75 "Promise PDC20318 SATA150 controller", 76 pdcsata_chip_map, 77 }, 78 { PCI_PRODUCT_PROMISE_PDC20319, 79 0, 80 "Promise PDC20319 SATA150 controller", 81 pdcsata_chip_map, 82 }, 83 { PCI_PRODUCT_PROMISE_PDC20371, 84 0, 85 "Promise PDC20371 SATA150 controller", 86 pdcsata_chip_map, 87 }, 88 { PCI_PRODUCT_PROMISE_PDC20375, 89 0, 90 "Promise PDC20375 SATA150 controller", 91 pdcsata_chip_map, 92 }, 93 { PCI_PRODUCT_PROMISE_PDC20376, 94 0, 95 "Promise PDC20376 SATA150 controller", 96 pdcsata_chip_map, 97 }, 98 { PCI_PRODUCT_PROMISE_PDC20377, 99 0, 100 "Promise PDC20377 SATA150 controller", 101 pdcsata_chip_map, 102 }, 103 { PCI_PRODUCT_PROMISE_PDC20378, 104 0, 105 "Promise PDC20378 SATA150 controller", 106 pdcsata_chip_map, 107 }, 108 { PCI_PRODUCT_PROMISE_PDC20379, 109 0, 110 "Promise PDC20379 SATA150 controller", 111 pdcsata_chip_map, 112 }, 113 { PCI_PRODUCT_PROMISE_PDC40718, 114 0, 115 "Promise PDC40718 SATA300 controller", 116 pdcsata_chip_map, 117 }, 118 { PCI_PRODUCT_PROMISE_PDC40719, 119 0, 120 "Promise PDC40719 SATA300 controller", 121 pdcsata_chip_map, 122 }, 123 { PCI_PRODUCT_PROMISE_PDC20571, 124 0, 125 "Promise PDC20571 SATA150 controller", 126 pdcsata_chip_map, 127 }, 128 { PCI_PRODUCT_PROMISE_PDC20575, 129 0, 130 "Promise PDC20575 SATA150 controller", 131 pdcsata_chip_map, 132 }, 133 { PCI_PRODUCT_PROMISE_PDC20579, 134 0, 135 "Promise PDC20579 SATA150 controller", 136 pdcsata_chip_map, 137 }, 138 { 0, 139 0, 140 NULL, 141 NULL 142 } 143 }; 144 145 static int 146 pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 147 { 148 struct pci_attach_args *pa = aux; 149 150 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 151 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 152 return (2); 153 } 154 return (0); 155 } 156 157 static void 158 pdcsata_attach(struct device *parent, struct device *self, void *aux) 159 { 160 struct pci_attach_args *pa = aux; 161 struct pciide_softc *sc = (struct pciide_softc *)self; 162 163 pciide_common_attach(sc, pa, 164 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 165 } 166 167 static void 168 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 169 { 170 struct pciide_channel *cp; 171 struct ata_channel *wdc_cp; 172 struct wdc_regs *wdr; 173 int channel, i; 174 bus_size_t dmasize; 175 pci_intr_handle_t intrhandle; 176 const char *intrstr; 177 178 /* 179 * Promise SATA controllers have 3 or 4 channels, 180 * the usual IDE registers are mapped in I/O space, with offsets. 181 */ 182 if (pci_intr_map(pa, &intrhandle) != 0) { 183 aprint_error("%s: couldn't map interrupt\n", 184 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 185 return; 186 } 187 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 188 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 189 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 190 191 if (sc->sc_pci_ih == NULL) { 192 aprint_error("%s: couldn't establish native-PCI interrupt", 193 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 194 if (intrstr != NULL) 195 aprint_normal(" at %s", intrstr); 196 aprint_normal("\n"); 197 return; 198 } 199 aprint_normal("%s: interrupting at %s\n", 200 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 201 intrstr ? intrstr : "unknown interrupt"); 202 203 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 204 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 205 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 206 if (!sc->sc_dma_ok) { 207 aprint_error("%s: couldn't map bus-master DMA registers\n", 208 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 209 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 210 return; 211 } 212 213 sc->sc_dmat = pa->pa_dmat; 214 215 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 216 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 217 &sc->sc_ba5_sh, NULL, NULL) != 0) { 218 aprint_error("%s: couldn't map IDE registers\n", 219 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 220 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 221 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 222 return; 223 } 224 225 aprint_normal("%s: bus-master DMA support present\n", 226 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 227 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 228 if (sc->sc_dma_ok) { 229 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 230 } 231 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 232 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 233 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 234 sc->sc_wdcdev.irqack = pdc203xx_irqack; 235 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 236 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 237 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 238 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 239 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 240 241 sc->sc_wdcdev.reset = pdcsata_do_reset; 242 243 switch (sc->sc_pp->ide_product) { 244 case PCI_PRODUCT_PROMISE_PDC20318: 245 case PCI_PRODUCT_PROMISE_PDC20319: 246 case PCI_PRODUCT_PROMISE_PDC20371: 247 case PCI_PRODUCT_PROMISE_PDC20375: 248 case PCI_PRODUCT_PROMISE_PDC20376: 249 case PCI_PRODUCT_PROMISE_PDC20377: 250 case PCI_PRODUCT_PROMISE_PDC20378: 251 case PCI_PRODUCT_PROMISE_PDC20379: 252 default: 253 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 0x00ff0033); 254 sc->sc_wdcdev.sc_atac.atac_nchannels = 255 (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 256 PDC203xx_NCHANNELS : 3; 257 258 break; 259 260 case PCI_PRODUCT_PROMISE_PDC40718: 261 case PCI_PRODUCT_PROMISE_PDC40719: 262 case PCI_PRODUCT_PROMISE_PDC20571: 263 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 264 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_NCHANNELS; 265 266 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 267 268 break; 269 case PCI_PRODUCT_PROMISE_PDC20575: 270 case PCI_PRODUCT_PROMISE_PDC20579: 271 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 272 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_NCHANNELS; 273 274 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 275 276 break; 277 } 278 279 wdc_allocate_regs(&sc->sc_wdcdev); 280 281 sc->sc_wdcdev.dma_arg = sc; 282 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 283 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 284 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 285 286 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 287 channel++) { 288 cp = &sc->pciide_channels[channel]; 289 sc->wdc_chanarray[channel] = &cp->ata_channel; 290 291 cp->ih = sc->sc_pci_ih; 292 cp->name = NULL; 293 cp->ata_channel.ch_channel = channel; 294 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 295 cp->ata_channel.ch_queue = 296 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 297 if (cp->ata_channel.ch_queue == NULL) { 298 aprint_error("%s channel %d: " 299 "can't allocate memory for command queue\n", 300 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 301 goto next_channel; 302 } 303 wdc_cp = &cp->ata_channel; 304 wdr = CHAN_TO_WDC_REGS(wdc_cp); 305 306 wdr->ctl_iot = sc->sc_ba5_st; 307 wdr->cmd_iot = sc->sc_ba5_st; 308 309 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 310 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 311 aprint_error("%s: couldn't map channel %d ctl regs\n", 312 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 313 channel); 314 goto next_channel; 315 } 316 for (i = 0; i < WDC_NREG; i++) { 317 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 318 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 319 &wdr->cmd_iohs[i]) != 0) { 320 aprint_error("%s: couldn't map channel %d cmd " 321 "regs\n", 322 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 323 channel); 324 goto next_channel; 325 } 326 } 327 wdc_init_shadow_regs(wdc_cp); 328 329 /* 330 * subregion de busmaster registers. They're spread all over 331 * the controller's register space :(. They are also 4 bytes 332 * sized, with some specific extentions in the extra bits. 333 * It also seems that the IDEDMA_CTL register isn't available. 334 */ 335 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 336 0x260 + (channel << 7), 1, 337 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 338 aprint_normal("%s channel %d: can't subregion DMA " 339 "registers\n", 340 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 341 goto next_channel; 342 } 343 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 344 0x244 + (channel << 7), 4, 345 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 346 aprint_normal("%s channel %d: can't subregion DMA " 347 "registers\n", 348 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 349 goto next_channel; 350 } 351 352 wdcattach(wdc_cp); 353 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 354 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 355 0) & ~0x00003f9f) | (channel + 1)); 356 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 357 (channel + 1) << 2, 0x00000001); 358 next_channel: 359 continue; 360 } 361 return; 362 } 363 364 static void 365 pdc203xx_setup_channel(struct ata_channel *chp) 366 { 367 struct ata_drive_datas *drvp; 368 int drive, s; 369 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 370 371 pciide_channel_dma_setup(cp); 372 373 for (drive = 0; drive < 2; drive++) { 374 drvp = &chp->ch_drive[drive]; 375 if ((drvp->drive_flags & DRIVE) == 0) 376 continue; 377 if (drvp->drive_flags & DRIVE_UDMA) { 378 s = splbio(); 379 drvp->drive_flags &= ~DRIVE_DMA; 380 splx(s); 381 } 382 } 383 } 384 385 static int 386 pdcsata_pci_intr(void *arg) 387 { 388 struct pciide_softc *sc = arg; 389 struct pciide_channel *cp; 390 struct ata_channel *wdc_cp; 391 int i, rv, crv; 392 u_int32_t scr, status, chanbase; 393 394 rv = 0; 395 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 396 if (scr == 0xffffffff) return(rv); 397 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 398 scr = scr & 0x0000ffff; 399 if (!scr) return(rv); 400 401 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 402 cp = &sc->pciide_channels[i]; 403 wdc_cp = &cp->ata_channel; 404 if (scr & (1 << (i + 1))) { 405 chanbase = PDC_CHANNELBASE(i) + 0x48; 406 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 407 if (status & PDC_ERRMASK) { 408 chanbase = PDC_CHANNELBASE(i) + 0x60; 409 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 410 status |= 0x800; 411 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 412 status &= ~0x800; 413 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 414 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 415 continue; 416 } 417 crv = wdcintr(wdc_cp); 418 if (crv == 0) { 419 printf("%s:%d: bogus intr (reg 0x%x)\n", 420 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 421 i, scr); 422 } else 423 rv = 1; 424 } 425 } 426 return rv; 427 } 428 429 static void 430 pdc203xx_irqack(struct ata_channel *chp) 431 { 432 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 433 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 434 435 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 436 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 437 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 438 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 439 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 440 } 441 442 static int 443 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 444 size_t datalen, int flags) 445 { 446 struct pciide_softc *sc = v; 447 448 return pciide_dma_dmamap_setup(sc, channel, drive, 449 databuf, datalen, flags); 450 } 451 452 static void 453 pdc203xx_dma_start(void *v, int channel, int drive) 454 { 455 struct pciide_softc *sc = v; 456 struct pciide_channel *cp = &sc->pciide_channels[channel]; 457 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 458 459 /* Write table addr */ 460 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 461 dma_maps->dmamap_table->dm_segs[0].ds_addr); 462 /* start DMA engine */ 463 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 464 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 465 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 466 } 467 468 static int 469 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 470 { 471 struct pciide_softc *sc = v; 472 struct pciide_channel *cp = &sc->pciide_channels[channel]; 473 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 474 475 /* stop DMA channel */ 476 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 477 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 478 0) & ~0x80)); 479 480 /* Unload the map of the data buffer */ 481 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 482 dma_maps->dmamap_xfer->dm_mapsize, 483 (dma_maps->dma_flags & WDC_DMA_READ) ? 484 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 485 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 486 487 return 0; 488 } 489 490 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 491 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 492 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 493 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 494 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 495 496 497 #define SCONTROL_WRITE(sc,channel,scontrol) \ 498 bus_space_write_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 499 PDC205_SCONTROL(channel), scontrol) 500 501 #define SSTATUS_READ(sc,channel) \ 502 bus_space_read_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 503 PDC205_SSTATUS(channel)) 504 505 506 507 static void 508 pdcsata_do_reset(struct ata_channel *chp, int poll) 509 { 510 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 511 int reset, status, i, chanbase; 512 513 /* reset SATA */ 514 reset = (1 << 11); 515 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 516 for (i = 0; i < 11;i ++) { 517 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 518 if (status & reset) break; 519 delay(100); 520 status |= reset; 521 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 522 } 523 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 524 status &= ~reset; 525 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 526 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 527 528 wdc_do_reset(chp, poll); 529 530 } 531 532 static void 533 pdc205xx_drv_probe(struct ata_channel *chp) 534 { 535 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 536 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 537 u_int32_t scontrol, sstatus; 538 u_int16_t scnt, sn, cl, ch; 539 int i, s; 540 541 /* XXX This should be done by other code. */ 542 for (i = 0; i < 2; i++) { 543 chp->ch_drive[i].chnl_softc = chp; 544 chp->ch_drive[i].drive = i; 545 } 546 547 SCONTROL_WRITE(sc, chp->ch_channel, 0); 548 delay(50*1000); 549 550 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 551 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 552 delay(50*1000); 553 554 scontrol &= ~SControl_DET_INIT; 555 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 556 delay(50*1000); 557 558 sstatus = SSTATUS_READ(sc,chp->ch_channel); 559 560 switch (sstatus & SStatus_DET_mask) { 561 case SStatus_DET_NODEV: 562 /* No Device; be silent. */ 563 break; 564 565 case SStatus_DET_DEV_NE: 566 aprint_error("%s: port %d: device connected, but " 567 "communication not established\n", 568 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 569 break; 570 571 case SStatus_DET_OFFLINE: 572 aprint_error("%s: port %d: PHY offline\n", 573 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 574 break; 575 576 case SStatus_DET_DEV: 577 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 578 WDSD_IBM); 579 delay(10); /* 400ns delay */ 580 scnt = bus_space_read_2(wdr->cmd_iot, 581 wdr->cmd_iohs[wd_seccnt], 0); 582 sn = bus_space_read_2(wdr->cmd_iot, 583 wdr->cmd_iohs[wd_sector], 0); 584 cl = bus_space_read_2(wdr->cmd_iot, 585 wdr->cmd_iohs[wd_cyl_lo], 0); 586 ch = bus_space_read_2(wdr->cmd_iot, 587 wdr->cmd_iohs[wd_cyl_hi], 0); 588 #if 0 589 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 590 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 591 scnt, sn, cl, ch); 592 #endif 593 /* 594 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 595 * cases we get wrong values here, so ignore it. 596 */ 597 s = splbio(); 598 if (cl == 0x14 && ch == 0xeb) 599 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 600 else 601 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 602 splx(s); 603 #if 0 604 aprint_normal("%s: port %d: device present, speed: %s\n", 605 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 606 sata_speed(sstatus)); 607 #endif 608 break; 609 610 default: 611 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 612 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 613 sstatus); 614 } 615 } 616
Indexes created Fri Oct 03 02:09:57 GMT 2025