pdcsata.c revision 1.3.2.4
1 /* $NetBSD: pdcsata.c,v 1.3.2.4 2006/08/15 10:58:22 ghen Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/malloc.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pciidereg.h> 40 #include <dev/pci/pciidevar.h> 41 #include <dev/ata/atareg.h> 42 #include <dev/ata/satavar.h> 43 #include <dev/ata/satareg.h> 44 45 #define PDC203xx_NCHANNELS 4 46 #define PDC40718_NCHANNELS 4 47 #define PDC20575_NCHANNELS 3 48 49 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 50 51 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 52 #define PDC_ERRMASK 0x00780700 53 54 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 55 static void pdc203xx_setup_channel(struct ata_channel *); 56 static void pdc203xx_irqack(struct ata_channel *); 57 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 58 static void pdc203xx_dma_start(void *,int ,int); 59 static int pdc203xx_dma_finish(void *, int, int, int); 60 static int pdcsata_pci_intr(void *); 61 static void pdcsata_do_reset(struct ata_channel *, int); 62 63 /* PDC205xx, PDC405xx and PDC407xx. but tested only pdc40718 */ 64 static void pdc205xx_drv_probe(struct ata_channel *); 65 66 static int pdcsata_match(struct device *, struct cfdata *, void *); 67 static void pdcsata_attach(struct device *, struct device *, void *); 68 69 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 70 pdcsata_match, pdcsata_attach, NULL, NULL); 71 72 static const struct pciide_product_desc pciide_pdcsata_products[] = { 73 { PCI_PRODUCT_PROMISE_PDC20318, 74 0, 75 "Promise PDC20318 SATA150 controller", 76 pdcsata_chip_map, 77 }, 78 { PCI_PRODUCT_PROMISE_PDC20319, 79 0, 80 "Promise PDC20319 SATA150 controller", 81 pdcsata_chip_map, 82 }, 83 { PCI_PRODUCT_PROMISE_PDC20371, 84 0, 85 "Promise PDC20371 SATA150 controller", 86 pdcsata_chip_map, 87 }, 88 { PCI_PRODUCT_PROMISE_PDC20375, 89 0, 90 "Promise PDC20375 SATA150 controller", 91 pdcsata_chip_map, 92 }, 93 { PCI_PRODUCT_PROMISE_PDC20376, 94 0, 95 "Promise PDC20376 SATA150 controller", 96 pdcsata_chip_map, 97 }, 98 { PCI_PRODUCT_PROMISE_PDC20377, 99 0, 100 "Promise PDC20377 SATA150 controller", 101 pdcsata_chip_map, 102 }, 103 { PCI_PRODUCT_PROMISE_PDC20378, 104 0, 105 "Promise PDC20378 SATA150 controller", 106 pdcsata_chip_map, 107 }, 108 { PCI_PRODUCT_PROMISE_PDC20379, 109 0, 110 "Promise PDC20379 SATA150 controller", 111 pdcsata_chip_map, 112 }, 113 { PCI_PRODUCT_PROMISE_PDC40518, 114 0, 115 "Promise PDC40518 SATA 150 controller", 116 pdcsata_chip_map, 117 }, 118 { PCI_PRODUCT_PROMISE_PDC40718, 119 0, 120 "Promise PDC40718 SATA300 controller", 121 pdcsata_chip_map, 122 }, 123 { PCI_PRODUCT_PROMISE_PDC40719, 124 0, 125 "Promise PDC40719 SATA300 controller", 126 pdcsata_chip_map, 127 }, 128 { PCI_PRODUCT_PROMISE_PDC20571, 129 0, 130 "Promise PDC20571 SATA150 controller", 131 pdcsata_chip_map, 132 }, 133 { PCI_PRODUCT_PROMISE_PDC20575, 134 0, 135 "Promise PDC20575 SATA150 controller", 136 pdcsata_chip_map, 137 }, 138 { PCI_PRODUCT_PROMISE_PDC20579, 139 0, 140 "Promise PDC20579 SATA150 controller", 141 pdcsata_chip_map, 142 }, 143 { PCI_PRODUCT_PROMISE_PDC20771, 144 0, 145 "Promise PDC20771 SATA300 controller", 146 pdcsata_chip_map, 147 }, 148 { PCI_PRODUCT_PROMISE_PDC20775, 149 0, 150 "Promise PDC20775 SATA300 controller", 151 pdcsata_chip_map, 152 }, 153 { 0, 154 0, 155 NULL, 156 NULL 157 } 158 }; 159 160 static int 161 pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 162 { 163 struct pci_attach_args *pa = aux; 164 165 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 166 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 167 return (2); 168 } 169 return (0); 170 } 171 172 static void 173 pdcsata_attach(struct device *parent, struct device *self, void *aux) 174 { 175 struct pci_attach_args *pa = aux; 176 struct pciide_softc *sc = (struct pciide_softc *)self; 177 178 pciide_common_attach(sc, pa, 179 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 180 } 181 182 static void 183 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 184 { 185 struct pciide_channel *cp; 186 struct ata_channel *wdc_cp; 187 struct wdc_regs *wdr; 188 int channel, i; 189 bus_size_t dmasize; 190 pci_intr_handle_t intrhandle; 191 const char *intrstr; 192 193 /* 194 * Promise SATA controllers have 3 or 4 channels, 195 * the usual IDE registers are mapped in I/O space, with offsets. 196 */ 197 if (pci_intr_map(pa, &intrhandle) != 0) { 198 aprint_error("%s: couldn't map interrupt\n", 199 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 200 return; 201 } 202 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 203 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 204 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 205 206 if (sc->sc_pci_ih == NULL) { 207 aprint_error("%s: couldn't establish native-PCI interrupt", 208 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 209 if (intrstr != NULL) 210 aprint_normal(" at %s", intrstr); 211 aprint_normal("\n"); 212 return; 213 } 214 aprint_normal("%s: interrupting at %s\n", 215 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 216 intrstr ? intrstr : "unknown interrupt"); 217 218 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 219 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 220 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 221 if (!sc->sc_dma_ok) { 222 aprint_error("%s: couldn't map bus-master DMA registers\n", 223 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 224 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 225 return; 226 } 227 228 sc->sc_dmat = pa->pa_dmat; 229 230 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 231 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 232 &sc->sc_ba5_sh, NULL, NULL) != 0) { 233 aprint_error("%s: couldn't map IDE registers\n", 234 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 235 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 236 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 237 return; 238 } 239 240 aprint_normal("%s: bus-master DMA support present\n", 241 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 242 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 243 if (sc->sc_dma_ok) { 244 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 245 } 246 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 247 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 248 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 249 sc->sc_wdcdev.irqack = pdc203xx_irqack; 250 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 251 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 252 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 253 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 254 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 255 256 sc->sc_wdcdev.reset = pdcsata_do_reset; 257 258 switch (sc->sc_pp->ide_product) { 259 case PCI_PRODUCT_PROMISE_PDC20318: 260 case PCI_PRODUCT_PROMISE_PDC20319: 261 case PCI_PRODUCT_PROMISE_PDC20371: 262 case PCI_PRODUCT_PROMISE_PDC20375: 263 case PCI_PRODUCT_PROMISE_PDC20376: 264 case PCI_PRODUCT_PROMISE_PDC20377: 265 case PCI_PRODUCT_PROMISE_PDC20378: 266 case PCI_PRODUCT_PROMISE_PDC20379: 267 default: 268 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 0x00ff0033); 269 sc->sc_wdcdev.sc_atac.atac_nchannels = 270 (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 271 PDC203xx_NCHANNELS : 3; 272 273 break; 274 275 case PCI_PRODUCT_PROMISE_PDC40518: 276 case PCI_PRODUCT_PROMISE_PDC40718: 277 case PCI_PRODUCT_PROMISE_PDC40719: 278 case PCI_PRODUCT_PROMISE_PDC20571: 279 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 280 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_NCHANNELS; 281 282 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 283 284 break; 285 case PCI_PRODUCT_PROMISE_PDC20575: 286 case PCI_PRODUCT_PROMISE_PDC20579: 287 case PCI_PRODUCT_PROMISE_PDC20771: 288 case PCI_PRODUCT_PROMISE_PDC20775: 289 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 290 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_NCHANNELS; 291 292 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 293 294 break; 295 } 296 297 wdc_allocate_regs(&sc->sc_wdcdev); 298 299 sc->sc_wdcdev.dma_arg = sc; 300 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 301 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 302 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 303 304 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 305 channel++) { 306 cp = &sc->pciide_channels[channel]; 307 sc->wdc_chanarray[channel] = &cp->ata_channel; 308 309 cp->ih = sc->sc_pci_ih; 310 cp->name = NULL; 311 cp->ata_channel.ch_channel = channel; 312 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 313 cp->ata_channel.ch_queue = 314 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 315 if (cp->ata_channel.ch_queue == NULL) { 316 aprint_error("%s channel %d: " 317 "can't allocate memory for command queue\n", 318 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 319 goto next_channel; 320 } 321 wdc_cp = &cp->ata_channel; 322 wdr = CHAN_TO_WDC_REGS(wdc_cp); 323 324 wdr->ctl_iot = sc->sc_ba5_st; 325 wdr->cmd_iot = sc->sc_ba5_st; 326 327 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 328 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 329 aprint_error("%s: couldn't map channel %d ctl regs\n", 330 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 331 channel); 332 goto next_channel; 333 } 334 for (i = 0; i < WDC_NREG; i++) { 335 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 336 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 337 &wdr->cmd_iohs[i]) != 0) { 338 aprint_error("%s: couldn't map channel %d cmd " 339 "regs\n", 340 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 341 channel); 342 goto next_channel; 343 } 344 } 345 wdc_init_shadow_regs(wdc_cp); 346 347 /* 348 * subregion de busmaster registers. They're spread all over 349 * the controller's register space :(. They are also 4 bytes 350 * sized, with some specific extentions in the extra bits. 351 * It also seems that the IDEDMA_CTL register isn't available. 352 */ 353 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 354 0x260 + (channel << 7), 1, 355 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 356 aprint_normal("%s channel %d: can't subregion DMA " 357 "registers\n", 358 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 359 goto next_channel; 360 } 361 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 362 0x244 + (channel << 7), 4, 363 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 364 aprint_normal("%s channel %d: can't subregion DMA " 365 "registers\n", 366 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 367 goto next_channel; 368 } 369 370 wdcattach(wdc_cp); 371 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 372 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 373 0) & ~0x00003f9f) | (channel + 1)); 374 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 375 (channel + 1) << 2, 0x00000001); 376 next_channel: 377 continue; 378 } 379 return; 380 } 381 382 static void 383 pdc203xx_setup_channel(struct ata_channel *chp) 384 { 385 struct ata_drive_datas *drvp; 386 int drive, s; 387 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 388 389 pciide_channel_dma_setup(cp); 390 391 for (drive = 0; drive < 2; drive++) { 392 drvp = &chp->ch_drive[drive]; 393 if ((drvp->drive_flags & DRIVE) == 0) 394 continue; 395 if (drvp->drive_flags & DRIVE_UDMA) { 396 s = splbio(); 397 drvp->drive_flags &= ~DRIVE_DMA; 398 splx(s); 399 } 400 } 401 } 402 403 static int 404 pdcsata_pci_intr(void *arg) 405 { 406 struct pciide_softc *sc = arg; 407 struct pciide_channel *cp; 408 struct ata_channel *wdc_cp; 409 int i, rv, crv; 410 u_int32_t scr, status, chanbase; 411 412 rv = 0; 413 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 414 if (scr == 0xffffffff) return(rv); 415 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 416 scr = scr & 0x0000ffff; 417 if (!scr) return(rv); 418 419 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 420 cp = &sc->pciide_channels[i]; 421 wdc_cp = &cp->ata_channel; 422 if (scr & (1 << (i + 1))) { 423 chanbase = PDC_CHANNELBASE(i) + 0x48; 424 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 425 if (status & PDC_ERRMASK) { 426 chanbase = PDC_CHANNELBASE(i) + 0x60; 427 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 428 status |= 0x800; 429 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 430 status &= ~0x800; 431 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 432 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 433 continue; 434 } 435 crv = wdcintr(wdc_cp); 436 if (crv == 0) { 437 printf("%s:%d: bogus intr (reg 0x%x)\n", 438 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 439 i, scr); 440 } else 441 rv = 1; 442 } 443 } 444 return rv; 445 } 446 447 static void 448 pdc203xx_irqack(struct ata_channel *chp) 449 { 450 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 451 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 452 453 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 454 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 455 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 456 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 457 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 458 } 459 460 static int 461 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 462 size_t datalen, int flags) 463 { 464 struct pciide_softc *sc = v; 465 466 return pciide_dma_dmamap_setup(sc, channel, drive, 467 databuf, datalen, flags); 468 } 469 470 static void 471 pdc203xx_dma_start(void *v, int channel, int drive) 472 { 473 struct pciide_softc *sc = v; 474 struct pciide_channel *cp = &sc->pciide_channels[channel]; 475 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 476 477 /* Write table addr */ 478 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 479 dma_maps->dmamap_table->dm_segs[0].ds_addr); 480 /* start DMA engine */ 481 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 482 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 483 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 484 } 485 486 static int 487 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 488 { 489 struct pciide_softc *sc = v; 490 struct pciide_channel *cp = &sc->pciide_channels[channel]; 491 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 492 493 /* stop DMA channel */ 494 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 495 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 496 0) & ~0x80)); 497 498 /* Unload the map of the data buffer */ 499 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 500 dma_maps->dmamap_xfer->dm_mapsize, 501 (dma_maps->dma_flags & WDC_DMA_READ) ? 502 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 503 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 504 505 return 0; 506 } 507 508 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 509 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 510 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 511 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 512 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 513 514 515 #define SCONTROL_WRITE(sc,channel,scontrol) \ 516 bus_space_write_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 517 PDC205_SCONTROL(channel), scontrol) 518 519 #define SSTATUS_READ(sc,channel) \ 520 bus_space_read_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 521 PDC205_SSTATUS(channel)) 522 523 524 525 static void 526 pdcsata_do_reset(struct ata_channel *chp, int poll) 527 { 528 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 529 int reset, status, i, chanbase; 530 531 /* reset SATA */ 532 reset = (1 << 11); 533 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 534 for (i = 0; i < 11;i ++) { 535 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 536 if (status & reset) break; 537 delay(100); 538 status |= reset; 539 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 540 } 541 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 542 status &= ~reset; 543 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 544 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 545 546 wdc_do_reset(chp, poll); 547 548 } 549 550 static void 551 pdc205xx_drv_probe(struct ata_channel *chp) 552 { 553 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 554 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 555 u_int32_t scontrol, sstatus; 556 u_int16_t scnt, sn, cl, ch; 557 int i, s; 558 559 /* XXX This should be done by other code. */ 560 for (i = 0; i < 2; i++) { 561 chp->ch_drive[i].chnl_softc = chp; 562 chp->ch_drive[i].drive = i; 563 } 564 565 SCONTROL_WRITE(sc, chp->ch_channel, 0); 566 delay(50*1000); 567 568 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 569 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 570 delay(50*1000); 571 572 scontrol &= ~SControl_DET_INIT; 573 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 574 delay(50*1000); 575 576 sstatus = SSTATUS_READ(sc,chp->ch_channel); 577 578 switch (sstatus & SStatus_DET_mask) { 579 case SStatus_DET_NODEV: 580 /* No Device; be silent. */ 581 break; 582 583 case SStatus_DET_DEV_NE: 584 aprint_error("%s: port %d: device connected, but " 585 "communication not established\n", 586 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 587 break; 588 589 case SStatus_DET_OFFLINE: 590 aprint_error("%s: port %d: PHY offline\n", 591 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 592 break; 593 594 case SStatus_DET_DEV: 595 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 596 WDSD_IBM); 597 delay(10); /* 400ns delay */ 598 scnt = bus_space_read_2(wdr->cmd_iot, 599 wdr->cmd_iohs[wd_seccnt], 0); 600 sn = bus_space_read_2(wdr->cmd_iot, 601 wdr->cmd_iohs[wd_sector], 0); 602 cl = bus_space_read_2(wdr->cmd_iot, 603 wdr->cmd_iohs[wd_cyl_lo], 0); 604 ch = bus_space_read_2(wdr->cmd_iot, 605 wdr->cmd_iohs[wd_cyl_hi], 0); 606 #if 0 607 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 608 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 609 scnt, sn, cl, ch); 610 #endif 611 /* 612 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 613 * cases we get wrong values here, so ignore it. 614 */ 615 s = splbio(); 616 if (cl == 0x14 && ch == 0xeb) 617 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 618 else 619 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 620 splx(s); 621 #if 0 622 aprint_normal("%s: port %d: device present, speed: %s\n", 623 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 624 sata_speed(sstatus)); 625 #endif 626 break; 627 628 default: 629 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 630 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 631 sstatus); 632 } 633 } 634
Indexes created Fri Oct 03 02:09:57 GMT 2025