pdcsata.c revision 1.3.4.3
1 /* $NetBSD: pdcsata.c,v 1.3.4.3 2005/04/07 16:01:57 tron Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/malloc.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pciidereg.h> 40 #include <dev/pci/pciidevar.h> 41 42 #define PDC203xx_NCHANNELS 4 43 44 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 45 46 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void pdc203xx_setup_channel(struct wdc_channel *); 48 static int pdc203xx_pci_intr(void *); 49 static void pdc203xx_irqack(struct wdc_channel *); 50 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 51 static void pdc203xx_dma_start(void *,int ,int); 52 static int pdc203xx_dma_finish(void *, int, int, int); 53 54 static int pdcsata_match(struct device *, struct cfdata *, void *); 55 static void pdcsata_attach(struct device *, struct device *, void *); 56 57 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 58 pdcsata_match, pdcsata_attach, NULL, NULL); 59 60 static const struct pciide_product_desc pciide_pdcsata_products[] = { 61 { PCI_PRODUCT_PROMISE_PDC20318, 62 0, 63 "Promise PDC20318 SATA150 controller", 64 pdcsata_chip_map, 65 }, 66 { PCI_PRODUCT_PROMISE_PDC20319, 67 0, 68 "Promise PDC20319 SATA150 controller", 69 pdcsata_chip_map, 70 }, 71 { PCI_PRODUCT_PROMISE_PDC20371, 72 0, 73 "Promise PDC20371 SATA150 controller", 74 pdcsata_chip_map, 75 }, 76 { PCI_PRODUCT_PROMISE_PDC20375, 77 0, 78 "Promise PDC20375 SATA150 controller", 79 pdcsata_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_PDC20376, 82 0, 83 "Promise PDC20376 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20377, 87 0, 88 "Promise PDC20377 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20378, 92 0, 93 "Promise PDC20378 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20379, 97 0, 98 "Promise PDC20379 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { 0, 102 0, 103 NULL, 104 NULL 105 } 106 }; 107 108 static int 109 pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 110 { 111 struct pci_attach_args *pa = aux; 112 113 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 114 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 115 return (2); 116 } 117 return (0); 118 } 119 120 static void 121 pdcsata_attach(struct device *parent, struct device *self, void *aux) 122 { 123 struct pci_attach_args *pa = aux; 124 struct pciide_softc *sc = (struct pciide_softc *)self; 125 126 pciide_common_attach(sc, pa, 127 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 128 } 129 130 static void 131 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 132 { 133 struct pciide_channel *cp; 134 struct wdc_channel *wdc_cp; 135 int channel, i; 136 bus_size_t dmasize; 137 pci_intr_handle_t intrhandle; 138 const char *intrstr; 139 140 /* 141 * Promise SATA controllers have 3 or 4 channels, 142 * the usual IDE registers are mapped in I/O space, with offsets. 143 */ 144 if (pci_intr_map(pa, &intrhandle) != 0) { 145 aprint_error("%s: couldn't map interrupt\n", 146 sc->sc_wdcdev.sc_dev.dv_xname); 147 return; 148 } 149 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 150 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 151 intrhandle, IPL_BIO, pdc203xx_pci_intr, sc); 152 if (sc->sc_pci_ih == NULL) { 153 aprint_error("%s: couldn't establish native-PCI interrupt", 154 sc->sc_wdcdev.sc_dev.dv_xname); 155 if (intrstr != NULL) 156 aprint_normal(" at %s", intrstr); 157 aprint_normal("\n"); 158 return; 159 } 160 aprint_normal("%s: interrupting at %s\n", 161 sc->sc_wdcdev.sc_dev.dv_xname, 162 intrstr ? intrstr : "unknown interrupt"); 163 164 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 165 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 166 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 167 if (!sc->sc_dma_ok) { 168 aprint_error("%s: couldn't map bus-master DMA registers\n", 169 sc->sc_wdcdev.sc_dev.dv_xname); 170 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 171 return; 172 } 173 174 sc->sc_dmat = pa->pa_dmat; 175 176 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 177 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 178 &sc->sc_ba5_sh, NULL, NULL) != 0) { 179 aprint_error("%s: couldn't map IDE registers\n", 180 sc->sc_wdcdev.sc_dev.dv_xname); 181 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 182 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 183 return; 184 } 185 186 aprint_normal("%s: bus-master DMA support present\n", 187 sc->sc_wdcdev.sc_dev.dv_xname); 188 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 189 if (sc->sc_dma_ok) { 190 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 191 } 192 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 193 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 194 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 195 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 196 sc->sc_wdcdev.irqack = pdc203xx_irqack; 197 sc->sc_wdcdev.PIO_cap = 4; 198 sc->sc_wdcdev.DMA_cap = 2; 199 sc->sc_wdcdev.UDMA_cap = 6; 200 sc->sc_wdcdev.set_modes = pdc203xx_setup_channel; 201 sc->sc_wdcdev.channels = sc->wdc_chanarray; 202 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x06c, 0x00ff0033); 203 sc->sc_wdcdev.nchannels = 204 (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 205 PDC203xx_NCHANNELS : 3; 206 207 sc->sc_wdcdev.dma_arg = sc; 208 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 209 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 210 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 211 212 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 213 cp = &sc->pciide_channels[channel]; 214 sc->wdc_chanarray[channel] = &cp->wdc_channel; 215 216 cp->ih = sc->sc_pci_ih; 217 cp->name = NULL; 218 cp->wdc_channel.ch_channel = channel; 219 cp->wdc_channel.ch_wdc = &sc->sc_wdcdev; 220 cp->wdc_channel.ch_queue = 221 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 222 if (cp->wdc_channel.ch_queue == NULL) { 223 aprint_error("%s channel %d: " 224 "can't allocate memory for command queue\n", 225 sc->sc_wdcdev.sc_dev.dv_xname, channel); 226 goto next_channel; 227 } 228 wdc_cp = &cp->wdc_channel; 229 wdc_cp->ctl_iot = sc->sc_ba5_st; 230 wdc_cp->cmd_iot = sc->sc_ba5_st; 231 232 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 233 0x0238 + (channel << 7), 1, &wdc_cp->ctl_ioh) != 0) { 234 aprint_error("%s: couldn't map channel %d ctl regs\n", 235 sc->sc_wdcdev.sc_dev.dv_xname, 236 channel); 237 goto next_channel; 238 } 239 for (i = 0; i < WDC_NREG; i++) { 240 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 241 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 242 &wdc_cp->cmd_iohs[i]) != 0) { 243 aprint_error("%s: couldn't map channel %d cmd " 244 "regs\n", 245 sc->sc_wdcdev.sc_dev.dv_xname, 246 channel); 247 goto next_channel; 248 } 249 } 250 wdc_cp->cmd_iohs[wd_status] = wdc_cp->cmd_iohs[wd_command]; 251 wdc_cp->cmd_iohs[wd_features] = wdc_cp->cmd_iohs[wd_error]; 252 253 /* 254 * subregion de busmaster registers. They're spread all over 255 * the controller's register space :(. They are also 4 bytes 256 * sized, with some specific extentions in the extra bits. 257 * It also seems that the IDEDMA_CTL register isn't available. 258 */ 259 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 260 0x260 + (channel << 7), 1, 261 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 262 aprint_normal("%s channel %d: can't subregion DMA " 263 "registers\n", 264 sc->sc_wdcdev.sc_dev.dv_xname, channel); 265 goto next_channel; 266 } 267 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 268 0x244 + (channel << 7), 4, 269 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 270 aprint_normal("%s channel %d: can't subregion DMA " 271 "registers\n", 272 sc->sc_wdcdev.sc_dev.dv_xname, channel); 273 goto next_channel; 274 } 275 276 wdcattach(wdc_cp); 277 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 278 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 279 0) & ~0x00003f9f) | (channel + 1)); 280 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 281 (channel + 1) << 2, 0x00000001); 282 next_channel: 283 continue; 284 } 285 return; 286 } 287 288 static void 289 pdc203xx_setup_channel(struct wdc_channel *chp) 290 { 291 struct ata_drive_datas *drvp; 292 int drive, s; 293 struct pciide_channel *cp = (struct pciide_channel*)chp; 294 295 pciide_channel_dma_setup(cp); 296 297 for (drive = 0; drive < 2; drive++) { 298 drvp = &chp->ch_drive[drive]; 299 if ((drvp->drive_flags & DRIVE) == 0) 300 continue; 301 if (drvp->drive_flags & DRIVE_UDMA) { 302 s = splbio(); 303 drvp->drive_flags &= ~DRIVE_DMA; 304 splx(s); 305 } 306 } 307 } 308 309 static int 310 pdc203xx_pci_intr(void *arg) 311 { 312 struct pciide_softc *sc = arg; 313 struct pciide_channel *cp; 314 struct wdc_channel *wdc_cp; 315 int i, rv, crv; 316 u_int32_t scr; 317 318 rv = 0; 319 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x00040); 320 321 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 322 cp = &sc->pciide_channels[i]; 323 wdc_cp = &cp->wdc_channel; 324 if (scr & (1 << (i + 1))) { 325 crv = wdcintr(wdc_cp); 326 if (crv == 0) { 327 printf("%s:%d: bogus intr (reg 0x%x)\n", 328 sc->sc_wdcdev.sc_dev.dv_xname, 329 i, scr); 330 } else 331 rv = 1; 332 } 333 } 334 return rv; 335 } 336 337 static void 338 pdc203xx_irqack(struct wdc_channel *chp) 339 { 340 struct pciide_channel *cp = (struct pciide_channel*)chp; 341 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 342 343 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 344 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 345 0) & ~0x00003f9f) | (cp->wdc_channel.ch_channel + 1)); 346 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 347 (cp->wdc_channel.ch_channel + 1) << 2, 0x00000001); 348 } 349 350 static int 351 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 352 size_t datalen, int flags) 353 { 354 struct pciide_softc *sc = v; 355 356 return pciide_dma_dmamap_setup(sc, channel, drive, 357 databuf, datalen, flags); 358 } 359 360 static void 361 pdc203xx_dma_start(void *v, int channel, int drive) 362 { 363 struct pciide_softc *sc = v; 364 struct pciide_channel *cp = &sc->pciide_channels[channel]; 365 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 366 367 /* Write table addr */ 368 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 369 dma_maps->dmamap_table->dm_segs[0].ds_addr); 370 /* start DMA engine */ 371 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 372 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 373 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 374 } 375 376 static int 377 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 378 { 379 struct pciide_softc *sc = v; 380 struct pciide_channel *cp = &sc->pciide_channels[channel]; 381 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 382 383 /* stop DMA channel */ 384 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 385 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 386 0) & ~0x80)); 387 388 /* Unload the map of the data buffer */ 389 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 390 dma_maps->dmamap_xfer->dm_mapsize, 391 (dma_maps->dma_flags & WDC_DMA_READ) ? 392 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 393 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 394 395 return 0; 396 } 397
Indexes created Fri Oct 03 02:09:57 GMT 2025