pdcsata.c revision 1.30
1 /* $NetBSD: pdcsata.c,v 1.30 2018/12/09 11:14:02 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.30 2018/12/09 11:14:02 jdolecek Exp $"); 29 30 #include <sys/types.h> 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/ata/atareg.h> 39 #include <dev/ata/satavar.h> 40 #include <dev/ata/satareg.h> 41 42 #define PDC203xx_SATA_NCHANNELS 4 43 #define PDC203xx_COMBO_NCHANNELS 3 44 #define PDC40718_SATA_NCHANNELS 4 45 #define PDC20575_COMBO_NCHANNELS 3 46 47 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 48 49 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 50 #define PDC_ERRMASK 0x00780700 51 52 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 53 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 54 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 55 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 56 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 57 58 static void pdcsata_chip_map(struct pciide_softc *, 59 const struct pci_attach_args *); 60 static void pdc203xx_setup_channel(struct ata_channel *); 61 static void pdc203xx_irqack(struct ata_channel *); 62 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 63 static void pdc203xx_dma_start(void *,int ,int); 64 static int pdc203xx_dma_finish(void *, int, int, int); 65 static void pdc203xx_combo_probe(struct ata_channel *); 66 static int pdcsata_pci_intr(void *); 67 static void pdcsata_do_reset(struct ata_channel *, int); 68 69 static int pdcsata_match(device_t, cfdata_t, void *); 70 static void pdcsata_attach(device_t, device_t, void *); 71 72 CFATTACH_DECL_NEW(pdcsata, sizeof(struct pciide_softc), 73 pdcsata_match, pdcsata_attach, pciide_detach, NULL); 74 75 static const struct pciide_product_desc pciide_pdcsata_products[] = { 76 { PCI_PRODUCT_PROMISE_PDC20318, 77 0, 78 "Promise PDC20318 SATA150 controller", 79 pdcsata_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_PDC20319, 82 0, 83 "Promise PDC20319 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20371, 87 0, 88 "Promise PDC20371 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20375, 92 0, 93 "Promise PDC20375 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20376, 97 0, 98 "Promise PDC20376 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_PDC20377, 102 0, 103 "Promise PDC20377 SATA150 controller", 104 pdcsata_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_PDC20378, 107 0, 108 "Promise PDC20378 SATA150 controller", 109 pdcsata_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_PDC20379, 112 0, 113 "Promise PDC20379 SATA150 controller", 114 pdcsata_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_PDC40518, 117 0, 118 "Promise PDC40518 SATA150 controller", 119 pdcsata_chip_map, 120 }, 121 { PCI_PRODUCT_PROMISE_PDC40519, 122 0, 123 "Promise PDC40519 SATA 150 controller", 124 pdcsata_chip_map, 125 }, 126 { PCI_PRODUCT_PROMISE_PDC40718, 127 0, 128 "Promise PDC40718 SATA300 controller", 129 pdcsata_chip_map, 130 }, 131 { PCI_PRODUCT_PROMISE_PDC40719, 132 0, 133 "Promise PDC40719 SATA300 controller", 134 pdcsata_chip_map, 135 }, 136 { PCI_PRODUCT_PROMISE_PDC40779, 137 0, 138 "Promise PDC40779 SATA300 controller", 139 pdcsata_chip_map, 140 }, 141 { PCI_PRODUCT_PROMISE_PDC20571, 142 0, 143 "Promise PDC20571 SATA150 controller", 144 pdcsata_chip_map, 145 }, 146 { PCI_PRODUCT_PROMISE_PDC20575, 147 0, 148 "Promise PDC20575 SATA150 controller", 149 pdcsata_chip_map, 150 }, 151 { PCI_PRODUCT_PROMISE_PDC20579, 152 0, 153 "Promise PDC20579 SATA150 controller", 154 pdcsata_chip_map, 155 }, 156 { PCI_PRODUCT_PROMISE_PDC20771, 157 0, 158 "Promise PDC20771 SATA300 controller", 159 pdcsata_chip_map, 160 }, 161 { PCI_PRODUCT_PROMISE_PDC20775, 162 0, 163 "Promise PDC20775 SATA300 controller", 164 pdcsata_chip_map, 165 }, 166 { PCI_PRODUCT_PROMISE_PDC20617, 167 0, 168 "Promise PDC2020617 Ultra/133 controller", 169 pdcsata_chip_map, 170 }, 171 { PCI_PRODUCT_PROMISE_PDC20618, 172 0, 173 "Promise PDC20618 Ultra/133 controller", 174 pdcsata_chip_map, 175 }, 176 { PCI_PRODUCT_PROMISE_PDC20619, 177 0, 178 "Promise PDC20619 Ultra/133 controller", 179 pdcsata_chip_map, 180 }, 181 { PCI_PRODUCT_PROMISE_PDC20620, 182 0, 183 "Promise PDC20620 Ultra/133 controller", 184 pdcsata_chip_map, 185 }, 186 { PCI_PRODUCT_PROMISE_PDC20621, 187 0, 188 "Promise PDC20621 Ultra/133 controller", 189 pdcsata_chip_map, 190 }, 191 { 0, 192 0, 193 NULL, 194 NULL 195 } 196 }; 197 198 static int 199 pdcsata_match(device_t parent, cfdata_t match, void *aux) 200 { 201 struct pci_attach_args *pa = aux; 202 203 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 204 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 205 return (2); 206 } 207 return (0); 208 } 209 210 static void 211 pdcsata_attach(device_t parent, device_t self, void *aux) 212 { 213 struct pci_attach_args *pa = aux; 214 struct pciide_softc *sc = device_private(self); 215 216 sc->sc_wdcdev.sc_atac.atac_dev = self; 217 218 pciide_common_attach(sc, pa, 219 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 220 } 221 222 static void 223 pdcsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 224 { 225 struct pciide_channel *cp; 226 struct ata_channel *wdc_cp; 227 struct wdc_regs *wdr; 228 int channel, i; 229 pci_intr_handle_t intrhandle; 230 const char *intrstr; 231 char intrbuf[PCI_INTRSTR_LEN]; 232 233 /* 234 * Promise SATA controllers have 3 or 4 channels, 235 * the usual IDE registers are mapped in I/O space, with offsets. 236 */ 237 if (pci_intr_map(pa, &intrhandle) != 0) { 238 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 239 "couldn't map interrupt\n"); 240 return; 241 } 242 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 243 sizeof(intrbuf)); 244 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc, 245 intrhandle, IPL_BIO, pdcsata_pci_intr, sc, 246 device_xname(sc->sc_wdcdev.sc_atac.atac_dev)); 247 248 if (sc->sc_pci_ih == NULL) { 249 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 250 "couldn't establish native-PCI interrupt"); 251 if (intrstr != NULL) 252 aprint_error(" at %s", intrstr); 253 aprint_error("\n"); 254 return; 255 } 256 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 257 "interrupting at %s\n", 258 intrstr ? intrstr : "unknown interrupt"); 259 260 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 261 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 262 &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios) == 0); 263 if (!sc->sc_dma_ok) { 264 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 265 "couldn't map bus-master DMA registers\n"); 266 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 267 return; 268 } 269 270 sc->sc_dmat = pa->pa_dmat; 271 272 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 273 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 274 &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 275 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 276 "couldn't map IDE registers\n"); 277 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios); 278 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 279 return; 280 } 281 282 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 283 "bus-master DMA support present\n"); 284 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 285 if (sc->sc_dma_ok) { 286 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 287 } 288 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 289 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 290 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 291 sc->sc_wdcdev.irqack = pdc203xx_irqack; 292 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 293 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 294 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 295 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 296 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 297 sc->sc_wdcdev.wdc_maxdrives = 2; 298 299 sc->sc_wdcdev.reset = pdcsata_do_reset; 300 301 switch (sc->sc_pp->ide_product) { 302 case PCI_PRODUCT_PROMISE_PDC20318: 303 case PCI_PRODUCT_PROMISE_PDC20319: 304 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 305 0x00ff0033); 306 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 307 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_SATA_NCHANNELS; 308 sc->sc_wdcdev.wdc_maxdrives = 1; 309 break; 310 case PCI_PRODUCT_PROMISE_PDC20371: 311 case PCI_PRODUCT_PROMISE_PDC20375: 312 case PCI_PRODUCT_PROMISE_PDC20376: 313 case PCI_PRODUCT_PROMISE_PDC20377: 314 case PCI_PRODUCT_PROMISE_PDC20378: 315 case PCI_PRODUCT_PROMISE_PDC20379: 316 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 317 0x00ff0033); 318 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 319 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_COMBO_NCHANNELS; 320 break; 321 322 case PCI_PRODUCT_PROMISE_PDC40518: 323 case PCI_PRODUCT_PROMISE_PDC40519: 324 case PCI_PRODUCT_PROMISE_PDC40718: 325 case PCI_PRODUCT_PROMISE_PDC40719: 326 case PCI_PRODUCT_PROMISE_PDC40779: 327 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 328 0x00ff00ff); 329 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_SATA_NCHANNELS; 330 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 331 sc->sc_wdcdev.wdc_maxdrives = 1; 332 break; 333 334 case PCI_PRODUCT_PROMISE_PDC20571: 335 case PCI_PRODUCT_PROMISE_PDC20575: 336 case PCI_PRODUCT_PROMISE_PDC20579: 337 case PCI_PRODUCT_PROMISE_PDC20771: 338 case PCI_PRODUCT_PROMISE_PDC20775: 339 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 340 0x00ff00ff); 341 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_COMBO_NCHANNELS; 342 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 343 break; 344 345 case PCI_PRODUCT_PROMISE_PDC20617: 346 case PCI_PRODUCT_PROMISE_PDC20618: 347 case PCI_PRODUCT_PROMISE_PDC20619: 348 case PCI_PRODUCT_PROMISE_PDC20620: 349 case PCI_PRODUCT_PROMISE_PDC20621: 350 sc->sc_wdcdev.sc_atac.atac_nchannels = 351 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 352 0x48) & 0x01) ? 1 : 0) + 353 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 354 0x48) & 0x02) ? 1 : 0) + 355 2; 356 sc->sc_wdcdev.sc_atac.atac_probe = wdc_drvprobe; 357 358 default: 359 aprint_error("unknown promise product 0x%x\n", 360 sc->sc_pp->ide_product); 361 } 362 363 wdc_allocate_regs(&sc->sc_wdcdev); 364 365 sc->sc_wdcdev.dma_arg = sc; 366 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 367 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 368 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 369 370 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 371 channel++) { 372 cp = &sc->pciide_channels[channel]; 373 sc->wdc_chanarray[channel] = &cp->ata_channel; 374 375 cp->ih = sc->sc_pci_ih; 376 cp->name = NULL; 377 cp->ata_channel.ch_channel = channel; 378 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 379 380 wdc_cp = &cp->ata_channel; 381 wdr = CHAN_TO_WDC_REGS(wdc_cp); 382 383 wdr->ctl_iot = sc->sc_ba5_st; 384 wdr->cmd_iot = sc->sc_ba5_st; 385 386 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 387 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 388 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 389 "couldn't map channel %d ctl regs\n", channel); 390 goto next_channel; 391 } 392 for (i = 0; i < WDC_NREG; i++) { 393 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 394 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 395 &wdr->cmd_iohs[i]) != 0) { 396 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 397 "couldn't map channel %d cmd regs\n", 398 channel); 399 goto next_channel; 400 } 401 } 402 wdc_init_shadow_regs(wdr); 403 404 /* 405 * subregion de busmaster registers. They're spread all over 406 * the controller's register space :(. They are also 4 bytes 407 * sized, with some specific extentions in the extra bits. 408 * It also seems that the IDEDMA_CTL register isn't available. 409 */ 410 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 411 0x260 + (channel << 7), 1, 412 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 413 aprint_normal("%s channel %d: can't subregion DMA " 414 "registers\n", 415 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 416 channel); 417 goto next_channel; 418 } 419 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 420 0x244 + (channel << 7), 4, 421 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 422 aprint_normal("%s channel %d: can't subregion DMA " 423 "registers\n", 424 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 425 channel); 426 goto next_channel; 427 } 428 429 /* subregion the SATA registers */ 430 if (sc->sc_wdcdev.sc_atac.atac_probe == wdc_sataprobe || 431 (sc->sc_wdcdev.sc_atac.atac_probe == pdc203xx_combo_probe 432 && channel < 2)) { 433 wdr->sata_iot = sc->sc_ba5_st; 434 wdr->sata_baseioh = sc->sc_ba5_sh; 435 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 436 PDC205_SSTATUS(channel), 1, 437 &wdr->sata_status) != 0) { 438 aprint_error_dev( 439 sc->sc_wdcdev.sc_atac.atac_dev, 440 "couldn't map channel %d " 441 "sata_status regs\n", channel); 442 goto next_channel; 443 } 444 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 445 PDC205_SERROR(channel), 1, &wdr->sata_error) != 0) { 446 aprint_error_dev( 447 sc->sc_wdcdev.sc_atac.atac_dev, 448 "couldn't map channel %d " 449 "sata_error regs\n", channel); 450 goto next_channel; 451 } 452 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 453 PDC205_SCONTROL(channel), 1, 454 &wdr->sata_control) != 0) { 455 aprint_error_dev( 456 sc->sc_wdcdev.sc_atac.atac_dev, 457 "couldn't map channel %d " 458 "sata_control regs\n", channel); 459 goto next_channel; 460 } 461 } 462 463 wdcattach(wdc_cp); 464 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 465 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 466 0) & ~0x00003f9f) | (channel + 1)); 467 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 468 (channel + 1) << 2, 0x00000001); 469 next_channel: 470 continue; 471 } 472 return; 473 } 474 475 static void 476 pdc203xx_combo_probe(struct ata_channel *chp) 477 { 478 if (chp->ch_channel < 2) 479 wdc_sataprobe(chp); 480 else 481 wdc_drvprobe(chp); 482 } 483 484 static void 485 pdc203xx_setup_channel(struct ata_channel *chp) 486 { 487 struct ata_drive_datas *drvp; 488 int drive, s; 489 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 490 491 pciide_channel_dma_setup(cp); 492 493 for (drive = 0; drive < 2; drive++) { 494 drvp = &chp->ch_drive[drive]; 495 if (drvp->drive_type == ATA_DRIVET_NONE) 496 continue; 497 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 498 s = splbio(); 499 drvp->drive_flags &= ~ATA_DRIVE_DMA; 500 splx(s); 501 } 502 } 503 } 504 505 static int 506 pdcsata_pci_intr(void *arg) 507 { 508 struct pciide_softc *sc = arg; 509 struct pciide_channel *cp; 510 struct ata_channel *wdc_cp; 511 int i, rv, crv; 512 u_int32_t scr, status, chanbase; 513 514 rv = 0; 515 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 516 if (scr == 0xffffffff) return(rv); 517 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 518 scr = scr & 0x0000ffff; 519 if (!scr) return(rv); 520 521 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 522 cp = &sc->pciide_channels[i]; 523 wdc_cp = &cp->ata_channel; 524 if (scr & (1 << (i + 1))) { 525 chanbase = PDC_CHANNELBASE(i) + 0x48; 526 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 527 if (status & PDC_ERRMASK) { 528 chanbase = PDC_CHANNELBASE(i) + 0x60; 529 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 530 status |= 0x800; 531 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 532 status &= ~0x800; 533 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 534 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 535 continue; 536 } 537 crv = wdcintr(wdc_cp); 538 if (crv == 0) { 539 aprint_error("%s:%d: bogus intr (reg 0x%x)\n", 540 device_xname( 541 sc->sc_wdcdev.sc_atac.atac_dev), i, scr); 542 } else 543 rv = 1; 544 } 545 } 546 return rv; 547 } 548 549 static void 550 pdc203xx_irqack(struct ata_channel *chp) 551 { 552 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 553 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 554 555 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 556 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 557 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 558 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 559 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 560 } 561 562 static int 563 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 564 size_t datalen, int flags) 565 { 566 struct pciide_softc *sc = v; 567 568 return pciide_dma_dmamap_setup(sc, channel, drive, 569 databuf, datalen, flags); 570 } 571 572 static void 573 pdc203xx_dma_start(void *v, int channel, int drive) 574 { 575 struct pciide_softc *sc = v; 576 struct pciide_channel *cp = &sc->pciide_channels[channel]; 577 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 578 579 /* Write table addr */ 580 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 581 dma_maps->dmamap_table->dm_segs[0].ds_addr); 582 /* start DMA engine */ 583 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 584 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 585 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 586 } 587 588 static int 589 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 590 { 591 struct pciide_softc *sc = v; 592 struct pciide_channel *cp = &sc->pciide_channels[channel]; 593 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 594 595 /* stop DMA channel */ 596 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 597 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 598 0) & ~0x80)); 599 600 /* Unload the map of the data buffer */ 601 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 602 dma_maps->dmamap_xfer->dm_mapsize, 603 (dma_maps->dma_flags & WDC_DMA_READ) ? 604 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 605 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 606 607 return 0; 608 } 609 610 611 static void 612 pdcsata_do_reset(struct ata_channel *chp, int poll) 613 { 614 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 615 int reset, status, i, chanbase; 616 617 /* reset SATA */ 618 reset = (1 << 11); 619 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 620 for (i = 0; i < 11;i ++) { 621 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 622 if (status & reset) break; 623 delay(100); 624 status |= reset; 625 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 626 } 627 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 628 status &= ~reset; 629 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 630 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 631 632 wdc_do_reset(chp, poll); 633 } 634
Indexes created Tue Sep 30 11:09:46 GMT 2025