pdcsata.c revision 1.31
1 /* $NetBSD: pdcsata.c,v 1.31 2019/02/03 03:19:27 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.31 2019/02/03 03:19:27 mrg Exp $"); 29 30 #include <sys/types.h> 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/ata/atareg.h> 39 #include <dev/ata/satavar.h> 40 #include <dev/ata/satareg.h> 41 42 #define PDC203xx_SATA_NCHANNELS 4 43 #define PDC203xx_COMBO_NCHANNELS 3 44 #define PDC40718_SATA_NCHANNELS 4 45 #define PDC20575_COMBO_NCHANNELS 3 46 47 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 48 49 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 50 #define PDC_ERRMASK 0x00780700 51 52 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 53 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 54 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 55 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 56 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 57 58 static void pdcsata_chip_map(struct pciide_softc *, 59 const struct pci_attach_args *); 60 static void pdc203xx_setup_channel(struct ata_channel *); 61 static void pdc203xx_irqack(struct ata_channel *); 62 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 63 static void pdc203xx_dma_start(void *,int ,int); 64 static int pdc203xx_dma_finish(void *, int, int, int); 65 static void pdc203xx_combo_probe(struct ata_channel *); 66 static int pdcsata_pci_intr(void *); 67 static void pdcsata_do_reset(struct ata_channel *, int); 68 69 static int pdcsata_match(device_t, cfdata_t, void *); 70 static void pdcsata_attach(device_t, device_t, void *); 71 72 CFATTACH_DECL_NEW(pdcsata, sizeof(struct pciide_softc), 73 pdcsata_match, pdcsata_attach, pciide_detach, NULL); 74 75 static const struct pciide_product_desc pciide_pdcsata_products[] = { 76 { PCI_PRODUCT_PROMISE_PDC20318, 77 0, 78 "Promise PDC20318 SATA150 controller", 79 pdcsata_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_PDC20319, 82 0, 83 "Promise PDC20319 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20371, 87 0, 88 "Promise PDC20371 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20375, 92 0, 93 "Promise PDC20375 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20376, 97 0, 98 "Promise PDC20376 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_PDC20377, 102 0, 103 "Promise PDC20377 SATA150 controller", 104 pdcsata_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_PDC20378, 107 0, 108 "Promise PDC20378 SATA150 controller", 109 pdcsata_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_PDC20379, 112 0, 113 "Promise PDC20379 SATA150 controller", 114 pdcsata_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_PDC40518, 117 0, 118 "Promise PDC40518 SATA150 controller", 119 pdcsata_chip_map, 120 }, 121 { PCI_PRODUCT_PROMISE_PDC40519, 122 0, 123 "Promise PDC40519 SATA 150 controller", 124 pdcsata_chip_map, 125 }, 126 { PCI_PRODUCT_PROMISE_PDC40718, 127 0, 128 "Promise PDC40718 SATA300 controller", 129 pdcsata_chip_map, 130 }, 131 { PCI_PRODUCT_PROMISE_PDC40719, 132 0, 133 "Promise PDC40719 SATA300 controller", 134 pdcsata_chip_map, 135 }, 136 { PCI_PRODUCT_PROMISE_PDC40779, 137 0, 138 "Promise PDC40779 SATA300 controller", 139 pdcsata_chip_map, 140 }, 141 { PCI_PRODUCT_PROMISE_PDC20571, 142 0, 143 "Promise PDC20571 SATA150 controller", 144 pdcsata_chip_map, 145 }, 146 { PCI_PRODUCT_PROMISE_PDC20575, 147 0, 148 "Promise PDC20575 SATA150 controller", 149 pdcsata_chip_map, 150 }, 151 { PCI_PRODUCT_PROMISE_PDC20579, 152 0, 153 "Promise PDC20579 SATA150 controller", 154 pdcsata_chip_map, 155 }, 156 { PCI_PRODUCT_PROMISE_PDC20771, 157 0, 158 "Promise PDC20771 SATA300 controller", 159 pdcsata_chip_map, 160 }, 161 { PCI_PRODUCT_PROMISE_PDC20775, 162 0, 163 "Promise PDC20775 SATA300 controller", 164 pdcsata_chip_map, 165 }, 166 { PCI_PRODUCT_PROMISE_PDC20617, 167 0, 168 "Promise PDC2020617 Ultra/133 controller", 169 pdcsata_chip_map, 170 }, 171 { PCI_PRODUCT_PROMISE_PDC20618, 172 0, 173 "Promise PDC20618 Ultra/133 controller", 174 pdcsata_chip_map, 175 }, 176 { PCI_PRODUCT_PROMISE_PDC20619, 177 0, 178 "Promise PDC20619 Ultra/133 controller", 179 pdcsata_chip_map, 180 }, 181 { PCI_PRODUCT_PROMISE_PDC20620, 182 0, 183 "Promise PDC20620 Ultra/133 controller", 184 pdcsata_chip_map, 185 }, 186 { PCI_PRODUCT_PROMISE_PDC20621, 187 0, 188 "Promise PDC20621 Ultra/133 controller", 189 pdcsata_chip_map, 190 }, 191 { 0, 192 0, 193 NULL, 194 NULL 195 } 196 }; 197 198 static int 199 pdcsata_match(device_t parent, cfdata_t match, void *aux) 200 { 201 struct pci_attach_args *pa = aux; 202 203 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 204 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 205 return (2); 206 } 207 return (0); 208 } 209 210 static void 211 pdcsata_attach(device_t parent, device_t self, void *aux) 212 { 213 struct pci_attach_args *pa = aux; 214 struct pciide_softc *sc = device_private(self); 215 216 sc->sc_wdcdev.sc_atac.atac_dev = self; 217 218 pciide_common_attach(sc, pa, 219 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 220 } 221 222 static void 223 pdcsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 224 { 225 struct pciide_channel *cp; 226 struct ata_channel *wdc_cp; 227 struct wdc_regs *wdr; 228 int channel, i; 229 pci_intr_handle_t intrhandle; 230 const char *intrstr; 231 char intrbuf[PCI_INTRSTR_LEN]; 232 233 /* 234 * Promise SATA controllers have 3 or 4 channels, 235 * the usual IDE registers are mapped in I/O space, with offsets. 236 */ 237 if (pci_intr_map(pa, &intrhandle) != 0) { 238 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 239 "couldn't map interrupt\n"); 240 return; 241 } 242 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 243 sizeof(intrbuf)); 244 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc, 245 intrhandle, IPL_BIO, pdcsata_pci_intr, sc, 246 device_xname(sc->sc_wdcdev.sc_atac.atac_dev)); 247 248 if (sc->sc_pci_ih == NULL) { 249 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 250 "couldn't establish native-PCI interrupt"); 251 if (intrstr != NULL) 252 aprint_error(" at %s", intrstr); 253 aprint_error("\n"); 254 return; 255 } 256 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 257 "interrupting at %s\n", 258 intrstr ? intrstr : "unknown interrupt"); 259 260 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 261 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 262 &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios) == 0); 263 if (!sc->sc_dma_ok) { 264 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 265 "couldn't map bus-master DMA registers\n"); 266 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 267 return; 268 } 269 270 sc->sc_dmat = pa->pa_dmat; 271 272 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 273 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 274 &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 275 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 276 "couldn't map IDE registers\n"); 277 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios); 278 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 279 return; 280 } 281 282 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 283 "bus-master DMA support present\n"); 284 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 285 if (sc->sc_dma_ok) { 286 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 287 } 288 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 289 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 290 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 291 sc->sc_wdcdev.irqack = pdc203xx_irqack; 292 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 293 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 294 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 295 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 296 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 297 sc->sc_wdcdev.wdc_maxdrives = 2; 298 299 sc->sc_wdcdev.reset = pdcsata_do_reset; 300 301 switch (sc->sc_pp->ide_product) { 302 case PCI_PRODUCT_PROMISE_PDC20318: 303 case PCI_PRODUCT_PROMISE_PDC20319: 304 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 305 0x00ff0033); 306 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 307 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_SATA_NCHANNELS; 308 sc->sc_wdcdev.wdc_maxdrives = 1; 309 break; 310 case PCI_PRODUCT_PROMISE_PDC20371: 311 case PCI_PRODUCT_PROMISE_PDC20375: 312 case PCI_PRODUCT_PROMISE_PDC20376: 313 case PCI_PRODUCT_PROMISE_PDC20377: 314 case PCI_PRODUCT_PROMISE_PDC20378: 315 case PCI_PRODUCT_PROMISE_PDC20379: 316 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 317 0x00ff0033); 318 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 319 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_COMBO_NCHANNELS; 320 break; 321 322 case PCI_PRODUCT_PROMISE_PDC40518: 323 case PCI_PRODUCT_PROMISE_PDC40519: 324 case PCI_PRODUCT_PROMISE_PDC40718: 325 case PCI_PRODUCT_PROMISE_PDC40719: 326 case PCI_PRODUCT_PROMISE_PDC40779: 327 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 328 0x00ff00ff); 329 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_SATA_NCHANNELS; 330 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 331 sc->sc_wdcdev.wdc_maxdrives = 1; 332 break; 333 334 case PCI_PRODUCT_PROMISE_PDC20571: 335 case PCI_PRODUCT_PROMISE_PDC20575: 336 case PCI_PRODUCT_PROMISE_PDC20579: 337 case PCI_PRODUCT_PROMISE_PDC20771: 338 case PCI_PRODUCT_PROMISE_PDC20775: 339 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 340 0x00ff00ff); 341 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_COMBO_NCHANNELS; 342 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; 343 break; 344 345 case PCI_PRODUCT_PROMISE_PDC20617: 346 case PCI_PRODUCT_PROMISE_PDC20618: 347 case PCI_PRODUCT_PROMISE_PDC20619: 348 case PCI_PRODUCT_PROMISE_PDC20620: 349 case PCI_PRODUCT_PROMISE_PDC20621: 350 sc->sc_wdcdev.sc_atac.atac_nchannels = 351 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 352 0x48) & 0x01) ? 1 : 0) + 353 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 354 0x48) & 0x02) ? 1 : 0) + 355 2; 356 sc->sc_wdcdev.sc_atac.atac_probe = wdc_drvprobe; 357 358 /* FALLTHROUGH */ 359 default: 360 aprint_error("unknown promise product 0x%x\n", 361 sc->sc_pp->ide_product); 362 } 363 364 wdc_allocate_regs(&sc->sc_wdcdev); 365 366 sc->sc_wdcdev.dma_arg = sc; 367 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 368 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 369 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 370 371 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 372 channel++) { 373 cp = &sc->pciide_channels[channel]; 374 sc->wdc_chanarray[channel] = &cp->ata_channel; 375 376 cp->ih = sc->sc_pci_ih; 377 cp->name = NULL; 378 cp->ata_channel.ch_channel = channel; 379 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 380 381 wdc_cp = &cp->ata_channel; 382 wdr = CHAN_TO_WDC_REGS(wdc_cp); 383 384 wdr->ctl_iot = sc->sc_ba5_st; 385 wdr->cmd_iot = sc->sc_ba5_st; 386 387 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 388 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 389 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 390 "couldn't map channel %d ctl regs\n", channel); 391 goto next_channel; 392 } 393 for (i = 0; i < WDC_NREG; i++) { 394 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 395 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 396 &wdr->cmd_iohs[i]) != 0) { 397 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 398 "couldn't map channel %d cmd regs\n", 399 channel); 400 goto next_channel; 401 } 402 } 403 wdc_init_shadow_regs(wdr); 404 405 /* 406 * subregion de busmaster registers. They're spread all over 407 * the controller's register space :(. They are also 4 bytes 408 * sized, with some specific extentions in the extra bits. 409 * It also seems that the IDEDMA_CTL register isn't available. 410 */ 411 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 412 0x260 + (channel << 7), 1, 413 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 414 aprint_normal("%s channel %d: can't subregion DMA " 415 "registers\n", 416 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 417 channel); 418 goto next_channel; 419 } 420 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 421 0x244 + (channel << 7), 4, 422 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 423 aprint_normal("%s channel %d: can't subregion DMA " 424 "registers\n", 425 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 426 channel); 427 goto next_channel; 428 } 429 430 /* subregion the SATA registers */ 431 if (sc->sc_wdcdev.sc_atac.atac_probe == wdc_sataprobe || 432 (sc->sc_wdcdev.sc_atac.atac_probe == pdc203xx_combo_probe 433 && channel < 2)) { 434 wdr->sata_iot = sc->sc_ba5_st; 435 wdr->sata_baseioh = sc->sc_ba5_sh; 436 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 437 PDC205_SSTATUS(channel), 1, 438 &wdr->sata_status) != 0) { 439 aprint_error_dev( 440 sc->sc_wdcdev.sc_atac.atac_dev, 441 "couldn't map channel %d " 442 "sata_status regs\n", channel); 443 goto next_channel; 444 } 445 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 446 PDC205_SERROR(channel), 1, &wdr->sata_error) != 0) { 447 aprint_error_dev( 448 sc->sc_wdcdev.sc_atac.atac_dev, 449 "couldn't map channel %d " 450 "sata_error regs\n", channel); 451 goto next_channel; 452 } 453 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 454 PDC205_SCONTROL(channel), 1, 455 &wdr->sata_control) != 0) { 456 aprint_error_dev( 457 sc->sc_wdcdev.sc_atac.atac_dev, 458 "couldn't map channel %d " 459 "sata_control regs\n", channel); 460 goto next_channel; 461 } 462 } 463 464 wdcattach(wdc_cp); 465 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 466 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 467 0) & ~0x00003f9f) | (channel + 1)); 468 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 469 (channel + 1) << 2, 0x00000001); 470 next_channel: 471 continue; 472 } 473 return; 474 } 475 476 static void 477 pdc203xx_combo_probe(struct ata_channel *chp) 478 { 479 if (chp->ch_channel < 2) 480 wdc_sataprobe(chp); 481 else 482 wdc_drvprobe(chp); 483 } 484 485 static void 486 pdc203xx_setup_channel(struct ata_channel *chp) 487 { 488 struct ata_drive_datas *drvp; 489 int drive, s; 490 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 491 492 pciide_channel_dma_setup(cp); 493 494 for (drive = 0; drive < 2; drive++) { 495 drvp = &chp->ch_drive[drive]; 496 if (drvp->drive_type == ATA_DRIVET_NONE) 497 continue; 498 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 499 s = splbio(); 500 drvp->drive_flags &= ~ATA_DRIVE_DMA; 501 splx(s); 502 } 503 } 504 } 505 506 static int 507 pdcsata_pci_intr(void *arg) 508 { 509 struct pciide_softc *sc = arg; 510 struct pciide_channel *cp; 511 struct ata_channel *wdc_cp; 512 int i, rv, crv; 513 u_int32_t scr, status, chanbase; 514 515 rv = 0; 516 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 517 if (scr == 0xffffffff) return(rv); 518 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 519 scr = scr & 0x0000ffff; 520 if (!scr) return(rv); 521 522 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 523 cp = &sc->pciide_channels[i]; 524 wdc_cp = &cp->ata_channel; 525 if (scr & (1 << (i + 1))) { 526 chanbase = PDC_CHANNELBASE(i) + 0x48; 527 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 528 if (status & PDC_ERRMASK) { 529 chanbase = PDC_CHANNELBASE(i) + 0x60; 530 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 531 status |= 0x800; 532 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 533 status &= ~0x800; 534 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 535 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 536 continue; 537 } 538 crv = wdcintr(wdc_cp); 539 if (crv == 0) { 540 aprint_error("%s:%d: bogus intr (reg 0x%x)\n", 541 device_xname( 542 sc->sc_wdcdev.sc_atac.atac_dev), i, scr); 543 } else 544 rv = 1; 545 } 546 } 547 return rv; 548 } 549 550 static void 551 pdc203xx_irqack(struct ata_channel *chp) 552 { 553 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 554 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 555 556 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 557 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 558 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 559 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 560 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 561 } 562 563 static int 564 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 565 size_t datalen, int flags) 566 { 567 struct pciide_softc *sc = v; 568 569 return pciide_dma_dmamap_setup(sc, channel, drive, 570 databuf, datalen, flags); 571 } 572 573 static void 574 pdc203xx_dma_start(void *v, int channel, int drive) 575 { 576 struct pciide_softc *sc = v; 577 struct pciide_channel *cp = &sc->pciide_channels[channel]; 578 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 579 580 /* Write table addr */ 581 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 582 dma_maps->dmamap_table->dm_segs[0].ds_addr); 583 /* start DMA engine */ 584 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 585 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 586 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 587 } 588 589 static int 590 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 591 { 592 struct pciide_softc *sc = v; 593 struct pciide_channel *cp = &sc->pciide_channels[channel]; 594 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 595 596 /* stop DMA channel */ 597 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 598 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 599 0) & ~0x80)); 600 601 /* Unload the map of the data buffer */ 602 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 603 dma_maps->dmamap_xfer->dm_mapsize, 604 (dma_maps->dma_flags & WDC_DMA_READ) ? 605 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 606 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 607 608 return 0; 609 } 610 611 612 static void 613 pdcsata_do_reset(struct ata_channel *chp, int poll) 614 { 615 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 616 int reset, status, i, chanbase; 617 618 /* reset SATA */ 619 reset = (1 << 11); 620 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 621 for (i = 0; i < 11;i ++) { 622 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 623 if (status & reset) break; 624 delay(100); 625 status |= reset; 626 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 627 } 628 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 629 status &= ~reset; 630 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 631 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 632 633 wdc_do_reset(chp, poll); 634 } 635
Indexes created Tue Sep 30 11:09:46 GMT 2025