pdcsata.c revision 1.5
1 /* $NetBSD: pdcsata.c,v 1.5 2006/01/16 20:30:19 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/malloc.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pciidereg.h> 40 #include <dev/pci/pciidevar.h> 41 #include <dev/ata/atareg.h> 42 #include <dev/ata/satavar.h> 43 #include <dev/ata/satareg.h> 44 45 #define PDC203xx_NCHANNELS 4 46 #define PDC40718_NCHANNELS 4 47 48 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 49 50 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 51 static void pdc203xx_setup_channel(struct ata_channel *); 52 static int pdc203xx_pci_intr(void *); 53 static void pdc203xx_irqack(struct ata_channel *); 54 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 55 static void pdc203xx_dma_start(void *,int ,int); 56 static int pdc203xx_dma_finish(void *, int, int, int); 57 58 /* PDC205xx, PDC405xx and PDC407xx. but tested only pdc40718 */ 59 static int pdc205xx_pci_intr(void *); 60 static void pdc205xx_do_reset(struct ata_channel *, int); 61 static void pdc205xx_drv_probe(struct ata_channel *); 62 63 static int pdcsata_match(struct device *, struct cfdata *, void *); 64 static void pdcsata_attach(struct device *, struct device *, void *); 65 66 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 67 pdcsata_match, pdcsata_attach, NULL, NULL); 68 69 static const struct pciide_product_desc pciide_pdcsata_products[] = { 70 { PCI_PRODUCT_PROMISE_PDC20318, 71 0, 72 "Promise PDC20318 SATA150 controller", 73 pdcsata_chip_map, 74 }, 75 { PCI_PRODUCT_PROMISE_PDC20319, 76 0, 77 "Promise PDC20319 SATA150 controller", 78 pdcsata_chip_map, 79 }, 80 { PCI_PRODUCT_PROMISE_PDC20371, 81 0, 82 "Promise PDC20371 SATA150 controller", 83 pdcsata_chip_map, 84 }, 85 { PCI_PRODUCT_PROMISE_PDC20375, 86 0, 87 "Promise PDC20375 SATA150 controller", 88 pdcsata_chip_map, 89 }, 90 { PCI_PRODUCT_PROMISE_PDC20376, 91 0, 92 "Promise PDC20376 SATA150 controller", 93 pdcsata_chip_map, 94 }, 95 { PCI_PRODUCT_PROMISE_PDC20377, 96 0, 97 "Promise PDC20377 SATA150 controller", 98 pdcsata_chip_map, 99 }, 100 { PCI_PRODUCT_PROMISE_PDC20378, 101 0, 102 "Promise PDC20378 SATA150 controller", 103 pdcsata_chip_map, 104 }, 105 { PCI_PRODUCT_PROMISE_PDC20379, 106 0, 107 "Promise PDC20379 SATA150 controller", 108 pdcsata_chip_map, 109 }, 110 { PCI_PRODUCT_PROMISE_PDC40718, 111 0, 112 "Promise PDC40718 SATA300 controller", 113 pdcsata_chip_map, 114 }, 115 { PCI_PRODUCT_PROMISE_PDC40719, 116 0, 117 "Promise PDC40719 SATA300 controller", 118 pdcsata_chip_map, 119 }, 120 { 0, 121 0, 122 NULL, 123 NULL 124 } 125 }; 126 127 static int 128 pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 129 { 130 struct pci_attach_args *pa = aux; 131 132 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 133 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 134 return (2); 135 } 136 return (0); 137 } 138 139 static void 140 pdcsata_attach(struct device *parent, struct device *self, void *aux) 141 { 142 struct pci_attach_args *pa = aux; 143 struct pciide_softc *sc = (struct pciide_softc *)self; 144 145 pciide_common_attach(sc, pa, 146 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 147 } 148 149 static void 150 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 151 { 152 struct pciide_channel *cp; 153 struct ata_channel *wdc_cp; 154 struct wdc_regs *wdr; 155 int channel, i; 156 bus_size_t dmasize; 157 pci_intr_handle_t intrhandle; 158 const char *intrstr; 159 160 /* 161 * Promise SATA controllers have 3 or 4 channels, 162 * the usual IDE registers are mapped in I/O space, with offsets. 163 */ 164 if (pci_intr_map(pa, &intrhandle) != 0) { 165 aprint_error("%s: couldn't map interrupt\n", 166 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 167 return; 168 } 169 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 170 171 switch (sc->sc_pp->ide_product) { 172 case PCI_PRODUCT_PROMISE_PDC20318: 173 case PCI_PRODUCT_PROMISE_PDC20319: 174 case PCI_PRODUCT_PROMISE_PDC20371: 175 case PCI_PRODUCT_PROMISE_PDC20375: 176 case PCI_PRODUCT_PROMISE_PDC20376: 177 case PCI_PRODUCT_PROMISE_PDC20377: 178 case PCI_PRODUCT_PROMISE_PDC20378: 179 case PCI_PRODUCT_PROMISE_PDC20379: 180 default: 181 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 182 intrhandle, IPL_BIO, pdc203xx_pci_intr, sc); 183 break; 184 185 case PCI_PRODUCT_PROMISE_PDC40718: 186 case PCI_PRODUCT_PROMISE_PDC40719: 187 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 188 intrhandle, IPL_BIO, pdc205xx_pci_intr, sc); 189 break; 190 } 191 192 if (sc->sc_pci_ih == NULL) { 193 aprint_error("%s: couldn't establish native-PCI interrupt", 194 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 195 if (intrstr != NULL) 196 aprint_normal(" at %s", intrstr); 197 aprint_normal("\n"); 198 return; 199 } 200 aprint_normal("%s: interrupting at %s\n", 201 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 202 intrstr ? intrstr : "unknown interrupt"); 203 204 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 205 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 206 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 207 if (!sc->sc_dma_ok) { 208 aprint_error("%s: couldn't map bus-master DMA registers\n", 209 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 210 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 211 return; 212 } 213 214 sc->sc_dmat = pa->pa_dmat; 215 216 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 217 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 218 &sc->sc_ba5_sh, NULL, NULL) != 0) { 219 aprint_error("%s: couldn't map IDE registers\n", 220 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 221 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 222 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 223 return; 224 } 225 226 aprint_normal("%s: bus-master DMA support present\n", 227 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 228 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 229 if (sc->sc_dma_ok) { 230 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 231 } 232 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 233 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 234 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 235 sc->sc_wdcdev.irqack = pdc203xx_irqack; 236 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 237 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 238 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 239 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 240 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 241 242 switch (sc->sc_pp->ide_product) { 243 case PCI_PRODUCT_PROMISE_PDC20318: 244 case PCI_PRODUCT_PROMISE_PDC20319: 245 case PCI_PRODUCT_PROMISE_PDC20371: 246 case PCI_PRODUCT_PROMISE_PDC20375: 247 case PCI_PRODUCT_PROMISE_PDC20376: 248 case PCI_PRODUCT_PROMISE_PDC20377: 249 case PCI_PRODUCT_PROMISE_PDC20378: 250 case PCI_PRODUCT_PROMISE_PDC20379: 251 default: 252 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 0x00ff0033); 253 sc->sc_wdcdev.sc_atac.atac_nchannels = 254 (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 255 PDC203xx_NCHANNELS : 3; 256 257 break; 258 259 case PCI_PRODUCT_PROMISE_PDC40718: 260 case PCI_PRODUCT_PROMISE_PDC40719: 261 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 262 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_NCHANNELS; 263 264 sc->sc_wdcdev.reset = pdc205xx_do_reset; 265 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 266 267 break; 268 } 269 270 wdc_allocate_regs(&sc->sc_wdcdev); 271 272 sc->sc_wdcdev.dma_arg = sc; 273 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 274 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 275 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 276 277 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 278 channel++) { 279 cp = &sc->pciide_channels[channel]; 280 sc->wdc_chanarray[channel] = &cp->ata_channel; 281 282 cp->ih = sc->sc_pci_ih; 283 cp->name = NULL; 284 cp->ata_channel.ch_channel = channel; 285 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 286 cp->ata_channel.ch_queue = 287 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 288 cp->ata_channel.ch_ndrive = 2; 289 if (cp->ata_channel.ch_queue == NULL) { 290 aprint_error("%s channel %d: " 291 "can't allocate memory for command queue\n", 292 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 293 goto next_channel; 294 } 295 wdc_cp = &cp->ata_channel; 296 wdr = CHAN_TO_WDC_REGS(wdc_cp); 297 298 wdr->ctl_iot = sc->sc_ba5_st; 299 wdr->cmd_iot = sc->sc_ba5_st; 300 301 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 302 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 303 aprint_error("%s: couldn't map channel %d ctl regs\n", 304 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 305 channel); 306 goto next_channel; 307 } 308 for (i = 0; i < WDC_NREG; i++) { 309 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 310 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 311 &wdr->cmd_iohs[i]) != 0) { 312 aprint_error("%s: couldn't map channel %d cmd " 313 "regs\n", 314 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 315 channel); 316 goto next_channel; 317 } 318 } 319 wdc_init_shadow_regs(wdc_cp); 320 321 /* 322 * subregion de busmaster registers. They're spread all over 323 * the controller's register space :(. They are also 4 bytes 324 * sized, with some specific extentions in the extra bits. 325 * It also seems that the IDEDMA_CTL register isn't available. 326 */ 327 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 328 0x260 + (channel << 7), 1, 329 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 330 aprint_normal("%s channel %d: can't subregion DMA " 331 "registers\n", 332 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 333 goto next_channel; 334 } 335 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 336 0x244 + (channel << 7), 4, 337 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 338 aprint_normal("%s channel %d: can't subregion DMA " 339 "registers\n", 340 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 341 goto next_channel; 342 } 343 344 wdcattach(wdc_cp); 345 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 346 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 347 0) & ~0x00003f9f) | (channel + 1)); 348 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 349 (channel + 1) << 2, 0x00000001); 350 next_channel: 351 continue; 352 } 353 return; 354 } 355 356 static void 357 pdc203xx_setup_channel(struct ata_channel *chp) 358 { 359 struct ata_drive_datas *drvp; 360 int drive, s; 361 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 362 363 pciide_channel_dma_setup(cp); 364 365 for (drive = 0; drive < 2; drive++) { 366 drvp = &chp->ch_drive[drive]; 367 if ((drvp->drive_flags & DRIVE) == 0) 368 continue; 369 if (drvp->drive_flags & DRIVE_UDMA) { 370 s = splbio(); 371 drvp->drive_flags &= ~DRIVE_DMA; 372 splx(s); 373 } 374 } 375 } 376 377 static int 378 pdc203xx_pci_intr(void *arg) 379 { 380 struct pciide_softc *sc = arg; 381 struct pciide_channel *cp; 382 struct ata_channel *wdc_cp; 383 int i, rv, crv; 384 u_int32_t scr; 385 386 rv = 0; 387 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x00040); 388 389 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 390 cp = &sc->pciide_channels[i]; 391 wdc_cp = &cp->ata_channel; 392 if (scr & (1 << (i + 1))) { 393 crv = wdcintr(wdc_cp); 394 if (crv == 0) { 395 printf("%s:%d: bogus intr (reg 0x%x)\n", 396 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 397 i, scr); 398 } else 399 rv = 1; 400 } 401 } 402 return rv; 403 } 404 405 static int 406 pdc205xx_pci_intr(void *arg) 407 { 408 struct pciide_softc *sc = arg; 409 struct pciide_channel *cp; 410 struct ata_channel *wdc_cp; 411 int i, rv, crv; 412 u_int32_t scr, status; 413 414 rv = 0; 415 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 416 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 417 418 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60); 419 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, status & 0x000000ff); 420 421 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 422 cp = &sc->pciide_channels[i]; 423 wdc_cp = &cp->ata_channel; 424 if (scr & (1 << (i + 1))) { 425 crv = wdcintr(wdc_cp); 426 if (crv == 0) { 427 printf("%s:%d: bogus intr (reg 0x%x)\n", 428 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 429 i, scr); 430 } else 431 rv = 1; 432 } 433 } 434 return rv; 435 } 436 437 static void 438 pdc203xx_irqack(struct ata_channel *chp) 439 { 440 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 441 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 442 443 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 444 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 445 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 446 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 447 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 448 } 449 450 static int 451 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 452 size_t datalen, int flags) 453 { 454 struct pciide_softc *sc = v; 455 456 return pciide_dma_dmamap_setup(sc, channel, drive, 457 databuf, datalen, flags); 458 } 459 460 static void 461 pdc203xx_dma_start(void *v, int channel, int drive) 462 { 463 struct pciide_softc *sc = v; 464 struct pciide_channel *cp = &sc->pciide_channels[channel]; 465 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 466 467 /* Write table addr */ 468 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 469 dma_maps->dmamap_table->dm_segs[0].ds_addr); 470 /* start DMA engine */ 471 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 472 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 473 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 474 } 475 476 static int 477 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 478 { 479 struct pciide_softc *sc = v; 480 struct pciide_channel *cp = &sc->pciide_channels[channel]; 481 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 482 483 /* stop DMA channel */ 484 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 485 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 486 0) & ~0x80)); 487 488 /* Unload the map of the data buffer */ 489 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 490 dma_maps->dmamap_xfer->dm_mapsize, 491 (dma_maps->dma_flags & WDC_DMA_READ) ? 492 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 493 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 494 495 return 0; 496 } 497 498 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 499 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 500 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 501 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 502 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 503 504 505 #define SCONTROL_WRITE(sc,channel,scontrol) \ 506 bus_space_write_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 507 PDC205_SCONTROL(channel), scontrol) 508 509 #define SSTATUS_READ(sc,channel) \ 510 bus_space_read_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 511 PDC205_SSTATUS(channel)) 512 513 514 515 static void 516 pdc205xx_do_reset(struct ata_channel *chp, int poll) 517 { 518 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 519 u_int32_t scontrol; 520 521 wdc_do_reset(chp, poll); 522 523 /* reset SATA */ 524 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 525 SCONTROL_WRITE(sc, chp->ch_channel, scontrol); 526 delay(50*1000); 527 528 scontrol &= ~SControl_DET_INIT; 529 SCONTROL_WRITE(sc, chp->ch_channel, scontrol); 530 delay(50*1000); 531 } 532 533 534 535 static void 536 pdc205xx_drv_probe(struct ata_channel *chp) 537 { 538 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 539 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 540 u_int32_t scontrol, sstatus; 541 u_int16_t scnt, sn, cl, ch; 542 int i, s; 543 544 /* XXX This should be done by other code. */ 545 for (i = 0; i < 2; i++) { 546 chp->ch_drive[i].chnl_softc = chp; 547 chp->ch_drive[i].drive = i; 548 } 549 550 SCONTROL_WRITE(sc, chp->ch_channel, 0); 551 delay(50*1000); 552 553 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 554 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 555 delay(50*1000); 556 557 scontrol &= ~SControl_DET_INIT; 558 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 559 delay(50*1000); 560 561 sstatus = SSTATUS_READ(sc,chp->ch_channel); 562 563 switch (sstatus & SStatus_DET_mask) { 564 case SStatus_DET_NODEV: 565 /* No Device; be silent. */ 566 break; 567 568 case SStatus_DET_DEV_NE: 569 aprint_error("%s: port %d: device connected, but " 570 "communication not established\n", 571 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 572 break; 573 574 case SStatus_DET_OFFLINE: 575 aprint_error("%s: port %d: PHY offline\n", 576 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 577 break; 578 579 case SStatus_DET_DEV: 580 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 581 WDSD_IBM); 582 delay(10); /* 400ns delay */ 583 scnt = bus_space_read_2(wdr->cmd_iot, 584 wdr->cmd_iohs[wd_seccnt], 0); 585 sn = bus_space_read_2(wdr->cmd_iot, 586 wdr->cmd_iohs[wd_sector], 0); 587 cl = bus_space_read_2(wdr->cmd_iot, 588 wdr->cmd_iohs[wd_cyl_lo], 0); 589 ch = bus_space_read_2(wdr->cmd_iot, 590 wdr->cmd_iohs[wd_cyl_hi], 0); 591 #if 0 592 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 593 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 594 scnt, sn, cl, ch); 595 #endif 596 /* 597 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 598 * cases we get wrong values here, so ignore it. 599 */ 600 s = splbio(); 601 if (cl == 0x14 && ch == 0xeb) 602 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 603 else 604 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 605 splx(s); 606 #if 0 607 aprint_normal("%s: port %d: device present, speed: %s\n", 608 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 609 sata_speed(sstatus)); 610 #endif 611 break; 612 613 default: 614 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 615 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 616 sstatus); 617 } 618 } 619
Indexes created Tue Sep 30 11:09:46 GMT 2025