pdcsata.c revision 1.6
1 /* $NetBSD: pdcsata.c,v 1.6 2006/01/26 20:58:52 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/malloc.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pciidereg.h> 40 #include <dev/pci/pciidevar.h> 41 #include <dev/ata/atareg.h> 42 #include <dev/ata/satavar.h> 43 #include <dev/ata/satareg.h> 44 45 #define PDC203xx_NCHANNELS 4 46 #define PDC40718_NCHANNELS 4 47 #define PDC20575_NCHANNELS 3 48 49 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 50 51 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 52 static void pdc203xx_setup_channel(struct ata_channel *); 53 static int pdc203xx_pci_intr(void *); 54 static void pdc203xx_irqack(struct ata_channel *); 55 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 56 static void pdc203xx_dma_start(void *,int ,int); 57 static int pdc203xx_dma_finish(void *, int, int, int); 58 59 /* PDC205xx, PDC405xx and PDC407xx. but tested only pdc40718 */ 60 static int pdc205xx_pci_intr(void *); 61 static void pdc205xx_do_reset(struct ata_channel *, int); 62 static void pdc205xx_drv_probe(struct ata_channel *); 63 64 static int pdcsata_match(struct device *, struct cfdata *, void *); 65 static void pdcsata_attach(struct device *, struct device *, void *); 66 67 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 68 pdcsata_match, pdcsata_attach, NULL, NULL); 69 70 static const struct pciide_product_desc pciide_pdcsata_products[] = { 71 { PCI_PRODUCT_PROMISE_PDC20318, 72 0, 73 "Promise PDC20318 SATA150 controller", 74 pdcsata_chip_map, 75 }, 76 { PCI_PRODUCT_PROMISE_PDC20319, 77 0, 78 "Promise PDC20319 SATA150 controller", 79 pdcsata_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_PDC20371, 82 0, 83 "Promise PDC20371 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20375, 87 0, 88 "Promise PDC20375 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20376, 92 0, 93 "Promise PDC20376 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20377, 97 0, 98 "Promise PDC20377 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_PDC20378, 102 0, 103 "Promise PDC20378 SATA150 controller", 104 pdcsata_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_PDC20379, 107 0, 108 "Promise PDC20379 SATA150 controller", 109 pdcsata_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_PDC40718, 112 0, 113 "Promise PDC40718 SATA300 controller", 114 pdcsata_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_PDC40719, 117 0, 118 "Promise PDC40719 SATA300 controller", 119 pdcsata_chip_map, 120 }, 121 { PCI_PRODUCT_PROMISE_PDC20571, 122 0, 123 "Promise PDC20571 SATA150 controller", 124 pdcsata_chip_map, 125 }, 126 { PCI_PRODUCT_PROMISE_PDC20575, 127 0, 128 "Promise PDC20575 SATA150 controller", 129 pdcsata_chip_map, 130 }, 131 { PCI_PRODUCT_PROMISE_PDC20579, 132 0, 133 "Promise PDC20579 SATA150 controller", 134 pdcsata_chip_map, 135 }, 136 { 0, 137 0, 138 NULL, 139 NULL 140 } 141 }; 142 143 static int 144 pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 145 { 146 struct pci_attach_args *pa = aux; 147 148 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 149 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 150 return (2); 151 } 152 return (0); 153 } 154 155 static void 156 pdcsata_attach(struct device *parent, struct device *self, void *aux) 157 { 158 struct pci_attach_args *pa = aux; 159 struct pciide_softc *sc = (struct pciide_softc *)self; 160 161 pciide_common_attach(sc, pa, 162 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 163 } 164 165 static void 166 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 167 { 168 struct pciide_channel *cp; 169 struct ata_channel *wdc_cp; 170 struct wdc_regs *wdr; 171 int channel, i; 172 bus_size_t dmasize; 173 pci_intr_handle_t intrhandle; 174 const char *intrstr; 175 176 /* 177 * Promise SATA controllers have 3 or 4 channels, 178 * the usual IDE registers are mapped in I/O space, with offsets. 179 */ 180 if (pci_intr_map(pa, &intrhandle) != 0) { 181 aprint_error("%s: couldn't map interrupt\n", 182 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 183 return; 184 } 185 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 186 187 switch (sc->sc_pp->ide_product) { 188 case PCI_PRODUCT_PROMISE_PDC20318: 189 case PCI_PRODUCT_PROMISE_PDC20319: 190 case PCI_PRODUCT_PROMISE_PDC20371: 191 case PCI_PRODUCT_PROMISE_PDC20375: 192 case PCI_PRODUCT_PROMISE_PDC20376: 193 case PCI_PRODUCT_PROMISE_PDC20377: 194 case PCI_PRODUCT_PROMISE_PDC20378: 195 case PCI_PRODUCT_PROMISE_PDC20379: 196 default: 197 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 198 intrhandle, IPL_BIO, pdc203xx_pci_intr, sc); 199 break; 200 201 case PCI_PRODUCT_PROMISE_PDC40718: 202 case PCI_PRODUCT_PROMISE_PDC40719: 203 case PCI_PRODUCT_PROMISE_PDC20571: 204 case PCI_PRODUCT_PROMISE_PDC20575: 205 case PCI_PRODUCT_PROMISE_PDC20579: 206 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 207 intrhandle, IPL_BIO, pdc205xx_pci_intr, sc); 208 break; 209 } 210 211 if (sc->sc_pci_ih == NULL) { 212 aprint_error("%s: couldn't establish native-PCI interrupt", 213 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 214 if (intrstr != NULL) 215 aprint_normal(" at %s", intrstr); 216 aprint_normal("\n"); 217 return; 218 } 219 aprint_normal("%s: interrupting at %s\n", 220 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 221 intrstr ? intrstr : "unknown interrupt"); 222 223 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 224 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 225 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 226 if (!sc->sc_dma_ok) { 227 aprint_error("%s: couldn't map bus-master DMA registers\n", 228 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 229 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 230 return; 231 } 232 233 sc->sc_dmat = pa->pa_dmat; 234 235 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 236 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 237 &sc->sc_ba5_sh, NULL, NULL) != 0) { 238 aprint_error("%s: couldn't map IDE registers\n", 239 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 240 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 241 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 242 return; 243 } 244 245 aprint_normal("%s: bus-master DMA support present\n", 246 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 247 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 248 if (sc->sc_dma_ok) { 249 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 250 } 251 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 252 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 253 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 254 sc->sc_wdcdev.irqack = pdc203xx_irqack; 255 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 256 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 257 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 258 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 259 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 260 261 switch (sc->sc_pp->ide_product) { 262 case PCI_PRODUCT_PROMISE_PDC20318: 263 case PCI_PRODUCT_PROMISE_PDC20319: 264 case PCI_PRODUCT_PROMISE_PDC20371: 265 case PCI_PRODUCT_PROMISE_PDC20375: 266 case PCI_PRODUCT_PROMISE_PDC20376: 267 case PCI_PRODUCT_PROMISE_PDC20377: 268 case PCI_PRODUCT_PROMISE_PDC20378: 269 case PCI_PRODUCT_PROMISE_PDC20379: 270 default: 271 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 0x00ff0033); 272 sc->sc_wdcdev.sc_atac.atac_nchannels = 273 (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 274 PDC203xx_NCHANNELS : 3; 275 276 break; 277 278 case PCI_PRODUCT_PROMISE_PDC40718: 279 case PCI_PRODUCT_PROMISE_PDC40719: 280 case PCI_PRODUCT_PROMISE_PDC20571: 281 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 282 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_NCHANNELS; 283 284 sc->sc_wdcdev.reset = pdc205xx_do_reset; 285 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 286 287 break; 288 case PCI_PRODUCT_PROMISE_PDC20575: 289 case PCI_PRODUCT_PROMISE_PDC20579: 290 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 291 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_NCHANNELS; 292 293 sc->sc_wdcdev.reset = pdc205xx_do_reset; 294 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 295 296 break; 297 } 298 299 wdc_allocate_regs(&sc->sc_wdcdev); 300 301 sc->sc_wdcdev.dma_arg = sc; 302 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 303 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 304 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 305 306 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 307 channel++) { 308 cp = &sc->pciide_channels[channel]; 309 sc->wdc_chanarray[channel] = &cp->ata_channel; 310 311 cp->ih = sc->sc_pci_ih; 312 cp->name = NULL; 313 cp->ata_channel.ch_channel = channel; 314 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 315 cp->ata_channel.ch_queue = 316 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 317 cp->ata_channel.ch_ndrive = 2; 318 if (cp->ata_channel.ch_queue == NULL) { 319 aprint_error("%s channel %d: " 320 "can't allocate memory for command queue\n", 321 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 322 goto next_channel; 323 } 324 wdc_cp = &cp->ata_channel; 325 wdr = CHAN_TO_WDC_REGS(wdc_cp); 326 327 wdr->ctl_iot = sc->sc_ba5_st; 328 wdr->cmd_iot = sc->sc_ba5_st; 329 330 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 331 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 332 aprint_error("%s: couldn't map channel %d ctl regs\n", 333 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 334 channel); 335 goto next_channel; 336 } 337 for (i = 0; i < WDC_NREG; i++) { 338 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 339 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 340 &wdr->cmd_iohs[i]) != 0) { 341 aprint_error("%s: couldn't map channel %d cmd " 342 "regs\n", 343 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 344 channel); 345 goto next_channel; 346 } 347 } 348 wdc_init_shadow_regs(wdc_cp); 349 350 /* 351 * subregion de busmaster registers. They're spread all over 352 * the controller's register space :(. They are also 4 bytes 353 * sized, with some specific extentions in the extra bits. 354 * It also seems that the IDEDMA_CTL register isn't available. 355 */ 356 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 357 0x260 + (channel << 7), 1, 358 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 359 aprint_normal("%s channel %d: can't subregion DMA " 360 "registers\n", 361 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 362 goto next_channel; 363 } 364 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 365 0x244 + (channel << 7), 4, 366 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 367 aprint_normal("%s channel %d: can't subregion DMA " 368 "registers\n", 369 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 370 goto next_channel; 371 } 372 373 wdcattach(wdc_cp); 374 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 375 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 376 0) & ~0x00003f9f) | (channel + 1)); 377 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 378 (channel + 1) << 2, 0x00000001); 379 next_channel: 380 continue; 381 } 382 return; 383 } 384 385 static void 386 pdc203xx_setup_channel(struct ata_channel *chp) 387 { 388 struct ata_drive_datas *drvp; 389 int drive, s; 390 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 391 392 pciide_channel_dma_setup(cp); 393 394 for (drive = 0; drive < 2; drive++) { 395 drvp = &chp->ch_drive[drive]; 396 if ((drvp->drive_flags & DRIVE) == 0) 397 continue; 398 if (drvp->drive_flags & DRIVE_UDMA) { 399 s = splbio(); 400 drvp->drive_flags &= ~DRIVE_DMA; 401 splx(s); 402 } 403 } 404 } 405 406 static int 407 pdc203xx_pci_intr(void *arg) 408 { 409 struct pciide_softc *sc = arg; 410 struct pciide_channel *cp; 411 struct ata_channel *wdc_cp; 412 int i, rv, crv; 413 u_int32_t scr; 414 415 rv = 0; 416 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x00040); 417 418 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 419 cp = &sc->pciide_channels[i]; 420 wdc_cp = &cp->ata_channel; 421 if (scr & (1 << (i + 1))) { 422 crv = wdcintr(wdc_cp); 423 if (crv == 0) { 424 printf("%s:%d: bogus intr (reg 0x%x)\n", 425 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 426 i, scr); 427 } else 428 rv = 1; 429 } 430 } 431 return rv; 432 } 433 434 static int 435 pdc205xx_pci_intr(void *arg) 436 { 437 struct pciide_softc *sc = arg; 438 struct pciide_channel *cp; 439 struct ata_channel *wdc_cp; 440 int i, rv, crv; 441 u_int32_t scr, status; 442 443 rv = 0; 444 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 445 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 446 447 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60); 448 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, status & 0x000000ff); 449 450 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 451 cp = &sc->pciide_channels[i]; 452 wdc_cp = &cp->ata_channel; 453 if (scr & (1 << (i + 1))) { 454 crv = wdcintr(wdc_cp); 455 if (crv == 0) { 456 printf("%s:%d: bogus intr (reg 0x%x)\n", 457 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 458 i, scr); 459 } else 460 rv = 1; 461 } 462 } 463 return rv; 464 } 465 466 static void 467 pdc203xx_irqack(struct ata_channel *chp) 468 { 469 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 470 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 471 472 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 473 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 474 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 475 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 476 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 477 } 478 479 static int 480 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 481 size_t datalen, int flags) 482 { 483 struct pciide_softc *sc = v; 484 485 return pciide_dma_dmamap_setup(sc, channel, drive, 486 databuf, datalen, flags); 487 } 488 489 static void 490 pdc203xx_dma_start(void *v, int channel, int drive) 491 { 492 struct pciide_softc *sc = v; 493 struct pciide_channel *cp = &sc->pciide_channels[channel]; 494 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 495 496 /* Write table addr */ 497 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 498 dma_maps->dmamap_table->dm_segs[0].ds_addr); 499 /* start DMA engine */ 500 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 501 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 502 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 503 } 504 505 static int 506 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 507 { 508 struct pciide_softc *sc = v; 509 struct pciide_channel *cp = &sc->pciide_channels[channel]; 510 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 511 512 /* stop DMA channel */ 513 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 514 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 515 0) & ~0x80)); 516 517 /* Unload the map of the data buffer */ 518 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 519 dma_maps->dmamap_xfer->dm_mapsize, 520 (dma_maps->dma_flags & WDC_DMA_READ) ? 521 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 522 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 523 524 return 0; 525 } 526 527 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 528 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 529 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 530 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 531 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 532 533 534 #define SCONTROL_WRITE(sc,channel,scontrol) \ 535 bus_space_write_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 536 PDC205_SCONTROL(channel), scontrol) 537 538 #define SSTATUS_READ(sc,channel) \ 539 bus_space_read_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 540 PDC205_SSTATUS(channel)) 541 542 543 544 static void 545 pdc205xx_do_reset(struct ata_channel *chp, int poll) 546 { 547 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 548 u_int32_t scontrol; 549 550 wdc_do_reset(chp, poll); 551 552 /* reset SATA */ 553 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 554 SCONTROL_WRITE(sc, chp->ch_channel, scontrol); 555 delay(50*1000); 556 557 scontrol &= ~SControl_DET_INIT; 558 SCONTROL_WRITE(sc, chp->ch_channel, scontrol); 559 delay(50*1000); 560 } 561 562 563 564 static void 565 pdc205xx_drv_probe(struct ata_channel *chp) 566 { 567 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 568 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 569 u_int32_t scontrol, sstatus; 570 u_int16_t scnt, sn, cl, ch; 571 int i, s; 572 573 /* XXX This should be done by other code. */ 574 for (i = 0; i < 2; i++) { 575 chp->ch_drive[i].chnl_softc = chp; 576 chp->ch_drive[i].drive = i; 577 } 578 579 SCONTROL_WRITE(sc, chp->ch_channel, 0); 580 delay(50*1000); 581 582 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 583 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 584 delay(50*1000); 585 586 scontrol &= ~SControl_DET_INIT; 587 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 588 delay(50*1000); 589 590 sstatus = SSTATUS_READ(sc,chp->ch_channel); 591 592 switch (sstatus & SStatus_DET_mask) { 593 case SStatus_DET_NODEV: 594 /* No Device; be silent. */ 595 break; 596 597 case SStatus_DET_DEV_NE: 598 aprint_error("%s: port %d: device connected, but " 599 "communication not established\n", 600 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 601 break; 602 603 case SStatus_DET_OFFLINE: 604 aprint_error("%s: port %d: PHY offline\n", 605 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 606 break; 607 608 case SStatus_DET_DEV: 609 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 610 WDSD_IBM); 611 delay(10); /* 400ns delay */ 612 scnt = bus_space_read_2(wdr->cmd_iot, 613 wdr->cmd_iohs[wd_seccnt], 0); 614 sn = bus_space_read_2(wdr->cmd_iot, 615 wdr->cmd_iohs[wd_sector], 0); 616 cl = bus_space_read_2(wdr->cmd_iot, 617 wdr->cmd_iohs[wd_cyl_lo], 0); 618 ch = bus_space_read_2(wdr->cmd_iot, 619 wdr->cmd_iohs[wd_cyl_hi], 0); 620 #if 0 621 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 622 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 623 scnt, sn, cl, ch); 624 #endif 625 /* 626 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 627 * cases we get wrong values here, so ignore it. 628 */ 629 s = splbio(); 630 if (cl == 0x14 && ch == 0xeb) 631 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 632 else 633 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 634 splx(s); 635 #if 0 636 aprint_normal("%s: port %d: device present, speed: %s\n", 637 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 638 sata_speed(sstatus)); 639 #endif 640 break; 641 642 default: 643 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 644 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 645 sstatus); 646 } 647 } 648
Indexes created Mon Sep 29 21:09:56 GMT 2025