pdcsata.c revision 1.7
1 /* $NetBSD: pdcsata.c,v 1.7 2006/06/20 02:39:58 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/malloc.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pciidereg.h> 40 #include <dev/pci/pciidevar.h> 41 #include <dev/ata/atareg.h> 42 #include <dev/ata/satavar.h> 43 #include <dev/ata/satareg.h> 44 45 #define PDC203xx_NCHANNELS 4 46 #define PDC40718_NCHANNELS 4 47 #define PDC20575_NCHANNELS 3 48 49 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 50 51 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 52 #define PDC_ERRMASK 0x00780700 53 54 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 55 static void pdc203xx_setup_channel(struct ata_channel *); 56 static void pdc203xx_irqack(struct ata_channel *); 57 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 58 static void pdc203xx_dma_start(void *,int ,int); 59 static int pdc203xx_dma_finish(void *, int, int, int); 60 static int pdcsata_pci_intr(void *); 61 static void pdcsata_do_reset(struct ata_channel *, int); 62 63 /* PDC205xx, PDC405xx and PDC407xx. but tested only pdc40718 */ 64 static void pdc205xx_drv_probe(struct ata_channel *); 65 66 static int pdcsata_match(struct device *, struct cfdata *, void *); 67 static void pdcsata_attach(struct device *, struct device *, void *); 68 69 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 70 pdcsata_match, pdcsata_attach, NULL, NULL); 71 72 static const struct pciide_product_desc pciide_pdcsata_products[] = { 73 { PCI_PRODUCT_PROMISE_PDC20318, 74 0, 75 "Promise PDC20318 SATA150 controller", 76 pdcsata_chip_map, 77 }, 78 { PCI_PRODUCT_PROMISE_PDC20319, 79 0, 80 "Promise PDC20319 SATA150 controller", 81 pdcsata_chip_map, 82 }, 83 { PCI_PRODUCT_PROMISE_PDC20371, 84 0, 85 "Promise PDC20371 SATA150 controller", 86 pdcsata_chip_map, 87 }, 88 { PCI_PRODUCT_PROMISE_PDC20375, 89 0, 90 "Promise PDC20375 SATA150 controller", 91 pdcsata_chip_map, 92 }, 93 { PCI_PRODUCT_PROMISE_PDC20376, 94 0, 95 "Promise PDC20376 SATA150 controller", 96 pdcsata_chip_map, 97 }, 98 { PCI_PRODUCT_PROMISE_PDC20377, 99 0, 100 "Promise PDC20377 SATA150 controller", 101 pdcsata_chip_map, 102 }, 103 { PCI_PRODUCT_PROMISE_PDC20378, 104 0, 105 "Promise PDC20378 SATA150 controller", 106 pdcsata_chip_map, 107 }, 108 { PCI_PRODUCT_PROMISE_PDC20379, 109 0, 110 "Promise PDC20379 SATA150 controller", 111 pdcsata_chip_map, 112 }, 113 { PCI_PRODUCT_PROMISE_PDC40718, 114 0, 115 "Promise PDC40718 SATA300 controller", 116 pdcsata_chip_map, 117 }, 118 { PCI_PRODUCT_PROMISE_PDC40719, 119 0, 120 "Promise PDC40719 SATA300 controller", 121 pdcsata_chip_map, 122 }, 123 { PCI_PRODUCT_PROMISE_PDC20571, 124 0, 125 "Promise PDC20571 SATA150 controller", 126 pdcsata_chip_map, 127 }, 128 { PCI_PRODUCT_PROMISE_PDC20575, 129 0, 130 "Promise PDC20575 SATA150 controller", 131 pdcsata_chip_map, 132 }, 133 { PCI_PRODUCT_PROMISE_PDC20579, 134 0, 135 "Promise PDC20579 SATA150 controller", 136 pdcsata_chip_map, 137 }, 138 { 0, 139 0, 140 NULL, 141 NULL 142 } 143 }; 144 145 static int 146 pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 147 { 148 struct pci_attach_args *pa = aux; 149 150 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 151 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 152 return (2); 153 } 154 return (0); 155 } 156 157 static void 158 pdcsata_attach(struct device *parent, struct device *self, void *aux) 159 { 160 struct pci_attach_args *pa = aux; 161 struct pciide_softc *sc = (struct pciide_softc *)self; 162 163 pciide_common_attach(sc, pa, 164 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 165 } 166 167 static void 168 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 169 { 170 struct pciide_channel *cp; 171 struct ata_channel *wdc_cp; 172 struct wdc_regs *wdr; 173 int channel, i; 174 bus_size_t dmasize; 175 pci_intr_handle_t intrhandle; 176 const char *intrstr; 177 178 /* 179 * Promise SATA controllers have 3 or 4 channels, 180 * the usual IDE registers are mapped in I/O space, with offsets. 181 */ 182 if (pci_intr_map(pa, &intrhandle) != 0) { 183 aprint_error("%s: couldn't map interrupt\n", 184 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 185 return; 186 } 187 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 188 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 189 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 190 191 if (sc->sc_pci_ih == NULL) { 192 aprint_error("%s: couldn't establish native-PCI interrupt", 193 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 194 if (intrstr != NULL) 195 aprint_normal(" at %s", intrstr); 196 aprint_normal("\n"); 197 return; 198 } 199 aprint_normal("%s: interrupting at %s\n", 200 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 201 intrstr ? intrstr : "unknown interrupt"); 202 203 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 204 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 205 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 206 if (!sc->sc_dma_ok) { 207 aprint_error("%s: couldn't map bus-master DMA registers\n", 208 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 209 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 210 return; 211 } 212 213 sc->sc_dmat = pa->pa_dmat; 214 215 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 216 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 217 &sc->sc_ba5_sh, NULL, NULL) != 0) { 218 aprint_error("%s: couldn't map IDE registers\n", 219 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 220 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 221 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 222 return; 223 } 224 225 aprint_normal("%s: bus-master DMA support present\n", 226 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 227 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 228 if (sc->sc_dma_ok) { 229 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 230 } 231 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 232 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 233 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 234 sc->sc_wdcdev.irqack = pdc203xx_irqack; 235 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 236 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 237 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 238 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 239 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 240 241 sc->sc_wdcdev.reset = pdcsata_do_reset; 242 243 switch (sc->sc_pp->ide_product) { 244 case PCI_PRODUCT_PROMISE_PDC20318: 245 case PCI_PRODUCT_PROMISE_PDC20319: 246 case PCI_PRODUCT_PROMISE_PDC20371: 247 case PCI_PRODUCT_PROMISE_PDC20375: 248 case PCI_PRODUCT_PROMISE_PDC20376: 249 case PCI_PRODUCT_PROMISE_PDC20377: 250 case PCI_PRODUCT_PROMISE_PDC20378: 251 case PCI_PRODUCT_PROMISE_PDC20379: 252 default: 253 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 0x00ff0033); 254 sc->sc_wdcdev.sc_atac.atac_nchannels = 255 (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 256 PDC203xx_NCHANNELS : 3; 257 258 break; 259 260 case PCI_PRODUCT_PROMISE_PDC40718: 261 case PCI_PRODUCT_PROMISE_PDC40719: 262 case PCI_PRODUCT_PROMISE_PDC20571: 263 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 264 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_NCHANNELS; 265 266 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 267 268 break; 269 case PCI_PRODUCT_PROMISE_PDC20575: 270 case PCI_PRODUCT_PROMISE_PDC20579: 271 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 272 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_NCHANNELS; 273 274 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 275 276 break; 277 } 278 279 wdc_allocate_regs(&sc->sc_wdcdev); 280 281 sc->sc_wdcdev.dma_arg = sc; 282 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 283 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 284 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 285 286 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 287 channel++) { 288 cp = &sc->pciide_channels[channel]; 289 sc->wdc_chanarray[channel] = &cp->ata_channel; 290 291 cp->ih = sc->sc_pci_ih; 292 cp->name = NULL; 293 cp->ata_channel.ch_channel = channel; 294 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 295 cp->ata_channel.ch_queue = 296 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 297 cp->ata_channel.ch_ndrive = 2; 298 if (cp->ata_channel.ch_queue == NULL) { 299 aprint_error("%s channel %d: " 300 "can't allocate memory for command queue\n", 301 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 302 goto next_channel; 303 } 304 wdc_cp = &cp->ata_channel; 305 wdr = CHAN_TO_WDC_REGS(wdc_cp); 306 307 wdr->ctl_iot = sc->sc_ba5_st; 308 wdr->cmd_iot = sc->sc_ba5_st; 309 310 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 311 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 312 aprint_error("%s: couldn't map channel %d ctl regs\n", 313 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 314 channel); 315 goto next_channel; 316 } 317 for (i = 0; i < WDC_NREG; i++) { 318 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 319 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 320 &wdr->cmd_iohs[i]) != 0) { 321 aprint_error("%s: couldn't map channel %d cmd " 322 "regs\n", 323 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 324 channel); 325 goto next_channel; 326 } 327 } 328 wdc_init_shadow_regs(wdc_cp); 329 330 /* 331 * subregion de busmaster registers. They're spread all over 332 * the controller's register space :(. They are also 4 bytes 333 * sized, with some specific extentions in the extra bits. 334 * It also seems that the IDEDMA_CTL register isn't available. 335 */ 336 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 337 0x260 + (channel << 7), 1, 338 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 339 aprint_normal("%s channel %d: can't subregion DMA " 340 "registers\n", 341 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 342 goto next_channel; 343 } 344 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 345 0x244 + (channel << 7), 4, 346 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 347 aprint_normal("%s channel %d: can't subregion DMA " 348 "registers\n", 349 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 350 goto next_channel; 351 } 352 353 wdcattach(wdc_cp); 354 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 355 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 356 0) & ~0x00003f9f) | (channel + 1)); 357 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 358 (channel + 1) << 2, 0x00000001); 359 next_channel: 360 continue; 361 } 362 return; 363 } 364 365 static void 366 pdc203xx_setup_channel(struct ata_channel *chp) 367 { 368 struct ata_drive_datas *drvp; 369 int drive, s; 370 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 371 372 pciide_channel_dma_setup(cp); 373 374 for (drive = 0; drive < 2; drive++) { 375 drvp = &chp->ch_drive[drive]; 376 if ((drvp->drive_flags & DRIVE) == 0) 377 continue; 378 if (drvp->drive_flags & DRIVE_UDMA) { 379 s = splbio(); 380 drvp->drive_flags &= ~DRIVE_DMA; 381 splx(s); 382 } 383 } 384 } 385 386 static int 387 pdcsata_pci_intr(void *arg) 388 { 389 struct pciide_softc *sc = arg; 390 struct pciide_channel *cp; 391 struct ata_channel *wdc_cp; 392 int i, rv, crv; 393 u_int32_t scr, status, chanbase; 394 395 rv = 0; 396 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 397 if (scr == 0xffffffff) return(rv); 398 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 399 scr = scr & 0x0000ffff; 400 if (!scr) return(rv); 401 402 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 403 cp = &sc->pciide_channels[i]; 404 wdc_cp = &cp->ata_channel; 405 if (scr & (1 << (i + 1))) { 406 chanbase = PDC_CHANNELBASE(i) + 0x48; 407 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 408 if (status & PDC_ERRMASK) { 409 chanbase = PDC_CHANNELBASE(i) + 0x60; 410 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 411 status |= 0x800; 412 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 413 status &= ~0x800; 414 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 415 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 416 continue; 417 } 418 crv = wdcintr(wdc_cp); 419 if (crv == 0) { 420 printf("%s:%d: bogus intr (reg 0x%x)\n", 421 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 422 i, scr); 423 } else 424 rv = 1; 425 } 426 } 427 return rv; 428 } 429 430 static void 431 pdc203xx_irqack(struct ata_channel *chp) 432 { 433 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 434 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 435 436 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 437 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 438 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 439 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 440 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 441 } 442 443 static int 444 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 445 size_t datalen, int flags) 446 { 447 struct pciide_softc *sc = v; 448 449 return pciide_dma_dmamap_setup(sc, channel, drive, 450 databuf, datalen, flags); 451 } 452 453 static void 454 pdc203xx_dma_start(void *v, int channel, int drive) 455 { 456 struct pciide_softc *sc = v; 457 struct pciide_channel *cp = &sc->pciide_channels[channel]; 458 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 459 460 /* Write table addr */ 461 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 462 dma_maps->dmamap_table->dm_segs[0].ds_addr); 463 /* start DMA engine */ 464 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 465 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 466 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 467 } 468 469 static int 470 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 471 { 472 struct pciide_softc *sc = v; 473 struct pciide_channel *cp = &sc->pciide_channels[channel]; 474 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 475 476 /* stop DMA channel */ 477 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 478 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 479 0) & ~0x80)); 480 481 /* Unload the map of the data buffer */ 482 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 483 dma_maps->dmamap_xfer->dm_mapsize, 484 (dma_maps->dma_flags & WDC_DMA_READ) ? 485 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 486 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 487 488 return 0; 489 } 490 491 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 492 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 493 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 494 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 495 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 496 497 498 #define SCONTROL_WRITE(sc,channel,scontrol) \ 499 bus_space_write_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 500 PDC205_SCONTROL(channel), scontrol) 501 502 #define SSTATUS_READ(sc,channel) \ 503 bus_space_read_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 504 PDC205_SSTATUS(channel)) 505 506 507 508 static void 509 pdcsata_do_reset(struct ata_channel *chp, int poll) 510 { 511 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 512 int reset, status, i, chanbase; 513 514 /* reset SATA */ 515 reset = (1 << 11); 516 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 517 for (i = 0; i < 11;i ++) { 518 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 519 if (status & reset) break; 520 delay(100); 521 status |= reset; 522 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 523 } 524 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 525 status &= ~reset; 526 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 527 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 528 529 wdc_do_reset(chp, poll); 530 531 } 532 533 static void 534 pdc205xx_drv_probe(struct ata_channel *chp) 535 { 536 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 537 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 538 u_int32_t scontrol, sstatus; 539 u_int16_t scnt, sn, cl, ch; 540 int i, s; 541 542 /* XXX This should be done by other code. */ 543 for (i = 0; i < 2; i++) { 544 chp->ch_drive[i].chnl_softc = chp; 545 chp->ch_drive[i].drive = i; 546 } 547 548 SCONTROL_WRITE(sc, chp->ch_channel, 0); 549 delay(50*1000); 550 551 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 552 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 553 delay(50*1000); 554 555 scontrol &= ~SControl_DET_INIT; 556 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 557 delay(50*1000); 558 559 sstatus = SSTATUS_READ(sc,chp->ch_channel); 560 561 switch (sstatus & SStatus_DET_mask) { 562 case SStatus_DET_NODEV: 563 /* No Device; be silent. */ 564 break; 565 566 case SStatus_DET_DEV_NE: 567 aprint_error("%s: port %d: device connected, but " 568 "communication not established\n", 569 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 570 break; 571 572 case SStatus_DET_OFFLINE: 573 aprint_error("%s: port %d: PHY offline\n", 574 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 575 break; 576 577 case SStatus_DET_DEV: 578 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 579 WDSD_IBM); 580 delay(10); /* 400ns delay */ 581 scnt = bus_space_read_2(wdr->cmd_iot, 582 wdr->cmd_iohs[wd_seccnt], 0); 583 sn = bus_space_read_2(wdr->cmd_iot, 584 wdr->cmd_iohs[wd_sector], 0); 585 cl = bus_space_read_2(wdr->cmd_iot, 586 wdr->cmd_iohs[wd_cyl_lo], 0); 587 ch = bus_space_read_2(wdr->cmd_iot, 588 wdr->cmd_iohs[wd_cyl_hi], 0); 589 #if 0 590 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 591 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 592 scnt, sn, cl, ch); 593 #endif 594 /* 595 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 596 * cases we get wrong values here, so ignore it. 597 */ 598 s = splbio(); 599 if (cl == 0x14 && ch == 0xeb) 600 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 601 else 602 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 603 splx(s); 604 #if 0 605 aprint_normal("%s: port %d: device present, speed: %s\n", 606 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 607 sata_speed(sstatus)); 608 #endif 609 break; 610 611 default: 612 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 613 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 614 sstatus); 615 } 616 } 617
Indexes created Mon Sep 29 21:09:56 GMT 2025